1]To design and simulate Half Adder and Full endmodule

Adder using gate level, behavioural and data

B. FULL ADDER
flow modeling.
1. GATE LEVEL MODELING:
1. GATE LEVEL MODELING:
module FA(sum,cout,a,b,cin);
`timescale 1ns / 1ps
input a,b,cin;
module HA(a,b,sum,carry);
output reg sum,cout;
input a,b;
wire k,l,m,n;
output wire sum,carry;
xor x1(k,a,b);
// XOR gate for Sum
xor x2(sum,k,cin);
xorx1(sum,a,b);
and a1(l,a,b);
//AND gate for carry
and a2(m,a,cin);
andx2(carry,a,b);
and a3(n,b,cin);
endmodule
or o1(cout,l,m,n);
3. DATA FLOW MODELING: endmodule
module HA(a,b,sum,carry);
input a,b; 2. DATA FLOW MODELING
output wire sum,carry; module FA(sum,cout,a,b,cin);
assign sum=a^b; input a,b,cin;
assign carry=a&b; output wire sum,cout;
endmodule assign sum=a^b^cin;
assign cout=a&b|b&cin|a&cin;
2. BEHAVIORAL MODELING: endmodule
module HA(a,b,sum,carry);
input a,b; 3. BEHAVIORAL MODELING:
output reg sum,carry; module FA(sum,cout,a,b,cin);
always @(*) input a,b,cin;
begin output reg sum,cout;
case ({a,b}) always @(a,b,cin) begin
2'b00: begin sum=0;carry=0; end case({a,b,cin})
2'b01: begin sum=1;carry=0; end 3'b000: begin sum=0;cout=0;end
2'b10: begin sum=1;carry=0; end 3'b001: begin sum=1;cout=0;end
2'b11: begin sum=0;carry=1; end 3'b010: begin sum=1;cout=0;end
endcase 3'b011: begin sum=0;cout=1;end
end 3'b100: begin sum=1;cout=0;end
endmodule 3'b101: begin sum=0;cout=1;end
TESTBENCH: 3'b110: begin sum=0;cout=1;end
`timescale 1ns / 1ps 3'b111: begin sum=1;cout=1;end
module HA_tb(); endcase
reg A,B; end
wire sum,carry; endmodule
HA uut(A,B,sum,carry); TESTBENCH:
initial begin `timescale 1ns / 1ps
A=1'b0;B=1'b0; module FA_tb();
#10 A=1'b0;B=1'b1; wire sum,cout;
#10 A=1'b1;B=1'b0; reg A,B,C;
#10 A=1'b1;B=1'b1; initial begin
end A=1'b0;B=1'b0;C=1'b0;
#100 A=1'b0;B=1'b0;C=1'b1; end
#100 A=1'b0;B=1'b1;C=1'b0; endmodule
#100 A=1'b0;B=1'b1;C=1'b1; TESTBENCH:
#100 A=1'b1;B=1'b0;C=1'b0; module Half_Sub_tb();
#100 A=1'b1;B=1'b0;C=1'b1; reg A,B;
#100 A=1'b1;B=1'b1;C=1'b0; wire diff,bor;
#100 A=1'b1;B=1'b1;C=1'b1; Half_Subuut(A,B,diff,bor);
end initial begin
FA uut(sum,cout,A,B,C); A=1'b0;B=1'b0;
endmodule #10 A=1'b0;B=1'b1;
#10 A=1'b1;B=1'b0;
2]To design and simulate Half Subtractor and
#10 A=1'b1;B=1'b1;
Full Subtractor using gate level, behavioural and
end
data flow modelling
endmodule
VERILOG CODES: B. FULL SUBTRACTOR
A. HALF SUBTRACTOR 1. GATE LEVEL MODELING:
module F_Sub(A,B,C,sub,bor);
1. GATE LEVEL MODELING:
input A,B,C;
module Half_Sub(a,b,diff,bor);
output sub,bor;
input a,b;
wire x1,x2,x3,y1,y2;
output diff,bor;
xor a1(x1,A,B);
wire k,l,m;
xor a2(sub,x1,C);
and (k,~a,b);
not a3(x2,A);
and (l,a,~b);
and a4(y1,x2,B);
or (diff,l,k);
not a5(x3,x1);
and x3(bor,~a,b);
and a6(y2,x3,C);
endmodule
or a7(bor,y1,y2);
3. DATA FLOW MODELING: endmodule
module Half_Sub(a,b,diff,bor);
2. DATA FLOW MODELING
input a,b;
module F_Sub(A,B,C,sub,bor);
output wire diff,bor;
input A,B,C;
assign diff=a^b;
output sub,bor;
assign bor=~a&b;
assign sub=A^B^C;
endmodule
assign bor=~A&B|(~(A^B))&C;
2. BEHAVIORAL MODELING:
endmodule
module Half_Sub(a,b,diff,bor);
input a,b;
output reg diff,bor; 3. BEHAVIORAL MODELING:
always@(*) module F_Sub(A,B,C,sub,bor);
begin input A,B,C;
case({a,b}) output reg sub,bor;
2'b00:begin diff=0;bor=0; end always @(A,B,C) begin
2'b01:begin diff=1;bor=1; end case({A,B,C})
2'b10:begin diff=1;bor=0; end 3'b000: begin sub=0;bor=0;end
2'b11:begin diff=0;bor=0; end 3'b001: begin sub=1;bor=1;end
endcase 3'b010: begin sub=1;bor=1;end
3'b011: begin sub=0;bor=1;end input [3:0]A;
3'b100: begin sub=1;bor=0;end input [3:0]B;
3'b101: begin sub=0;bor=0;end input Cin;
3'b110: begin sub=0;bor=0;end output [3:0]Sum;
3'b111: begin sub=1;bor=1;end output Cout;
endcase wire [2:0]c;
end FA a1(A[0],B[0],Cin,Sum[0],c[0]);
endmodule FA a2(A[1],B[1],c[0],Sum[1],c[1]);
FA a3(A[2],B[2],c[1],Sum[2],c[2]);
TESTBENCH: FA a4(A[3],B[3],c[2],Sum[3],Cout);
module F_Sub_tb(); endmodule
reg A,B,C;
wire sub,bor; TESTBENCH:
F_Subuut(A,B,C,sub,bor); module P_Add_tb;
initial begin wire Cout;
A=1'b0;B=1'b0;C=1'b0; wire [3:0]Sum;
#100 A=1'b0;B=1'b0;C=1'b1; reg [3:0]A;
#100 A=1'b0;B=1'b1;C=1'b0; reg [3:0]B;
#100 A=1'b0;B=1'b1;C=1'b1; reg Cin;
#100 A=1'b1;B=1'b0;C=1'b0; P_Add m(.A(A), .B(B), .Cin(Cin), .Sum(Sum),
#100 A=1'b1;B=1'b0;C=1'b1; .Cout(Cout));
#100 A=1'b1;B=1'b1;C=1'b0; initial
#100 A=1'b1;B=1'b1;C=1'b1; begin
end $monitor(" ",A," ",B," ",Sum," ",Cout);
endmodule A=4'b0101;
B=4'b1001;
3a]To design and simulate 4-bitParallel Adder Cin=0;
using Behavioural Modelling. #100;
end
VERILOG CODES:
endmodule
module FA(a,b,cin,sum,cout); 3b]To design and simulate 4-bitParallel
input a,b,cin; Subtractor using Behavioural Modelling.
output reg sum,cout;
always @(a,b,cin) begin VERILOG CODE:
case({a,b,cin}) module F_Sub(a,b,Bin,Diff,Bor);
3'b000: begin sum=0;cout=0;end input a,b,Bin;
3'b001: begin sum=1;cout=0;end output reg Diff,Bor;
3'b010: begin sum=1;cout=0;end always @(a,b,Bin) begin
3'b011: begin sum=0;cout=1;end case({a,b,Bin})
3'b100: begin sum=1;cout=0;end 3'b000: begin Diff=0;Bor=0;end
3'b101: begin sum=0;cout=1;end 3'b001: begin Diff=1;Bor=1;end
3'b110: begin sum=0;cout=1;end 3'b010: begin Diff=1;Bor=1;end
3'b111: begin sum=1;cout=1;end 3'b011: begin Diff=0;Bor=1;end
endcase 3'b100: begin Diff=1;Bor=0;end
end 3'b101: begin Diff=0;Bor=0;end
endmodule 3'b110: begin Diff=0;Bor=0;end
module P_Add(A,B,Cin,Sum,Cout);
3'b111: begin Diff=1;Bor=1;end FA
endcase FA1(m[1],m[2],A[1]&B[1],(A[0]&B[2]),m[0]);
end FA
endmodule FA2(m[3],m[4],(A[1]&B[2]),(A[0]&B[3]),m[2])
module P_Sub(A,B,Bin,Diff,Bor); ;
input [3:0]A; HA HA2(m[5],m[6],(A[1]&B[3]),m[4]);
input [3:0]B; HA HA3(P[2],m[14],m[1],(A[2]&B[0]));
input Bin; FA
output [3:0]Diff; FA5(m[13],m[15],m[3],(A[2]&B[1]),m[14]);
output Bor; FA
wire [2:0]c; FA4(m[12],m[16],m[5],(A[2]&B[2]),m[15]);
F_Sub a1(A[0],B[0],Bin,Diff[0],c[0]); FA FA3(m[8],m[7],m[6],(A[2]&B[3]),m[16]);
F_Sub a2(A[1],B[1],c[0],Diff[1],c[1]); HA HA4(P[3],m[11],m[13],(A[3]&B[0]));
F_Sub a3(A[2],B[2],c[1],Diff[2],c[2]); FA
F_Sub a4(A[3],B[3],c[2],Diff[3],Bor); FA8(P[4],m[10],m[12],(A[3]&B[1]),m[11]);
endmodule FA FA7(P[5],m[9],m[8],(A[3]&B[2]),m[10]);
FA FA6(P[6],P[7],m[7],(A[3]&B[3]),m[9]);
TESTBENCH: endmodule
module P_Sub_tb; module HA(sout,cout,a,b);
wire Bor; output sout,cout;
wire [3:0]Diff; input a,b;
reg [3:0]A; assign sout=a^b;
reg [3:0]B; assign cout=(a&b);
reg Bin; endmodule
P_Sub m(.A(A), .B(B), .Bin(Bin), .Diff(Diff), module FA(sout,cout,a,b,cin);
.Bor(Bor)); output sout,cout;
initial input a,b,cin;
begin assign sout=(a^b^cin);
$monitor(" ",A," ",B," ",Diff," ",Bor); assign cout=((a&b)|(a&cin)|(b&cin));
A=4'b1001; endmodule
B=4'b0101;
Bin=0; TESTBENCH:
#100; module array_multi_tb();
end reg [3:0]A;
endmodule reg [3:0]B;
4] To design and simulate 4x4 Array Multiplier. wire [7:0]P;
array_multidut(
VERILOG CODE:
.A(A),
module array_multi(P,A,B); .B(B),
output [7:0]P; .P(P)
input [3:0]A; );
input [3:0]B; initial begin
assign P[0]=(A[0]&B[0]); A=0;B=0;
wire [16:0]m; #10 A = 4'b0101; // Input A = 5
HA #10 B = 4'b0011; // Input B = 3
HA1(P[1],m[0],(A[1]&B[0]),(A[0]&B[1])); #10 A = 4'b1010; // Input A = 10
#10 B = 4'b0101; // Input B = 5
 #10 A = 4'b1111; // Input A = 15 wire [7:0] Z;
#10 B = 4'b0001; // Input B = 1 booth_multiuut (
#10 $finish; .M(M),
end .Q(Q),
endmodule .Z(Z));
5] To design and simulate 4-bit Booth initial begin
Multiplier. M = 0;
VERILOG CODE: Q = 0;#100;
module booth_multi(M, Q, Z); M=-5;
input signed [3:0] M, Q; Q=7;#100;
M=-3;
output signed [7:0] Z;
Q=7;#100;
reg signed [7:0] Z; M=5;
reg [1:0] temp; Q=6;#100;
integer i; M=4;
reg Qnm1; Q=7;#100;
reg [3:0] Y1; M=-2;
always @ (M, Q) Q=-4;#100;
begin end
Z = 8'd0; endmodule
Qnm1 = 1'd0; 6a] To design a hardware description of SR
for (i = 0; i< 4; i = i + 1) Flip-flop, D Flip-flop and test its operation.
begin VERILOG CODE:
temp = {M[i], Qnm1};
module SR_FF (
Y1 = - Q;
input clk, rst_n,
case (temp) input s,r,
2'd2 : Z [7 : 4] = Z [7 : 4] + Y1; output reg q,
2'd1 : Z [7 : 4] = Z [7 : 4] + Q; output q_bar
default : begin end );
endcase always@(posedgeclk) begin // for
Z = Z >> 1; synchronous reset
Z[7] = Z[6]; if(!rst_n) q <= 0;
Qnm1 = M[i]; else begin
end case({s,r})
if (Q == 4'd8) 2'b00: q <= q; // No change
begin 2'b01: q <= 1'b0; // reset
2'b10: q <= 1'b1; // set
Z = - Z;
2'b11: q <= 1'bx; // Invalid inputs
end
endcase
end end
endmodule end
TESTBENCH: assign q_bar = ~q;
module booth_multi_tb; endmodule
reg [3:0] M; TESTBENCH:
reg [3:0] Q;
module SR_FF_tb; module D_FF (
// Inputs input clk, rst_n,
reg clk; input d,
reg rst_n; output reg q,
reg s; output q_bar
reg r; );
// Outputs always @(posedge clk) begin
wire q; if (!rst_n) // Asynchronous reset
wire q_bar; q <= 1'b0;
SR_FF uut ( else
.clk(clk), q <= d; // D input is directly connected
.rst_n(rst_n), to the output
.s(s), end
.r(r), assign q_bar = ~q;
.q(q), endmodule
.q_bar(q_bar)
TESTBENCH:
);
// Clock generation module D_FF_tb;
always #5 clk = ~clk; // Inputs
// Stimulus reg clk;
initial begin reg rst_n;
// Initialize inputs reg d;
clk = 0; // Outputs
rst_n = 0; wire q;
s = 0; wire q_bar;
r = 0; D_FF uut (
// Apply reset .clk(clk),
#10 rst_n = 1; .rst_n(rst_n),
// Test cases .d(d),
// Case 1: No change .q(q),
#20; .q_bar(q_bar)
// Case 2: Set );
s = 1; r = 0; // Clock generation
#20; always #5 clk = ~clk;
// Case 3: Reset initial begin
s = 0; r = 1; // Initialize inputs
#20; clk = 0;
// Case 4: Invalid inputs rst_n = 0;
s = 1; r = 1; d = 0;
#20; // Apply reset
$finish; #10 rst_n = 1;
end // Test cases
endmodule // Case 1: No change (d=0)
#20;
d-flipflop
// Case 2: Set d to 1
VERILOG CODE: d = 1;
 #20; end
// Case 3: Reset endmodule
rst_n = 0;
#10; TESTBENCH:
rst_n = 1; module booth_multi_tb;
// Case 4: Set d to 0 again reg [3:0] M;
d = 0; reg [3:0] Q;
#20; wire [7:0] Z;
$finish; booth_multiuut (
end .M(M),
endmodule .Q(Q),
.Z(Z));
6b]To design a hardware description of JK initial begin
Flip-flop, T Flip-flop and test its operation M = 0;
Q = 0;#100;
VERILOG CODE: M=-5;
module booth_multi(M, Q, Z); Q=7;#100;
input signed [3:0] M, Q; M=-3;
output signed [7:0] Z; Q=7;#100;
reg signed [7:0] Z; M=5;
reg [1:0] temp; Q=6;#100;
integer i; M=4;
reg Qnm1; Q=7;#100;
M=-2;
reg [3:0] Y1;
Q=-4;#100;
always @ (M, Q) end
begin endmodule
Z = 8'd0;
Qnm1 = 1'd0; t flip-flop
for (i = 0; i< 4; i = i + 1) verilog code:
begin
temp = {M[i], Qnm1};
Y1 = - Q;
case (temp)
2'd2 : Z [7 : 4] = Z [7 : 4] + Y1;
2'd1 : Z [7 : 4] = Z [7 : 4] + Q;
default : begin end
endcase
Z = Z >> 1;
Z[7] = Z[6];
Qnm1 = M[i];
end
if (Q == 4'd8)
begin
Z = - Z;
end
module T_ff(
input t, clk, reset, initial begin
output reg q, q_bar $monitor(clk, t, q, qb, reset);
); t = 1'b1;

always @(posedge clk) begin reset = 1;

if (reset) begin clk = 1;
q = 1'b0;
q_bar = 1'b1; #10 reset = 0;
end t = 1'b0;
else begin
if (t) begin #100 reset = 0;
q = ~q; t = 1'b1;
q_bar = ~q_bar;
end #100 reset = 0;
else begin t = 1'b1;
q = q;
q_bar = q_bar; #100 reset = 0;
end t = 1'b0;
end
#100 reset = 1;
end
t = 1'b1;
endmodule
end
testbench: always #25 clk = ~clk;
module tb_T_ff;
endmodule
reg clk; 7] To design and simulate NAND gate, NOR gate
reg reset; calculate their propagation delay using simica.
reg t;
wire q;
wire qb;

T_ff tflipflop(
.clk(clk),
.reset(reset),
.t(t),
.q(q),
.q_bar(qb)
);
8] To design and simulate 2X1 MUX using
Symica and compute the delay between input
and output waveforms.

10]mod13 jkcounter
Verilog code:
module JK_flipflop (
input clk, rst_n,
input j,k,
output reg q
);
always@(negedge clk ) begin // for
9] : To design and simulate basic gates CMOS synchronous reset
Inverter, OR gate, AND gate using Symica and if(!rst_n) q <= 0;
calculate their propagation delay of input and else begin
output waveforms. case({j,k})
2'b00: q <= q; // No change
2'b01: q <= 1'b0; // reset
2'b10: q <= 1'b1; // set
2'b11: q <= ~q; // Toggle
endcase
end
end
endmodule

module counter13(input clk,rst_n,output

[3:0]q);
reg w;
always @(negedge clk)
begin
if(rst_n==0 | (~(q[0]&q[2]&q[3]))==0)
w<=0;
else
 w<=1;
end
JK_flipflop df1(clk, w, 1'b1, 1'b1, q[0]);
JK_flipflop df2(q[0], w, 1'b1, 1'b1, q[1]);
JK_flipflop df3(q[1], w, 1'b1, 1'b1, q[2]);
JK_flipflop df4(q[2], w, 1'b1, 1'b1, q[3]);
endmodule
testbench: