1.
HDL CODE TO REALIZE ALL LOGIC GATES
VERILOG SOURCE CODE:
module
logicgates1(a,b
,c);
input a;
input b;
outp
ut[6
:0]c;
assign c[0]= a & b;
assign c[1]= a | b;
assign c[2]= ~(a &b);
assign c[3]= ~(a | b);
assign c[4]= a ^ b;
assign c[5]= ~(a ^ b);
assign c[6]= ~ a;
endmodule;
Simulation output:
RESULT:
Thus the outputs of all logic gates are verified by synthesizing and simulating the
Verilog code.
2. DESIGN AND SIMULATION OF ADDERS
HALF ADDER FULL ADDERS
AIM: To develop the source code for a half adder by using verilog and obtain the simulation,
synthesis, place and route and implement into FPGA.
Program:
//dataflow model
module halfadder(A,B,s,c);
input A;
input B;
output s;
output c;
assign s=A^B;
assign c=A&B;
end module
//behavioural model
module halfadderbha(A,B,s,c);
input A;
input B;
output s;
output c;
reg s,c;
always @(A,B)
case ({A,B})
2'b00:begin s=0;c=0; end
2'b00:begin s=1;c=0; end
2'b00:begin s=1;c=0; end
2'b00:begin s=0;c=1; end
endcase
endmodule
Waveform:
Result: Thus the logic circuit for the Half adder is designed in Verilog HDL and the output is
verified.
FULL ADDER
AIM: To develop the source code for full adder by using verilog and obtain the simulation,
synthesis, place and route and implement into FPGA.
Program:
//dataflow model
module fulladder(x, y, cin, s, cout);
input x;
input y;
input cin;
output s;
output cout;
wire s1,d1,d2;
xor (s1,x,y);
xor (s,s1,cin);
and(x,y,d1);
and (s1,d1,d2);
or (cout,c1,c2);
end module
//behavioral model
module fulladderbha(x,y,cin,s,cout);
input x;
input y;
input cin;
output s;
output cout;
reg s,cout;
always @(x,y,cin)
case ({x,y,cin})
3'b000:begin s=0;cout=0; end;
3'b001:begin s=1;cout=0; end;
3'b010:begin s=1;cout=0;end;
3'b011:begin s=0;cout=1;end;
3'b100:begin s=0;cout=0;end;
3'b101:begin s=0;cout=1;end;
3'b110:begin s=0;cout=1;end;
3'b111:begin s=1;cout=1;end;
endcase;
endmodule;
Waveform:
Result: Thus the logic circuit for the Full adder is designed in Verilog HDL and the output is
verified.
3. DESIGN OF 2-TO-4 DECODER
AIM: To develop the source code for 2 to 4 decoder by using verilog and obtain the simulation,
synthesis, place and route and implement into FPGA.
VERILOG SOURCE CODE:
module decoderbehv(A, B,E,Z);
input A;
input B; input E;
output [3:0] Z;
reg [3:0] Z;
reg Abar,Bbar;
always @ (A,B,E)
begin
z[0] = (Abar&Bbar&E);
z[1] = (Abar&B&E);
z[2] = (A&Bbar&E);
z[3] = (A&B&E);
end
endmodule
RESULT: Thus the outputs of 2 to 4 decoder are verified by synthesizing and simulating the
verilog code.
4. DESIGN OF 8-TO-3 ENCODER
AIM: To develop the source code for 8 to 3 encoder by using verilog and obtain the simulation,
synthesis, place and route and implement into FPGA.
VERILOG SOURCE CODE:
//dataflow modeling
module encoder data(d,y);
input [0:7] d;
output[0:2] y;
or (y[0],d[4],d[5],d[6],d[7]);
or (y[1],d[2],d[3],d[6],d[7]);
or (y[2],d[1],d[3],d[5],d[7]);
end module
//behavioral modeling
module encoderbahv(d,Y);
input [0:7] d;
output[0:2] Y;
reg [0:2] Y;
always @(d)
case (d)
8'b00000001:Y=3'b000;
8'b00000010:Y=3'b001;
8'b00000100:Y=3'b010;
8'b00001000:Y=3'b011;
8'b00010000:Y=3'b100;
8'b00100000:Y=3'b101;
8'b01000000:Y=3'b110;
8'b10000000:Y=3'b111;
end case;
end module;
RESULT: Thus the outputs of 8 to 3 encoder are verified by synthesizing and simulating the
verilog code.
5. DESIGN OF 8 to 1 MULTIPLEXER
AIM: To develop the source code for 8 to 1 multiplexer by using verilog and obtain the
simulation, synthesis, place and route and implement into FPGA.
Verilog code
Using if statement
module mux8_1
input [7:0]D;
output [2:0]S;
output y;
input en;
reg y;
always @(en,S,D,y);
begin
if (en= =1)
begin
if (s= =000 y=D[0];
else if (s==001) D=I[1];
else if (s==001) D=I[2];
else if (s==001) D=I[3];
else if (s==001) D=I[4];
else if (s==001) D=I[5];
else if (s==001) D=I[6];
else if (s==001) D=I[7];
end;
else y=0
end;
end;
end module;
Using case statement
module mux8to1(D, s, y)
input [0:7] D;
input [0:2] s;
output [0:0] y;
reg y;
always @(D, s)
case({s})
3'b000:y=D[0];
3'b000:y=D[1];
3'b000:y=D[2];
3'b000:y=D[3];
3'b000:y=D[4];
3'b000:y=D[5];
3'b000:y=D[6];
3'b000:y=D[7];
endcase;
endmodule;
Simulation result:
RESULT: Thus the outputs of 8 to 1 Multiplexer are verified by synthesizing and simulating the
verilog code.
6. 4-BIT BINARY TO GRAY CONVERTER
AIM: To develop the source code for binary to gray converter by using verilog and obtained the
simulation, synthesis, place and route and implement into FPGA.
Behavioral Modeling:
module b2g_behv(b, g)
input [3:0] b;
output[3:0]g;
reg [3:0] g;
always@(b) begin
g[3]=b[3];
g[2]=b[3]^b[2]
;
g[1]=b[2]^b[1]
;
g[0]=b[1]^b[0]
;
end;
endmodule;
Simulation output:
RESULT: Thus the outputs of binary to gray code converter are verified by synthesizing and
simulating the verilog code.
DESIGN OF FULL ADDER USING THREE MODELLING STYLES
Dataflow Modeling:
module full add dataflow(a, b, sum,carry);
input a;
input b;
input c;
output sum; output carry;
assign #2 p=a&b;
assign#2 q=b&c;
assign#2 r=c&a;
assign#4 sum=a^b^c;
assign#4carry =(p1 | p2) | p3;
endmodule;
Behavioral Modeling:
module fuladbehavioral(a, b, c, sum, carry);
input a;
input b;
input c;
output sum;
output carry;
reg sum,carry;
reg p1,p2,p3;
always @ (a or b or c)
begin
sum = (a^b)^c;
p1=a & b;
p2=b & c;
p3=a & c;
carry=(p1 | p2) | p3;
end;
endmodule;
Structural Modeling:
module fa_struct(a, b, c, sum,carry);
input a;
input b;
input c;
output sum;
output carry;
wire t1,t2,t3,s1;
xor x1(t1a,b),
xor x2(sum,s1,c);
and a1(t1,a,b);
and a2(t2,b,c);
and a3(t3,a,c);
or o1(carry,t1,t2,t3);
endmodule;
SIMULATION OUTPUT:
RESULT: Thus the outputs of full adder using three modeling styles are verified by
synthesizing and simulating the verilog code.
9. DESIGN OF FLIP FLOPS (SR, JK, D, T)
AIM: To develop the source code for flip flops by using verilog and obtained the simulation,
synthesis, place and route and implement into FPGA.
// VERILOG CODE
module sr_ff(clk,s,r,q,qb);
input clk,s,r;
output rer q,qb;
always @(clk,s,r)
begin
if(clk==1)
begin
if(s==0 & r==1)
begin
q=0; qb=~q;
end
else if(s==1 & r==0)
begin
q=1; qb=~q;
end
else if(s==0 & r==0)
begin
q=q; qb=~q;
end
else if(s==1 & r==1)
begin
q=1'bz; qb= 1'bz;
end
end
end
endmodule
//Test bench structure
module rsff_v;
reg clk ;reg s; reg r; // Inputs
wire q; wire qb; // Outputs
// Instantiate the Unit Under Test (UUT)
ff uut ( .clk(clk), .s(s), .r(r), .q(q), .qb(qb) );
initial begin
clk = 0; s = 1; r = 0; #100; // Initialization of the Inputs
clk = 1; s = 0; r = 1; #100;
clk = 1; s = 1; r = 0; #100;
clk = 1; s = 0; r = 0; #100;
clk = 1; s = 1; r = 1; #100;
end
endmodule
Waveform:
// VERILOG CODE
module jk_ff(clk,j,k,q,qb);
input clk, j, k;
output q,qb;
reg q,qb;
always @(clk,j,k)
begin
if(clk==1)
begin
if(j==0 & k==1)
begin
q=0; qb=~q;
end
else if(j==1 & k==0)
begin
q=1; qb=~q;
end
else if(j==0 & k==0)
begin
q=q; qb=~q;
end
else if(j==1 & k==1)
q=~q; qb=~q;
end
end
endmodule
//Test bench structure
module jk_
reg clk, j, k ; // Inputs
wire q, qb; // Outputs
// Instantiate the Unit Under Test (UUT)
jk_ff uut (.clk(clk), .j(j), .k(k), .q(q), .qb(qb) );
initial begin
clk = 0; j = 0; k = 0; #100;
clk = 1; j = 1; k = 0; #100;
clk = 1; j = 0; k = 1; #100;
clk = 1; j = 0; k = 0; #100;
clk = 1; j = 1; k = 1; #100;
end
endmodule
Waveform:
// VERILOG CODE for D flip flop
module d_ff( d, clk, q, q_bar);
input d, clk;
output q, q_bar;
reg q;
reg q_bar;
always @ (posedge clk)
begin
q <= d;
q_bar <= !d;
end;
endmodule;
//Test bench structure
module cc_v;
reg d; reg clk; // Inputs
wire q; wire q_bar; // Outputs
// Instantiate the Unit Under Test (UUT)
d_ff uut (.d(d), .clk(clk), .q(q), .q_bar(q_bar) );
initial begin
d = 0; clk = 0; #100;// Initialization of Inputs
d = 0; clk = 1; #100;
d = 1; clk = 1; #100;
d = 1; clk = 0; #100;
end;
endmodule;
Waveform:
// VERILOG CODE for T flipflop
module t_ff ( T, clk, q, q_bar);
input t, clk;
output q, q_bar;
reg q;
reg q_bar;
always @ (posedge clk)
begin
q = ~t;
q_bar = ~q;
end;
endmodule;
//Test bench structure
module cc_v;
reg t; reg clk; // Inputs
wire q; wire q_bar; // Outputs
// Instantiate the Unit Under Test (UUT)
t_ff uut ( .t(t), .clk(clk), .q(q), .q_bar(q_bar) );
initial begin
t = 0;clk = 0; #100; // Initialization of Inputs
t = 0;clk = 1; #100;
t = 1;clk = 1; #100
t = 1;clk = 0; #100;
end;
endmodule;
Waveform:
Result: Design of Flip-flops(D,T,SR,JK) in xilinx tool and is verified according to the truth
table.
