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LECTURE 6
ASSOCIATED OUTPUT AND INPUT FILTER
AC WAVEFORMS CAUSED BY SWITCHING

I. SELECTING INDUCTOR AND

CAPACITOR VALUES TO MEET RIPPLE
SPECIFICATIONS FOR A GIVEN DUTY CYCLE
- L(D) & C(D)

a. L(D) FOR SPECIFIED ∆iL

,GIVEN VL DURING DTS
VL(duringDTs)
L= DTs = L(D)
2∆iL

b. C(D) FOR SPECIFIED ∆Vc,

GIVEN Vout DURING DTS
Vout DTs Vout
C= , = Iout during Ts ⇒ C=f(D)
∆V 2R R

II. DOUBLE POLE LOW PASS FILTERS

A. OUTPUT L-C FILTER C≠f(D), C∝1/fs
B. INPUT EMI FILTER, L≠f(D), L∝1/fs
STEADY STATE VOLTAGES C1 ,C2 -
CHARGE BALANCE GIVES STEADY
STATE VOLTAGES
D. RIPPLE ON INPUT FILTER
a. C1 FOR ∆VC1 SPEC
b. L1 FOR ∆IL1 SPEC
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OUTPUT AND INPUT AC WAVEFORMS CAUSED BY

SWITCHING

I. SELECTING L(D) AND C(D) IN DC FILTERS FOR PWM

CONVERTERS
A.SELECTING REQUIRED L(D) IN AN L-R FILTER
On output filters for DC POWER will outline two separate
methods to achieve SPECIFIED ∆iL LIMITS AND
REQUIRED L VALUES AS WELL AS SPECIFIED ∆vC
LIMITS AND REQUIRED C VALUES . Clearly iLin a PWM
circuit will ramp up and down around its DC level. Lets
specify ∆iL limits and find how to select L values to achieve
this.

DEFINING: The inductor current is IL(DC) + iL(RIPPLE)

and having ripple about IDC(steady-state)

Ts We find for both the buck

s.s DC and the boost:
∆iL
level
∆iL V − Vo
∆iL = DC DTs
DTs D'Ts 2L
Given in a practical case iL = 10% of idc(steady-state) and
the vdc - vo difference as known
L(FOR DESIRED ∆iL) = (VDC - Vo)DTS/2∆Il IS A LINEAR
FUNCTION OF D. This is a minimum value of L. Note
that L will increase when smaller ripple is required.
⇒ USEFUL RELATION TO SELECT L(D) :NOTE THAT
L = f(D)

EXAMPLE: For either a buck or a boost:

with: fSW = 100 kHz = 105, TS=10 µsec
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VDC - Vo IS THE VALUE ACROSS “L” DURING “D” the on

time of the power switch. Usually D does not exceed 0.9,
and its value
IF VDC - Vo = 50V, IL = 10A & ∆iL = 10%IL(DC) = 1A

50
L = L(fsw, D, CIRCUIT) ⇒ L = D10 − 5 = 250 µH *D
(2)(1)

•The proper L value to meet the required ripple spec. is set

in either the buck or the boost by required duty cycle, d.
L(max) = 250µ H for D=1.
•D WILL BE SET BY: Vo / VDC = f(D) AND f(D) IS UNIQUE
TO EACH CONVERTER TOPOLOGY AS SHOWN
BEFORE. In short, the required l will vary with d, and d will
vary with converter type for specified vout and vin.

•
OTHER L ISSUES: L ≠ f(IL) ⇒ only valid when idc + iac is
limited to below core
saturation, isat.
THE IDC LEVEL MUST BE FAR BELOW ISAT OR ∆iL
SWINGS WILL SATURATE THE CORE.

B
Bsat
SATURATE CORE—
NOTE: SATURATION
Icritical I OCCURS IF i > i(critical)
BE CAREFUL!

i > i(critical) implies H or I > H(critical) or I(critical) and µr

changes to µo suddenly. Core saturation occurs for big
current amplitudes if we are not careful. THIS CAUSES L
TO DROP IN VALUE BY 100 OR MORE.
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B
Bsat
µr µoN2
L≡
H R
⇒ FOR LARGE µr(core)
µo µo L WILL BE LARGE
µr

If b in inductor core exceeds Bsat the L value will decrease

by 10-103 at B > Bsat. This means L(i) variation occurs in a
threshold fashion, not gradually. Finally, for steady-state to
occur over the full cycle of the switch waveform ts THE NET
T
∫0 vL dt ≡ 0 . THIS MUST OCCUR, OTHERWISE THE
s

INDUCTOR CURRENT WILL GROW EACH CYCLE AND

EVENTUALLY REACH SATURATION AND
i > i(critical).

VL

V+
For an inductor in steady-
D state and well below core
saturation, the total integral
D'
V-
area vLdt over Ts is ZERO.

GIVEN THAT IN STEADY-STATE THE INDUCTOR MUST

HAVE VOLT-SEC BALANCE OVER Ts:
iL

IDC
su sd

DTs D'Ts
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In many cases the di/dt upward slope (su) ≠ downward slope

(sd) in a/sec units. this means that we must choose d and d’
so that the integral is indeed zero. That is volt-second
balance sets d values to their proper values in steady state.

di/dt SLOPE IN THE INDUCTOR IS SET BY:

upward VL/L during dts. vL is the voltage
across L during internal dts.

Downward VL/L during d’ts. VL is the voltage

across L during interval d’ts which is the switch off
time...

VL differs during dts and d’ts because the converter circuit

topology differs for dts (switch on) and d’ts (switch off) as we
will show in more detail below.
B. SELECTING C(D) IN A DC FILTER
Likewise for capacitors we have “capacitor charge balance”.
in steady state for any capacitor, Vc is fixed after the
switching period ts and not growing or decreasing in steady
state.. Vc has a dc baseline and an AC ripple.

vC
su sd
2∆vC

DTs D'Ts

Downward slope is set by IC during DTs when the switch is

on and the circuit is the on case topology.
Upward slope is set by IC during D’Ts when the switch is off
and the circuit is in the off case topology.
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If su ≠ sd then D ≠ D’for steady-state conditions to occur.

EXAMPLE: We did the single pole L-R filter now for a R-C
filter we assume vo = vdc was set by the converter f(d) and vin
vo = f(d)vin so that d is known. CONSIDER FIRST A
SINGLE POLE R-C LOW PASS FILTER driven by a current
source. this could very well be the current from an inductor
as we will show later.

Isw Isw and in

Switched C steady-state
current R Vdc
DTs D'Ts
from source
V
Output
Io ≡ dc
R
filter
FOR A SPECIFIED ∆v RIPPLE GOAL, THE VALUE OF C
DEPENDS ON fsw, D, VDC, R

First consider an interruption of current with no source

current for dts:
iout = vdc / R is drained from C initially
charged to vo = vdc.

voltage discharge
sd slope (Vdc/R)(1/C)
in V/sec units

With source current switched back on for d’ts we recharge

the capacitor above:
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Iswitch VDC  1
−   ⇐ assume net positive
C  R C
↑ ↑ current to recharge
C BACK TO Vo = VDC
active load still
current drains
drive current

su slope (Isw-Vdc/R)(1/C)
in units of V/sec

then the change in Vc is such that:

vC

Vdc 2∆vC
V  DT
∆vC ≡  DC  s
 R  2C

DTs D'Ts

GIVEN ∆VC THIS SETS “C” VALUE C IS A LINEAR D

 V  DT
FUNCTION: C ≡  DC  s = C(D)
 ∆v  2R

EXAMPLE: VDC = 20 V, fs = 100 KHz

∆V OF 10% = 2 V, R = 4 Ω

20  D10 µs 200

C=  = µF *D NOTE C IS A LINEAR
 2  (2)(4) 16
FUNCTION OF ON-TIME
DUTY CYCLE D
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•Required value of “C(D)” for specified 10% ripple on vdc

depends on D (duty cycle)
•For a given vdc output and vin as well as converter type, D is
set by the f(D) for a given converter type.
•vdc/vg = f(D) yields D to achieve that specific steady state.
•each converter topology has a unique f(d).
Ts
again ∫vL dt = 0 . if not, vc will increase until the dielectric
0
breakdown of the capacitor is reached.

C. DOUBLE POLE L-C LOW PASS FILTERS

Here we are solving the case of a series L in-between input
and output and parallel C across the load
At the output, you can calculate similiar current and voltage
ripple waveforms for both a series L and a shunt C. Again
we assume working converters set d and d’values and are
only concerned with the output ripple specifications ∆i(ac)
and ∆v(ac) and how they effect the choice of L and C in
output filters. L is in series and C is in parallel.

THIS IS A UNIQUE SITUATION WHERE SMALL RIPPLE

APPROXIMATION MUST BE USED TO GET CORRECT V
vs. t. WE ARE ABLE TO USE THIS SIMPLE
APPROXIMATION IF WE DO IT CAREFULLY.

1. First recognize that capacitor voltage ripple is affected

by the ∆iL ripple in the series charging inductor:
IL = IL(dc) + ∆iL ⇐ ∆iL was usually considered
zero before for single pole filters. Now however, ∆iL
is not considered zero.

WE SHOW FOR THE CASE BELOW ∆iL EFFECTS ∆vC

AND CANNOT BE NEGLECTED.
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C
Vsw = Vg R

In fact in steady state at the output we can say to a good

approximation:
•IL(DC) FLOWS ONLY INTO R AS C DOESN’T
ALLOW IDC
• ∆iL(ac) AT fsw FLOWS MOSTLY INTO C AND NOT R
IF ZC(fsw) << R. THEN WE CAN SIMPLIFY FILTER
ANALYSIS SO THAT ∆iL FLOWS ONLY INTO C. This
is often the case in practice.
∆iL ≡ ∆iC ⇐ ALL “L” RIPPLE ∆i FLOWS INTO “C”

So the time analysis sequence of voltage across the series

inductor is:
1. vsw = vg comes on as a step: constant voltage is
applied during dts to the left side of “L”. The right side of L is
considered fixed at vout. VL = vout(sw)-vout(dc) or vL = vg-vo

2. iL appears as a linear ramp during dts

v
∆iL = L dt or i ~ at
L
3. This current flows mostly into C causing vc to change
given ic = at is a linear function of time (ramp) then vc ~
at2 during dts
i
v C = ∫ C dt
C
WE WILL AVOID THIS COMPLEX ANALYSIS AS
FOLLOWS. Consider the vL waveform as a
unisymmetric square wave. then from vL being a
square wave ∆iL will be a ramp -
∆iL is a linear function of time( at). The area under the
i-t ramp is the charge to be dumped on the capacitor.
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We will find that the “C” VALUE TO MEET REQUIRED

RIPPLE DEPENDS ONLY ON fsw AND NOT ON D.
Vg Assuming vo varies little, this
D is the voltage waveform
t across the inductor vL for:
D' vsw(on) (DTs circuit): VL=Vg-Vo
Vsw(off)
unspecified
vsw(off) (D’Ts circuit):
VL unspecified
∆iL=∆iC
∆iC=∆iL
This voltage variation across
VL causes a ∆iL flowing
∆iL through L about IDC
∆iL
Shaded area under the
∆iL vs t curve shown is
positive QC during Ts/2. This
interval Ts/2 by symmetry will cause a ∆vC.
THE NET CHARGE
Q(DURING Ts/2) = ½*BASE(Ts/2)*HEIGHT(∆iL).
This charge change causes 2∆vc to vary across the
capacitor in the double pole L-C filter.

1 Ts
∆i
Q 2 2 L
2∆VC = =
C C

∆iL Ts
∆VC (Ripple on double pole series L / parallel C output filter) =
8C
GIVEN ∆iL AND ∆vC AS SPECIFIED BY THE DESIGN OF
THE OUTPUT SPEC’S WE CAN WRITE A SIMPLE
EXPRESSION FOR C,
∆i T 
C ≡ L  s  = f (fs ) is the relation to determine C
∆v C  8 
GIVEN THE REQUIRED ∆iL AND ∆vc RIPPLE VALUES.
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NOTE THAT UNLIKE THE PRIOR SIMPLE L-R ANC R-C

FILTERS IN L-C DOUBLE POLE FILTERS C ≠ f(D), ONLY
fs, ∆iL AND ∆vC

2. INDUCTOR AFFECTED BY ∆Vc

Previously we had a series L and parallel C between the

switched converter pulsed output and the load. A filter could
also be placed between the input to the converter and the
mains to reduce emi from entering the ac mains from the
switching waveforms at the inverter input. There are now
laws concerning emi allowed on mains.
a. EMI and EMC ISSUES

In Europe the EU regulation of allowable harmonic

pollution of the ac mains is strictly enforced for all switch
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mode power supplies. See later lectures for more details.

Never the less, a simple parallel C - series L input filter can
do wonders for reducing signals at f(switch) from entering
the mains.

On the next page we will illustrate both conducted and

radiated emissions. Both arise from the switches operating
at high frequency and carrying large switch powers.
THIS IS THE DIRTY SECRET DISADVANTAGE of the
PWM APPROACH
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To bring this all to a head we place on the next page some

data from the noise generated by a PWM Flyback converter.
The noise spectrum is shown as a FFT. Finally, the total
EMI signal is compared to that allowed by the law. We
repeat that electrical engineers that do not design to
regulatory specs are IN VIOLATIOL OF THE LAW.
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 15

iT

Switch
Vg(in) Mode Vout
Network

Input filter to keep switching

harmonics from entering the mains:
EMI noise issue is now a legal one.

Incidentally, some switching signals have very sharp

transients that can be better reduced by an RC snubber
circuit in addition to the EMI filter as shown:

Switch
Vin Mode Vout
Network

A simplified equivalent circuit model is given below:

L
→ Switch
AC C Rout
Mains ← Converter

Previously, we saw that for an equal duration square wave

(d = d’) the fundamental ac component of the signal has
an amplitude 2vdc/π. We will consider the attenuation of the
filter in two ways on the next page:
•A rough transfer function approach
•An intuitive ripple estimate approach
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 1  2
 ⋅R  Where V in = VDCsinwt
jwC π
 
 1  (for D = 0.5)
 + R 
 jwC 
Vout = Vin
 1 
 jwL + ⋅R
 jwC 
 1
+ R 
 
 jwC 
Assume a 40db per decade rolloff due to the L-C. If we
specify the need for 24db of attenuation at the switch
frequency, then the corner frequency of the filter will be at:
FC =fswx 10(24/40) =25KHz
For a 50 Ohm input line impedance and a filter damping
factor of .707 the required Land C are given by:
L= 50x0.707/πx25KHz =450 µH
C= 1/ (2πfC)2L =0.9 µF
Real commercially available capacitors do not exceed
.o5µ so, we need to reduce C by 2 and increase L by 2.
THIS IS ONE WAY. WE ALSO GET A ROUGH IDEA AS
FOLLOWS:
L1 EMI generation

Raw DC ∆vC1 variation occurs

Consider here due to switch switch @ fs
C1
Vg(fixed) network

∆vc1 variation at the inverter input causes ∆iL1 to flow back to

the mains. We have a spec. on the maximum ∆iL1 from the
government. Consider vg for now as fixed instead of a
rectified sinusoid. VL = vg(fixed) - vc1 = ∆vc.
Now any change in ∆vc will cause a change in ∆iL.
∆v dt
2∆iL 1 = ∫ c
L1
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THE TIME PERIOD dt IS Ts/2 AGAIN BY SYMMETRY, AND

1 T
VOLT-sec AREA UNDER ∫∆vdt ≡ ∆v c s
2 2

∆v C Ts
∆iL1(Ripple current due to ∆v) = . IF WE
8L1
SPECIFY BOTH ∆vc (known or measured) AND ∆iL,
WE CAN WRITE THE L VALUE EQUATIONS AS:
value to reduce ∆iL1  ∆v C Ts
L1( ) ≡
to gov. specification ∆iL1 8
given ∆vc
FOR THE DOUBLE POLE FILTER INCLUDING
RIPPLE:

L1 ≠ f(D), L1 ∝ 1/fs

Finally, For HW#1:

1. Answer Questions asked throughout
lectures 1-7.
2. Chapter 2 of ERICKSON Problems 2, 3,
4 and 6.