Chapter 2

Computer system

A Top-Level View of Computer

Function and Interconnection

1
 A Top-Level View of Computer
• At a top level, a computer consists of CPU (central processing
unit), memory, and I/O components, with one or more modules of
each type.
• These components are interconnected in some fashion to achieve
the basic function of the computer, which is to execute programs.
• Thus, at a top level, we can characterize a computer system by
describing
• (1) the external behavior of each component, that is, the data and
control signals that it exchanges with other components and
• (2) the interconnection structure and the controls required to
manage the use of the interconnection structure.
• This top-level view of structure and function is important because
of its explanatory power in understanding the nature of a
computer.
• Equally important is its use to understand the increasingly complex issues of
performance evaluation. 2
 A Top-Level View of Computer
• A grasp of the top-level structure and function offers insight
into system bottlenecks, alternate pathways, the magnitude
of system failures if a component fails, and the ease of
adding performance enhancements.

• In many cases, requirements for greater system power and

fail-safe capabilities are being met by changing the design
rather than merely increasing the speed and reliability of
individual components.

3
 Computer Components
• All contemporary computer designs are based on concepts
developed by John von Neumann at the Institute for
Advanced Studies (IAS), Princeton referred to as the von
Neumann architecture
• and is based on three key concepts:
– Data and instructions are stored in a single read-write
memory
– The contents of this memory are addressable by location,
without regard to the type of data contained there
– Execution occurs in a sequential fashion (unless explicitly
modified) from one instruction to the next

4
 Hardwired program
• A set of basic logic components can be combined to store
binary data and perform arithmetic and logical operations.
• A specific configuration of these components can be
constructed for a specific computation (e.g. a configuration of
logic components can be designed to do specific
calculation).
• The process of connecting the various components in the
desired configuration is a form of programming.
• The resulting “program” is in the form of hardware and is
termed a hardwired program.

Sequence of
Data arithmetic and Results
logic functions

Programming in hardwired

5
 Software Program
• A general-purpose configuration of arithmetic and logic
functions can be constructed, allowing the system to
perform various functions on data based on control signals
applied to the hardware.
• This eliminates the need for rewiring hardware for each
new program, as the programmer only needs to supply
new control signals.
• The program is a sequence of steps, each requiring a new
set of control signals.
• A unique code is provided for each possible set of signals,
and a segment is added to the general-purpose hardware
to accept and generate these signals.

6
 Software Program
• Software: Instead of
rewiring the hardware for Instruction Instruction
codes Interpreter
each new program, all
we need to do is
– provide a new sequence Control
of codes. signals

– Each code is, in effect, an General-purpose

arithmetic and
instruction, and Data
logic functions
Results

– part of the hardware

interprets each instruction
Programming in software
and generates control
signals.

7
 Software and CPU Components
• Software:
– A sequence of codes or instructions
– Part of the hardware interprets each instruction and
generates control signals
– Provide a new sequence of codes for each new program
instead of rewiring the hardware
• Major components of the system:
• CPU constituted by:
– Instruction interpreter
– Module of general-purpose arithmetic and logic functions
• I/O Components

8
 Software and CPU Components
• I/O Components:
– Data and instructions must be put into the system.
– For this we need some sort of input module.
– This module contains basic components for accepting
data and instructions in some form and converting
them into an internal form of signals usable by the
system.
– A means of reporting results is needed which is in the
form of an output module.
• Taken together, these are referred to as I/O
components.
• Memory module (main memory) is a place
where to store temporarily both data and
instructions
9
 Computer Component: Top Level View
• CPU exchanges data CPU Main Memory
with memory using System
0
1

MBR for data & MAR PC MAR Bus

Instruction
2

for addresses. Instruction

Instruction
• I/O AR specifies a IR MBR
particular I/O device, I/O AR
and the I/O BR is used Execution
Data

to exchange data unit Data

I/O BR Data

between an I/O module Data

and the CPU I/O Module n–2

• A Memory module n–1

consists of locations
addressable by
numbers. PC = Program counter

• I/O module transfers Buffers IR

MAR =
= Instruction register
Memory address register
data from external MBR =
I/O AR =
Memory buffer register
Input/output address register
devices to CPU and I/O BR = Input/output buffer register

memory, and vice

versa. Figure 3.2 Computer Components: Top-Level View
10
 Registers
• In a computer, the Memory Address Register (MAR) is
a CPU register that either stores the memory address from which
data will be fetched to the CPU or the address to which data will
be sent and stored.
• An instruction register (IR) is the part of a CPU's control
unit that stores the address of the next instruction currently being
executed or decoded.
• A Memory Buffer Register (MBR) is the register in a computer's
processor, or central processing unit, CPU, that stores the data
being transferred to and from the immediate access store. It
contains the copy of designated memory locations specified by
MAR.
• It acts as a buffer allowing the processor and memory units to act
independently without being affected by minor differences in
operation. A data item will be copied to the MBR ready for use at
the next clock cycle, when it can be either used by the processor
for reading or writing or stored in main memory after being
written.
 Registers
• Similarly, an I/O Address Register (I/OAR) specifies a
particular I/O device.
• An I/O Buffer Register (I/OBR) is used for the exchange
of data between an I/O module and the CPU.

• A memory module consists of a set of locations, defined by

sequentially numbered addresses.
• Each location contains a binary number that can be
interpreted as either an instruction or data.
• An I/O module transfers data from external devices to CPU
and memory, and vice versa.
• It contains internal buffers for temporarily holding these
data until they can be sent on.
 Computer’s Basic Function

• The basic function performed by a computer is

execution of a program, which consists of a set
of instructions stored in memory.

• The instruction is in the form of a binary code that

specifies what action the CPU is to take.

• The processing required for a single instruction is

called an instruction cycle.

• Instruction processing consists of two steps:

13
 Fetch/Execute Cycle
• Instruction fetching: gets/fetches an instruction from
memory
• Instruction execution: performs the instruction

Figure 3.3: Basic instruction cycle

14
 Fetch cycle
◼ At the beginning of each instruction cycle the processor
fetches an instruction from memory

◼ The program counter (PC) holds the address of the instruction

to be fetched next.

◼ Unless told otherwise, the processor always increments the PC

after each instruction fetch so that it will fetch the next
instruction in sequence. (i.e., the instruction located at the next
higher memory address) *

◼ The fetched instruction is loaded into the instruction register (IR)

◼ The instruction contains bits that specify the action the processor is to take.

◼ The processor interprets the instruction and performs the

required action
15
 Fetch cycle
• In general, these actions fall into four categories:
• Processor-memory: Data may be transferred from processor to memory
or from memory to processor.
• Processor-I/O: Data may be transferred to or from a peripheral device by
transferring between the processor and an I/O module.
• Data processing: The processor may perform some arithmetic or logic
operation on data.
• Control: An instruction may specify that the sequence of execution be
altered.
• For example, the processor may fetch an instruction from location 149, which
specifies that the next instruction be from location 182.
• The processor will remember this fact by setting the program counter to 182.
• Thus, on the next fetch cycle, the instruction will be fetched from location 182
rather than 150.
• An instruction’s execution may involve a combination of these actions.
16
 Fetching an Instruction
Memory location contents
Instruction Pointer

0001 0001 0FFF

0002 0FA0
Address Bus
0003 010D

0004 00C1

0005 0010

17
 Fetching an Instruction
Instruction Pointer Memory location contents

0001 0001 0FFF

0002 0FA0
Address Bus

0003 010D

Contents of the
Program 0004 00C1
Counter are
passed across
the Address Bus 0005 0010

18
 Fetching an Instruction
Instruction Pointer Memory location contents

0001 The address 0001 0FFF

moves over the
address bus to
the Memory 0002 0FA0
Address Bus Access Register

0003 010D

0001
0004 00C1

Memory Access Register

0005 0010

19
 Fetching an Instruction
Memory location contents

0001 0FFF

The memory location

of the next instruction 0002 0FA0
is located.

0003 010D

0001
0004 00C1

Memory Access Register

0005 0010

20
 Fetching an Instruction
Memory location contents

Data Bus 0001 0FFF

The contents of
memory at the 0002 0FA0
given location are
moved across the
data bus 0003 010D

0004 00C1

0005 0010

21
 Fetching an Instruction
Memory location contents

Data Bus 0001 0FFF

0002 0FA0
Into the instruction
register (IR) 0003 010D

0FFF
0004 00C1

Instruction Register
0005 0010

22
 Fetching an Instruction

With the instruction loaded from

memory into the Instruction Register
the fetch portion of the cycle is
complete.

0FFF

Instruction Register

23
 Execute Cycle

• The processor interprets instruction

and performs required actions:
• Data transfer
– Between CPU and main memory
– Between CPU and I/O module
• Data processing
– Some arithmetic or logical operation on data
• Control
– Alteration of sequence of operations, e.g. jump
• Combinations of the above
 Execute Cycle

Fetch Next
Instruction

Decode
Instruction

Execute
Instruction

Processor Fetch, Decode and Execute Cycle.

Characteristics of a Hypothetical Machine

Consider a simple example using a

hypothetical machine that includes the
characteristics listed in Figure 3.4. The
processor contains a single data register,
called an accumulator (AC). Both
instructions and data are 16 bits long.
Thus, it is convenient to organize memory
using 16-bit words. The instruction format
provides 4 bits for the opcode, so that
there can be as many as 24 = 16 different
opcodes, and up to 212 = 4096 (4K) words
of memory can be directly addressed.
 Example of Program Execution
NB:
contents of
memory and
registers in
hexadecimal
 From the example above example. . .
1. The PC contains 300, the address of the first instruction. This
instruction (the value 1940 in hexadecimal) is loaded into the
instruction register IR, and the PC is incremented. Note that this
process involves the use of a memory address register and a memory buffer
register. For simplicity, these intermediate registers are ignored.
2. The first 4 bits (first hexadecimal digit) in the IR indicate that the
AC is to be loaded. The remaining 12 bits (three hexadecimal
digits) specify the address (940) from which data are to be loaded.
3. The next instruction (5941) is fetched from location 301, and the PC
is incremented.
4. The old contents of the AC and the contents of location 941 are
added, and the result is stored in the AC.
5. The next instruction (2941) is fetched from location 302, and the PC
is incremented.
6. The contents of the AC are stored in location 941.
28
 Instruction Cycle state diagram
In above example, three instruction cycles, each consisting of a fetch
cycle and an execute cycle, are needed to add the contents of location
940 to the contents of 941. With a more complex set of instructions,
fewer cycles would be needed. With these additional considerations in
mind, Figure 3.6 provides a more detailed look at the basic instruction
cycle of Figure 3.3.

29
 Instruction Cycle state diagram…
• Instruction address calculation (iac): determines the address of
the next instruction to be executed
• Instruction fetch (if): fetch (read) instruction from memory
location into the processor
• Instruction operation decoding (iod): decode (analyze)
instruction to determine type of operation to be performed and
operand/s to be used
• Operand address calculation (oac):determine the address of the
operand (in memory or I/O) if the instruction has a reference to an
operand.
• Operand fetch (of): fetch the operand from memory or read it in
from I/O
• Data operation (do): perform the operation indicated in the
instruction
• Operand store (os): Write the result into memory or out to I/O
30
 Instruction Cycle state diagram…
• Notice that: The upper part of the diagram involve data exchanging
between the CPU and either the memory or an I/O module.

The lower part involve only internal processor operations

31
 Single Instruction Cycle example
• For example, a processor includes an instruction, expressed
symbolically as ADD B, A, that stores the sum of the contents of
memory locations B and A into memory location A.
• A single instruction cycle with the following steps occurs:
i. Fetch the ADD instruction.
ii. Read the contents of memory location A into the processor.
iii. Read the contents of memory location B into the processor.
In order that the contents of A are not lost, the processor must
have at least two registers for storing memory values, rather
than a single accumulator.
iv. Add the two values.
v. Write the result from the processor to memory location A.

32
 Interrupts
• From the point of view of the user program, an interrupt is
just that: an interruption of the normal sequence of execution.
• When the interrupt processing is completed, execution
resumes.
• Interrupt is a mechanism by which other modules (e.g. I/O,
memory) may interrupt the normal processing of the
processor.
• Its main goal is to improve processing efficiency since the
external devices (e.g. I/O modules) are very slow.
• CPU may waste time waiting for these slow devices to
perform their tasks.
• With interrupts, the processor can be engaged in executing
other instructions while an I/O operation is in progress.

33
 Classes of interrupts
• Program: Generated by some condition that occurs as
a result of an instruction execution, such as arithmetic
overflow, division by zero, attempt to execute an illegal
machine instruction, or reference outside a user’s
allowed memory space.
• Timer: Generated by a timer within the processor.
• This allows the operating system to perform certain
functions on a regular basis.
• I/O: Generated by an I/O controller, to signal normal
completion of an operation, request service from the
processor, or to signal a variety of error conditions.
• Hardware Failure: Generated by a failure such as
power failure or memory parity error. 34
 Interrupts example
• Assume that the processor is transferring data to a printer using
the instruction cycle scheme.
• After each write operation, the processor must pause and remain
idle until the printer catches up.
• The length of this pause may be on the order of many hundreds
or even thousands of instruction cycles that do not involve
memory. Clearly, this is a very wasteful use of the processor.
• Figure 3.7a illustrates this state of affairs.
• The user program performs a series of WRITE calls interleaved
with processing.
• Code segments 1, 2, and 3 refer to sequences of instructions that
do not involve I/O.
• The WRITE calls are to an I/O program that is a system utility
and that will perform the actual I/O operation.
35
 Interrupts example
• The I/O program consists of three sections:
1. A sequence of instructions, labeled 4 in the figure, to prepare
for the actual I/O operation.
This may include copying the data to be output into a special
buffer and preparing the parameters for a device command.
2. The actual I/O command. Without the use of interrupts, once
this command is issued, the program must wait for the
I/O device to perform the requested function (or
periodically poll the device).
The program might wait by simply repeatedly performing
a test operation to determine if the I/O operation is done.
3. A sequence of instructions, labeled 5 in the figure, to
complete the operation.
36
Figure 3.7 Program Flow of Control without and with Interrupts

X= interrupt occurs during course of execution of user program 37

 Interrupt and the instruction cycle
• To accommodate interrupts, an interrupt cycle is added to the
instruction cycle.
• In the interrupt cycle, the processor checks to see if any
interrupts have occurred, indicated by the presence of an interrupt signal.
• If no interrupts are pending:
– the processor proceeds to the fetch cycle and
– fetches the next instruction
• If interrupts are pending:
– Suspend execution of current program
– Save its context (i.e., saving the address of the next instruction to be executed)
– Set program counter (PC) to start address of interrupt
handler routine
– Process interrupt
– Restore context and continue interrupted program
Transfer of Control via Interrupts
Interrupts: Instruction cycle with interrupts

40
The revised instruction cycle state diagram
that includes interrupt cycle processing

41
 Multiple interrupts
• Multiple interrupts refer to situations where more than one
interrupt occurs while the processor is already handling
another interrupt.
• This can happen when multiple devices or processes need
the CPU’s attention simultaneously.
• Example: a program may be receiving data from a
communications line and printing results.
• The printer will generate an interrupt every time it completes
a print operation.
• The communication line controller will generate an interrupt
every time a unit of data arrives.
• The unit could either be a single character or a block,
depending on the nature of the communications discipline.
• In any case, it is possible for a communications interrupt to
occur while a printer interrupt is being processed.
42
 Multiple interrupt approaches
• Two approaches can be taken to dealing with multiple
interrupts: disable interrupts and define priorities
• First approach: a disabled interrupt means that the processor
can and will ignore that interrupt request signal.
• If an interrupt occurs during this time:
– it remains pending and will be checked by the processor
after the processor has enabled interrupts.
• i.e., when a user program is executing and an interrupt occurs,
interrupts are disabled immediately.
• After the interrupt handler routine completes, interrupts are
enabled before resuming the user program, and the processor
checks to see if additional interrupts have occurred.
• This approach is nice and simple, as interrupts are handled in
strict sequential order. 43
 Multiple interrupt approaches
• The drawback to this approach is that it does not take into
account relative priority or time-critical needs.
• For example, when input arrives from the
communications line, it may need to be absorbed rapidly
to make room for more input.
• If the first batch of input has not been processed before
the second batch arrives, data may be lost.
• Second approach: is to define priorities for interrupts
and to allow an interrupt of higher priority to cause a
lower-priority interrupt handler to be itself interrupted.

44
 Multiple interrupt approaches
• Define priorities example: consider a system with three
I/O devices: a printer, a disk, and a communications line, with
increasing priorities of 2, 4, and 5, respectively. See Figure 3.14
• A user program begins at t = 0. At t = 10, a printer interrupt occurs;
user information is placed on the system stack and execution
continues at the printer interrupt service routine (ISR).
• While this routine is still executing, at t = 15, a communications
interrupt occurs. Because the communications line has higher priority
than the printer, the interrupt is honored.
• The printer ISR is interrupted, its state is pushed onto the stack,
and execution continues at the communications ISR.
• While this routine is executing, a disk interrupt occurs (t = 20).
• Because this interrupt is of lower priority, it is simply held, and the
communications ISR runs to completion.
• When the communications ISR is complete (t = 25), the previous processor state
is restored, which is the execution of the printer ISR. 45
Time Sequence of Multiple Interrupts

46
Interrupts: nested interrupts
processing

47
 I/O function
• I/O module can exchange data directly with the processor
• Processor can read data from or write data to an I/O module
– Processor identifies a specific device that is controlled by a
particular I/O module
– an instruction sequence similar could occur I/O instructions
rather than memory referencing instructions
• In some cases, it is desirable to allow I/O exchanges to occur
directly with memory
– The processor grants to an I/O module the authority to read
from or write to memory so that the I/O memory transfer can
occur without tying up the processor
– The I/O module issues read or write commands to memory
relieving the processor of responsibility for the exchange
– This operation is known as direct memory access (DMA)
48
 Interconnection Structures
• A computer consists of a set of components or modules of
three basic types (processor, memory, I/O) that communicate
with each other and all units must be connected.
• Interconnection structure: is the collection of paths
connecting the various modules.
• The design of this structure will depend on the
exchanges that must be made among modules.
– Memory: will consist of N words of equal length.
– Input/output: is functionally similar to memory.
Has two operations (read and write).
Further, may control more than one external device.
– CPU: reads in instructions and data, writes out data after
processing, uses control signals to control the overall operation
of the system, and receives interrupt signals.
49
Computer Modules
• NB: The wide
arrows represent
multiple signal
lines carrying
multiple bits of
information in
parallel.
• Each
narrow arrow
represents a
single signal
line.

50
 Data Transfer
• The interconnection structure must support the following types of
transfers:
– Memory to processor: The processor reads an instruction or a
unit of data from memory.
– Processor to memory: The processor writes a unit of data to
memory.
– I/O to processor: The processor reads data from an I/O device
via an I/O module.
– Processor to I/O: The processor sends data to the I/O device.
– I/O to or from memory: For these two cases, an I/O module
is allowed to exchange data directly with memory, without
going through the processor, using direct memory access
(DMA).

51
 Bus Interconnection
• A bus is a communication pathway connecting two or more
devices.
• A key characteristic of a bus is that it is a shared transmission
medium.
• Multiple devices connect to the bus, and a signal transmitted by
any one device is available for reception by all other devices
attached to the bus.
• If two devices transmit during the same time period, their signals
will overlap and become garbled.
• Thus, only one device at a time can successfully transmit.
• Typically, a bus consists of multiple pathways or lines.
• Each line is capable of transmitting signal representing binary
digits ( binary 1 and binary 0) 52
 Bus Interconnection
• A sequence of bits can be transmit across a single
line.
• Taken together, several lines can be used to
transmit bits simultaneously (in parallel).
• For example, an 8-bit unit of data can be transmitted over
eight bus lines.
• Computer systems contain a number of different buses that
provide pathways between components at various levels of
the computer system hierarchy.
• A bus that connects major components (CPU,
Memory, I/O) is called System Bus.
• The most common computer interconnection
structures are based on the use of one or more
53
system buses.
 Bus Structure
• A system bus consists of 50-100 separate lines.
• Each line is assigned a particular meaning or function.
• Although there are many different bus designs, on any bus
the lines can be classified into 3 groups
– Data lines
– Address lines
– Control lines

• In addition, there may be power distribution lines that supply

power to the attached modules.
54
 Data Lines
• Provide a path for moving data between system
modules.
• These lines, collectively, are called the data bus
• The data bus may consist of 32, 64, 128, or even more
separate lines, the numbers of lines being transferred to
as the width of the data bus.
• Because, each line carry only 1 bit at a time, the number
of lines determines how many bits can transferred at a
time.
• The width of the data bus is a key factor in determining
overall system performance.
• For example, if the data bus is 32 bits wide and each
instruction is 64 bits long, then the processor must access
the memory module twice during each instruction cycle.
55
 The Address Lines
• are used to designate the source or destination of the data
on the data bus.
• For example, if the processor wishes to read a word (8, 16,
or 32 bits) of data from memory, it puts the address of the
desired word on the address lines.
• The width of the address bus determines the maximum
possible memory capacity of the system.
• The address lines are also used to address I/O ports.
– Typically, the higher-order bits are used to select a
particular module on the bus, and the lower-order bits
select a memory location or I/O port within the module.
– For example, on an 8-bit address bus, address 01111111 and below might reference
locations in a memory module (module 0) with 128 words of memory, and address
10000000 and above refer to devices attached to an I/O module (module 1).
56
 The Control Lines
• are used to control the access to and the use of the
data lines and address lines.
• Because the data lines and address lines are shared
by all components, there must be a means of
controlling their use.
• Control signals transmit both command and timing
information among system modules.
• Timing signals indicate the validity of data and
address information.
• Command signals specify operations to be
performed.

57
 The Control Lines
Typical Control Lines include:
▪ Memory write: causes data on the bus to be written into the
addressed location.
▪ Memory read: causes data from the addressed location to be
placed on the bus.
▪ I/O write: causes data on the bus to be output to the addressed
I/O port.
▪ I/O read: causes data from the addressed I/O port to be placed
on the bus.
▪ Transfer ACK: indicates that data have been accepted from or
placed on the bus.
▪ Bus Request: indicates that a module needs to gain control of
the bus.
▪ Bus Grant: indicates that the requesting module has been
granted control of the bus.
▪ Interrupt Request: indicates that an interrupt is pending.
▪ Interrupt ACK: acknowledges that the pending interrupt has been
recognized.
▪ Clock: is used to synchronize operations
▪ Reset: initializes all modules 58
 Bus operation
• The operation of the bus is as follows.
• If one module wishes to send data to another, it must do
two things:
– (1) obtain the use of the bus, and
– (2) transfer data via the bus.
• If one module wishes to request data from another
module, it must
– (1) obtain the use of the bus, and
– (2) transfer a request to the other module over the
appropriate control and address lines.
• It must then wait for that second module to send the
data.
59
 Single Bus Problems
• Lots of devices on one bus (will cause performance to
suffer) leads to:
– Propagation delays
• Long data paths mean that co-ordination of bus use
can adversely affect performance
• The bus may become a bottleneck as the aggregate
data transfer demand approaches the capacity of
the bus (in available transfer cycles/second)

• Most systems use multiple buses to overcome these

problems
What do buses look like?

✓Parallel lines on circuit boards

✓Ribbon cables
✓Strip connectors on mother boards
✓e.g. PCI
✓Sets of wires
?

61
 Multiple-Bus Hierarchies
• Traditional Hierarchical Bus Architecture
– Use of a cache structure insulates CPU from
frequent accesses to main memory
– Main memory can be moved off local bus to a
system bus
– Expansion bus interface
• buffers data transfers between system bus
and I/O controllers on expansion bus
• insulates memory-to-processor traffic from I/O
traffic
 Traditional Hierarchical Bus Architecture Example

• Local bus
– CPU - Cache/bridge
• System bus
– Cache/bridge - memory
• Expansion bus
– Low-speed I/O modules - Expansion interface
 Multiple-Bus Hierarchies
• High-performance Hierarchical Bus Architecture
– Traditional hierarchical bus breaks down as higher and
higher performance is seen in the I/O devices
– Incorporates a high-speed bus
• specifically designed to support high-capacity I/O
devices
• brings high-demand devices into closer integration
with the processor and at the same time is
independent of the processor
• Changes in processor architecture do not affect the
high-speed bus, and vice versa
– Sometimes known as a mezzanine architecture
 High-performance Hierarchical Bus Architecture Example
•

• Local bus: CPU - Cache/bridge

• System bus: Cache/bridge - memory
• High-speed bus: High-speed I/O module - Cache/bridge
• Expansion bus: Low-speed I/O modules - Expansion interface
 Elements of Bus Design
◼ Bus types: ◼ Bus Width:
◼ Dedicated ◼ Address
◼ Multiplexed ◼ Data
◼ Bus Arbitration: ◼ Data Transfer Type:
◼ Centralized ◼ Read
◼ Distributed ◼ Write
◼ Timing: ◼ Read-modify-write
◼ Read-after-write
◼ Synchronous
◼ Block
◼ Asynchronous

66
 Bus Types
• Dedicated
– Separate data & address lines
• Multiplexed
– Shared lines
– Address valid or data valid control line
– Advantage - fewer lines
– Disadvantages
• More complex control
• Ultimate performance
 Bus Width
• Address:- the wider of address bus has an impact on
range of locations that can be referenced
• Data:- the wider of data bus has an impact on the
number of bits transferred at one time
Timing: Refers to the way in which events are coordinated
on the bus.
– Buses use either synchronous timing or asynchronous timing.
• Synchronous :- Occurrence of events on the bus is
determined by a clock (Clock Cycle or Bus Cycle)
which includes line upon.
• Asynchronous:- occurrence of one event follows
and depends on the previous event.

68
 Bus Arbitration
• is a process used in computer systems to manage access to a
shared communication pathway, known as a bus, when multiple
devices need to use it simultaneously.
• This ensures that data transfers occur smoothly without conflicts
or data corruption.
• More than one module may control the bus
– e.g. CPU and DMA controller
• Only one module may control bus at one time
– Centralized arbitration
• Single hardware device controlling bus access
– Single bus arbiter: A central controller (bus arbiter) manages access to the bus.

• May be part of CPU or separate

– Distributed arbitration
• No central arbiter: All devices participate in the arbitration process.
i.e., each module may claim the bus
• Control logic on all modules
 Samples of Bus
• ISA (Industry Standard Architecture)
• EISA (Extended ISA)
• VL Bus (VESA Local Bus)
• PCI Bus (Peripheral Connection Interface)

70
 Industry Standard Architecture
• ISA is a standard bus (computer interconnection)
architecture that is associated with the IBM AT
motherboard.
• It allows 16 bits at a time to flow between the
motherboard circuitry and an expansion slot
card and its associated device(s).

71
 Extended Industry Standard Architecture
• EISA is a standard bus architecture that extends the
ISA standard to a 32-bit interface.
• It was developed in part as an open alternative to
the proprietary Micro Channel Architecture (MCA)
that IBM introduced in its PS/2 computers.
• EISA data transfer can reach a peak of 33
megabytes per second

72
 VESA Local Bus
• VESA VL bus is a standard interface between your
computer and its expansion slot that provides faster data
flow between the devices controlled by the expansion cards
and your computer's microprocessor.
• A "local bus" is a physical path on which data flows at
almost the speed of the microprocessor, increasing total
system performance.
• VESA Local Bus is particularly effective in systems with
advanced video cards and supports 32-bit data flow at 50
MHz
• A VESA Local Bus is implemented by adding a
supplemental slot and card that aligns with and augments
an ISA expansion card. (ISA is the most common expansion
slot in today's computers.)
73
 Peripheral Component Interconnect (PCI)
• PCI (Designed by Intel) is a popular high-bandwidth, processor-
independent bus that can function as a mezzanine or
peripheral bus.
• PCI is an interconnection system between a microprocessor
and attached devices in which expansion slot are spaced
closely for high speed operation.
• PCI deliver better system performance for high-speed
I/O subsystems :
– e.g. graphic display adapters, network interface
controllers, disk controllers
• PCI is designed to be synchronized with the clock speed of
the microprocessor, in the range of 33 to 66 MHz.

74
 Peripheral Component Interconnect (cont.)
• PCI is now installed on most new desktop computers.
• Current Standard:
– up to 64 data lines at 33 to 66 Mhz
– requires few chips to implement
– supports other buses attached to PCI bus
– public domain, initially developed by Intel to support
Pentium-based systems
– supports a variety of microprocessor-based
configurations, including multiple processors
– uses synchronous timing and centralized arbitration
• However, the bus-based PCI scheme has not been able to
keep pace/speed with the data rate demands of attached
devices.
75
 PCI Express (PCIe)
• PCIe is a new version has been developed.
• PCIe is a point-to-point interconnect scheme intended to
replace bus-based schemes such as PCI.
• A key requirement for PCIe is high capacity to support
the needs of higher data rate I/O devices, such as
Gigabit Ethernet.
• Another requirement deals with the need to support
time-dependent data streams.
• Applications such as video-on-demand and audio
redistribution are putting real-time constraints on servers
too.
• Many communications applications and embedded PC
control systems also process data in real-time.
76
 PCI Express (PCIe) configuration
•

77
 PCI Express (PCIe) con …
• A root complex device, also referred to as a chipset or a host
bridge, connects the processor and memory subsystem to the PCI
Express switch fabric comprising one or more PCIe and PCIe
switch devices.
• PCIe links from the chipset may attach to kinds of devices:
• Switch: manages multiple PCIe streams.
• PCIe endpoint: An I/O device or controller that implements PCIe,
such as a Gigabit ethernet switch, a graphics or video controller,
disk interface, or a communications controller.
• Legacy endpoint: is intended for existing designs that have been
migrated to PCI Express, and it allows legacy behaviors such
as use of I/O space and locked transactions.
– PCI Express endpoints are not permitted to require the use of
I/O space at runtime and must not use locked transactions.

78
 PCI Express (PCIe) con …
• PCIe/PCI bridge: allows older PCI devices to be connected to
PCIe-based systems.

• Physical: consists of the actual wires carrying the signals, as well

as circuitry and logic to support ancillary features required in the
transmission and receipt of the 1s and 0s.

• Data link: is responsible for reliable transmission and flow control.

• Transaction: Generates and consumes data packets used to

implement load/ store data transfer mechanisms
– also manages the flow control of those packets between the two
components on a link.

79