MemoryAccess(DMA)
Direct
For the execution
of a computerprogram,
it requires
the synchronous
workingof more than
one componentof a computer. For example, -
Processors providing necessarycontrol
information, -
addressetc.buses to transferinformation and datato and frommemoryto /0
deviceetc.The interestingfactorof the systemwouldbe the way ithandlesthe transfer of
informationamong processor, memory and /0devices. Usually,processors controlallthe
processof transferring
data, rightfrominitiating the transferto the storage of data at the
destination.
Thisadds load on the processor and most of the timeit staysinthe ideal state,
thusdecreasing the efficiency
of the system.To speed up the transfer of data between /0
and memory,DMA Controller
devices actsas stationmaster.DMA controller transfersdatawith
minimalinterventionofthe processor.
What isa DMA Controller?
The term DMA standsfor direct
memoryaccess. memory
The hardwaredeviceused fordirect
access is called the DMA DMA controller
controller. is a controlunit,part of /0
device's
interface whichcan transferblocksof data between /o devicesand main
circuit,
memorywithminimal intervention fromthe processor.
The DMA transfers
the data inthreemodes whichinclude the following.
a) BurstMode: Inthismode DMA handoverthe busesto CPUonlyaftercompletion of whole
Meanwhile,
data transfer. if the CPU requires
the bus ithas to stay ideal
and waitfordata
transfer.
b) CycleStealing :
Mode Inthismode,DMA givescontrolof busesto CPU aftertransfer
of every
byte.Itcontinuously
issuesa requestfor bus control,
makes the transferof one byte and
returns
the bus.By thisCPU doesn'thave to waitfor a long timeif it needsa bus for higher
priority
task.
Mode:Here,DMA
c) Transparent data only when CPU
transfers is executing
the instruction
whichdoes not require
the useof buses.
How DMA Operationsareperformed?
Followingis the sequenceof operations
performedby a DMA -
when anydevicerequires
Primarily, to send data betweenthe deviceand the memory, the
deviceneed to send DMA request
(DRQ)to DMA controller.
The DMA controllersendsHoldrequest(HRQ)to the CPU and waitsforthe CPU to assertthe
HLDA signal.
Then the microprocessor bus.TheCPU
allthe data bus,addressbus,and control
tri-states
leavesthe control
overbusandacknowledges the HOLDrequestthroughHLDAsignal.
When the CPU is the DMA controller
inHOLDstatewiththe HOLD request, has to control
overbusesbetweenthe CPU, memory,
the operations and i/0devices.
of 8257
Features
Hereis a listof some ofthe prominent of 8257 -
features
> It has fourchannels over fouri/0devices.
whichcan be exhibited
address
has 16-bit
Each channel and 14-bit
counter.
canbe takenup to 16kB.
of each channel
Data transfer
Each channelcanbe programmedindependently.
Each channelcanperformcertain actions
specific i.e. writetransferand
readtransfer,
verifytransfer
operations.
It
devicethat 128 bytes have been
produces MARK signalto the peripheral
transferred.
a single
It requires phase clock.
> Its frequencyr angesfrom250Hzto 3MHz.
It operations
performs Master mode and Slavemode.
i.e.,
in2 modes,
connected
signals
tri-state to the system data bus.
These are bi-directional
Data Bus (Do-D,):
of addressregister, status
When CPUis having controlof systembus it can accesscontents
countregisterand it can also program,control
and a terminal
mode set register,
register,
throughthe data bus.
of DMA controller,
registers
are used to send the most significantbytes of the memory
DuringDMA cyclesthese lines
fromone of the
address
AddressBus (Ao-Azand Ag-A): The fourleastsignificantlines -
Ag-Azare bi directionaltri-
the register
and used by the CPU to address to
Inthe idlecyclethey are inputs
statesignals.
lower4 bitsof the addressfor DMA
be loadedor read.Inthe Activecyclethey outputthe
lines,
A4-Az are unidirectional
operation. 4
provide -bits
of addressduringDMA service.
higherbyte addressand data
is used to demultiplex
AddressStrobe(ADSTB): This signal
usingexternallatch.
the upper 8
latchcontaining
enablesthe 8-bit
AddressEnable(AEN): Thisactivehighsignal
other systembus
addressbitsonto the system addressbus.AEN can alsobeused to disable
duringDMA transfers.
drivers
Memory Read and Memory Write(MEMR, MEMW) These are activelowtri-state
: signals.
The MEMR signalused to accessdata from the addressedmernorylocationduringa DMA
reador memory-to-memory and MEMW signalis usedto writedatato the addressed
transfer
memorylocationduringDMA writeor memoryto memorytransfer.
/o Read and i/0Write(IORand lOW ):These
are activelow bi-directional
signals.
Inidle
cycle,theseare an inputcontrolsignalsusedby CPUto read/write Inthe
the controlregisters.
activecycleIORsignal is usedto accessdata from a peripheral
and IOW signalis usedto send
data to the peripheral.
ChipSelect(CS):Thisisan activelow input,
usedto selectthe 8257 as an /0 deviceduring
ThisallowsCPU to communicate
the idlecycle. with PinDiagramof 8257.
:
Reset Thisactivehighsignal the command,status,
clears, request
and temporary registers. It
alsoclears
the first/last and setsthe Master Register.
flip-flop Afterresetthe deviceis in the
idlecycle.
Ready : This inputis used to extendthe memory read and writesignals
fromthe 8257 to
interfaceslowmemories or i/0devices.
Hold request(HRQ):
Any validDREQ causes8257 to issue
the HRQ. Itis used forrequesting
CPUtogetthe control
of systembus.
HoldAcknowledge(HLDA):The activehighHoldAcknowledgefrom the CPU indicates
thatit
has relinquished
control
ofthe systembus.
DREQO-DREQ3 :These are DMA request whichareactivatedto obtainDMA service,
lines, until
the corresponding
DACK signalgoesactive.
DACKo-DACK3 : Theseare usedto indicate
peripheral thatthe DMA request
devices isgranted.
Terminal :
Count(TC) Thisis activehighsignal of DMA service.
concernwiththe completion
The TC outputsignal at the end of DMA service,
is activated when presentcycleisa last
i.e.
cycleforthe current
data block.
MARK This output notifies
: the selected that the currentDMA cycle isthe
peripheral
128"cyclesincethe previous
MARK output.MARK alwaysoccursat 128(allmultiplies
of 128)
cyclesfromthe end ofthedata block.
of 8257:
BlockDiagram
DRQO
CiHO
16
Dala bil
bus addr
buffor CNTR DACK,
CH1 DRQ,
16
bit
IOR addr
CNTR DACK,
CLK Read/
RESET write
A logic CH2 DRQ,
A.
bit
A
addr
CNTR DACK
CS
CH3 DRQ3
A
16
A bit
addr
DACK,
A
A7 Control CNTR
READY logic
and
HRQ
mode
HLDA set
MEMR Priority
register resolver
MEMW
AEN
ADSTB
Internalbus
TC
MARK
diagram of 8257
Fig.14.62Functionalblock
Data Bus Buffer: to the system data
the 8257
bitbufferwhichinterfaces
eight
bi-directional,
It is a tri-state, and internal
is used to transferdata
between microprocessor
bus.Inthe slave mode,it on thedata
(Ag-A15)
higherbyte address
of 8257.In
registers mastermode,it is usedto send
bus.
Read/Write logic: of PinDiagramof 8257
or readingone of the internalregisters
When the CPU is programming or
logicacceptsthe i/ORead (IOR)
whenthe 8257 is inthe slavemode),the Read/Write
(i.e, either
decodesthe leastsignificant fouraddressbits(Ao-A3) and
I/0Write(I0W)signal, register(ifIOW is low) or placesthe
writesthe contents of the data bus intothe addressed
of the addressedregister onto the data bus(ifIORis low).
contents logic generates
Read/Write
DuringDMAcycles(i.e. whenthe 8257 is inthe mastermode)the
writeand memory read (DMA read
writecycle)or i/O
the i/0readand memorywrite(DMA
betweenperipheral and memorydevice.
signals
cycle) whichcontrol the datatransfer
DMA Channels:
fouridentical
of 8257 provides
The Pin Diagram labeledCH,to
channels, CH,.Each channel
has two sixteen
bitregisters:
1, DMA addressregister,
and
2 Terminal
countregister.
It specifies
register.
14.63shows theformatof DMA
:Fig.
DMA addressregister address
It is necessary to loadvalidmemory
the address memorylocationto be accessed.
of the first
addressin the DMA address beforechannelis enabled.
register
|AsA4AjsA AA A Ag Ay A As A,A,
A2 A1A,
Fig.14.63Formatof DMA addressregister
Countregister.
the formatof Terminal
CountRegisterFig.14.64shows
Terminal :
c|C
GC |C|Cl
count(N-1)
14bitbinary
Fig.14.64
Type ofoperation
0 DMA verifycycle
0 1 DMA Writecycle
DMA READ cycle
1|1
1 llegal
Note : N is numberofbytesto be transferred.
countregister specifies
(C13- Co)of the terminal
The valueloadedintothe low order14bits
beforethe terminal count (TC)outputis activated.
the number of DMA cyclesminusone
DMA Cyclesitis necessaryto loadthe value N-1intothe
Therefore,forN numberof desired
2 bitsof the terminal
The most significant
low order14-bitsof the terminalcountregister.
to be performed.Itis necessaryto load
the type of DMA operation
specifies
count register
code forvalidDMACycleinthe terminal countregister
countforDMA cyclesandoperational
beforechannelis enabled.
Controllogic:
Itcontrols the sequenceof operations duringallDMA Cycles(DMA read,DMA Write,DMA
and the 16-bitaddressthatspecifiesthe
by generating
verify) the appropriatecontrolsignals
of modesetregister
Itconsists Mode set
and statusregister.
memory locationto be accessed.
the statusregister
i s read by
is programmed by the CPUto configure8257 whereas
register and statusof update
countcondition
reacheda terminal
CPUto checkwhichchannelshave
flag.
Mode SetRegister: four bitsof mode set
Leastsignificant
the format of mode set register.
Fig.14.65 g ives fourbitsallowfour
Most significant
enable each ofthe four DMA channels.
when
register, set,
forthe PinDiagram of 8257. and
differentoptions the DMA addressregisters
by the CPU afterinitializing
It is normally programmed alloptions,inhibiting
thusdisabling
It is clearedby the RESET input,
terminalcountregisters.
busconflicts on power-up.
allchannels,and preventing
B, B Bs B4 B B, B Bo
DMA channel
Enables 0
AUTOLOAD
Enables DMA channel1
Enables
TC stop
Enables -EnablesDMAchannel2
EXTENDED WRITE DMA channel3
Enables Enables
ROTATING PRIORITY
Enables
Fig.14.65Mode set register
StatusRegister: which
it indicates
have
channels
format.As saidearlier,
statusregister
Fig.14.66shows the previously.
and includesthe updateflagdescribed
countcondition
reacheda terminal
B, B B B B B, B Bo
TC stalusforchannel0
Updateflag TC status forchannel1
TC statusforchannel2
-TCstatusforchannel3
Fig.14.66Statusregister
if one,indicates
terminal counthas beenreachedforthatchannel. 1Cbit
The TC statusbit,
however,is
The updateflag,
is reador the 8257is reset.
the statusregister
remainsset until
notaffectedbya statusreadoperation.
updatecycle.Inupdate cycie
CPU that8257 is executing
ifone,indicates
The updateflagbit,
8257 loadsparameters 3 to channel2.
inchannel
PriorityResolver: modes,eitherin
be programmed
to work intwo
the peripherals
Itresolves itcan
requests.
mode.
priority
fixedmodeorrotating
