PHYSICAL verification

Inputs in Pastroute db
Iii Ruledeckfile
OASIS GDS II
YI

Runtime
Physical verification caliber
Lhs

Output lil DRC

metallayer Base layer
DRC DRC

II ERC
Ciii Antenna Violation
In Metal Go violations
C Lus
Rule deck Rule deck is given from foundry It is a
file file
set of written in standard verification rule format
Code

It guides the tool to extract the devices and the connectivity

layer information to identifythe layers in used
ofIC's It
contains

file and to match it with the location of layer in Gns

Rule deck also contains device structure definitions

Restore the same post route db in which we were implementing Eco

flow
NERI
ERC involves checking a design for all electrical connection
ERC Will check
Unconnected
Inputandshorted output
Gate should not connect directly to supply Must beconnected
TIE
through high and TIE low cells
Iii VDDLuss errors to be connected to
The wellgeometries med

power ground and if the PG connection is notcomplete

as if the pins are not defined the whole layout can

repost error like MWELL notconnected to Uno

 Schematicchecks
Linus Layout Vs

Mo ofdevices in schematic layout

devices in schematic
Type of layout
Kill Moofnets in schematic layout

Typicalerrors during Lus checks

lil Shorts opens
Component mismatch Componentmismatch can happen if
component of different types areused Luiinsteadof Srt
Ciii Missing component tf some expected componentis leftout
from layout
Iv Parameter mismatch Allcomponent has its own properties LUS
tool is configured to compare these properties withsome
tolerance tolerance is not met then it will
if give
parameter mismatch

US layoutnetlist
Spice netlist generatedfromspicetool

4 Overlap whenAND gate is overlapped with buffer toolcannot

understand which all should behere iftonsiders
considered

it asbuffer if spice netlistwell showANDgateandlayoutnettist

shows a buffer it will lead to Los
fait
 design_ckDRc
nothing but physicalcheckof
A Design rule checke is metal width
pitch and spacing requirement different layers with respect
for
to different manufacturing process

Bares
it Violation with to oxide diffusion OD
ftp.ggt
spacing
Area
Enclosure
Overlaps Overlaps with N well

Iii Violation with respect to polyonide Po

Area Enample ODwidth

Pitch
OD Area
Width
spacing
Enclosure
Minimum distance that should be maintained

from boundary to poly

a cut Polyoxide Cpo
width
b butted Bpo spiffing
polyonide
I 4 Trim polyoxide Teo
Liii Violation lost to PODE
Poly on Onide Edge
s

width
Area

Violation wet to CPO DE Connected Poly on oxide

Edge

At floorplan stage we are checking for Denarules

there with
respect to memory the above violation will be reported and in
post route stage with respect to standard cell we have may
these type
ofviolations
 Physical Verification

ptre t
US ERC I

ÉTMÉntt maiden HtqÉsD

Goviolation

MetalDRIs
From me to the top routing layer Fos ex Mai if we are

having any Dre with respect to metal layers

Shorts opens min cut min step Violations cut enclosure vialoops

Finingthe Metal Dress

a In case of shorts we will delete the nets andthen we will

reroute it again

89Short
i

b In case of opens stretch or move the metal layer to empty

tracks
stretchmetal to empty
metal tracks
 ESDViolation Base layer DRC
Based on the the chiptop level decides howmany
tolerance level

ESD cellshas to be present and its respectivelocations

DESD Cells are used to avoid damage from the accumulation of

static charges

D TSMC also gives some

guidlines in and around
these cells

regarding spacing and overlaps

Soif some overlap issue is present with respect to ESD cells this will
be reported in ESD violations

ESD cells and Blok level

4 If chiptop level has given some DEF for
Engineer forget to source this DEF then tool will report error
regarding ESD coverage

ESD P Clamp N Clamp Maro all

fulfill samepurpose
Latch Up Violations Base DRC

Generally well tap coverage and latch up violations are fined at

floorplan stage but if the well tap does not have a fixed
floorplan stage then it will again show latchup
Status at

violation at post route stage

in there are missing well tape so this

If a particular
region
will be reported under batch up violation

Go Violations Metal Drc

This violation is with respect to internal structure ofStandard
cell pins

Sometimes
in order to the min the pin
fill area requirements
dimension is not a straight line So the pin dimensionmay
be in CShape I Shape or reverse C Shape

r b
formation of metalloop
So in this this mutual couplingof Pins
case during fabrication
this might effect the intended functionality of cell
 Dueto the's type of metal loopformation capacitance ofeach
pin will effect the pinsof other standard cells
Spreading the cell can resolve metal G violation

LEC Tools Formality Conformality

Logic Equivalence Check

Inputs to LEC a Golden Netlist Synthesized Netlist

b Revised Netlist Recent Netlist after Each
stage

Alsoknown as layout netlist

Lutputs of LEC
A Mismatch Instance Name report LEC Fait

Ill Passing Instance name report LEC Pass

o o

ye FE
Inverter Buffer
Mismatch Instant.es LEC fail
of

In LEC the tool matches thetwo given netlist with respect toinputs
andoutputs logico orlogic 1
 Stages at which LEC isdone
Reason
forperforming Lec
Post Timing optimization
Synthesis
Ii At placement Data path optimization
Hill Past Cts Data Path and Clock optimizations
v1 Past Routes Datapath optimization

X After Eco Manual Eco's

All the time synthesized netlist is considerd as

golden netlist

your netlist
Question a Functional Eco is introduced in which
If
will
your golden netlist
aFunctional Eco Synthesized netlist will be
mygolden
netlist Given Synthesis team
by

Again after doing the Eco the postroute is done and db is

saved while saving the db you will generate netlist that
will be revised netlist
my
 POWER CHECKS

Inputs I DEF DesignExchange format

TWI Timing window
file
Lili SPEF
Liv Apache Power library

Runtime
Redhawk EM IR Checks
2hrs

output I Vector based IR

report
in vectorless IR report

IR drop IR drop can be defined as the Voltage drop in natal

wires constituting power grid before reaching the Uddpins
of cells
Emigration
Electromigration is the movement
of atoms based on the flow of
current through a material If the currentdensity is highenough
the heat dissipated within the material will be repeteadly break
atoms
from the structure andmove them This will createboth
vacancies vacancies and deposits The vacancies can
grow andeventually
break the circuit connections resulting in open circuits while
the deposits can and eventually close the circuit connections
grow
resulting in short circuit
 so due to EMmetal layers can haveshorts andopens in the design

of metal layers is causedby divergence in atomic flux

Damage
when amount metal leaving and entering a given volume are
ofassociated
unequal the accumulation
on loss materialsresults
of
in damage This results in two types ofinequalities

Atoms Voids Interconnect

Depletion
of failure
hillocks Shorts
Hi Deposition
ofmetals

0 Due to chemical mechanical polishing camp effects which

reduces the thickness ofwires a thinner wire be able
hold a large current density than a wider one
may

In lowernets Resistances M and Capacitance H due to that

D leadsto EM
there is currentdensity which
high
Methods to reduce EM
Rules
By Applying NDR
d
Applying NDR rules mean increasing the width of metal layer
which intern increases the capacitance of the net
therefore electron density is reduced in the nets leading
to
voids hillocks

Always EM will be reported to specific nets

 ANTENNA EFFECT
The antenna effect occurs mainly occurs due to the excessive
accumulation
of charges on a metal interconnect
connected to
agate of transistor during plasma etthing
of the metal interconnect The amount
of accumulated
charge depends on the area ofmetal interconnect connected
to thegate The excessive accumulated Charges getdischarged
through the thin gate on de and it cause permanent
damage to the gate oxide

a The
first method is to reduce the amount
ofchargeaccumulation
and this can be acheived
reducing the area of metal
by
gate oftransistor
interconnect connected to

b the second method is to increase the gate area so the

ratio becomes lesser than the permitted metal
ghettos
to gate area ratio
c The third method is to provide an alternative path to
get discharged
the accumulated charges on the ofthe transistor which is
gate
addition
ofan antenna Diode

Antenna Ratio
Antenna Ratio is theratio ofthe metal area connected tothe
gate
to thetotal gate area

Antenna Checks Physical verification

Antenna Rule

file CALIBER
Antenna Check
results
Design
gaffease

N JumperInsertion
Best to break thelengthy metal into small pieces and
way
using jumpers route them through other metal layers This
process is called jumper insertion ofmetal hopping
Iii Adding antenna diodes Ireversedbiased zener diode

Ciii Laya hopping

In layer hopping transistor uses less no of metal layers
and skippingthese metallayers means lessstaticcharge
 CROSSTALK

Crosstalk noise refers to unintentional coupling

ofactivity
between two

or more signals which can either effect the functionality or

the timing ofthedevises

The effected signal is called victim

The affecting
signal are called aggressors
A net can be victim as well as aggressor
in Crosstalkglitch
Typesofcrosstalk Victim is steady aggressor
is switching

Ciii Crosstalk Delta Delay

Victim and aggressor both
are switchin
 Gosa glitch
I

Aggressor
Do 0

mm Im Iit
GlitchMagnitudes
Magnitude depends on
Ii coupling capacitor between Aggressor victim
Slew of aggressor
tin Victim not ground Capacitor
N Victim net driving strength
Overshoot

victim

Aggressor
AFall glitch

Rise
glitch

Nana
Crosstalk delta
delay
Negative crosstalk delays
when Aggressor and victim are switching in same direction
abath
Aggressor
Do 0

Cotai mtg tcg

Hmm I grit
mm Victim
ig
o IG
fuk delay

Positive Crosstalk
Delays
d
o
Aggressor

Ciotat mtg tcg

Hmm I grit
mm
Victim
o ig
1 Icg
fastadelay
This scenario occurs when aggressor and victim both are
switching
in opposite direction
A The crosstalk can delay the delay ofthe victim only if
the switching windows of aggressor and victim nets
overlap
Crosstalk SetupAnalysis

Setup Equation

Launch Clockpath
Dataggh
Tsetup Jimmy t Capture path

Delay Delay

Worstcrosstalk scenario
forsetup
delay on launchand data path
Positive crosstalk

Negative crosstalk delay on Capture path

Note path crosstalk contributions are consideredfor

The common
both launch and Capture clock paths during setup Analysis

Worstcrosstalk scenario
for hold
Launch Clock path Datapath delay Thold Capture Path Delay

Worst crosstalkscenario for hold

Negative crosstalk impact on launch and data path

Positive crosstalk delay an Capture path

The crosstalk impact onthe common portion the clock

Note
of
tree is not considerd the hold an s
for
 LATCH UP

Latch up issue can be defined as a formation

of a directpath
fromVan to Gnd terminal in the design which will cause
a huge current flow between Uop andgroundterminal

Latchap formation
CMos circuit two parasites BIT
Inside a
get formed and
and connected in such a
way that
these BIT form a PNPN
device

Both the Bit's are connected to eachother in such a that

way
they form aPillPN device The baseof PNP BST is connected
to the collector ofNPN BIT andbase NPN BIT is connected
of
to collector
ofNPN BIT

APNPN device is normally in off state andthere are minimal

current or no current flowthrough it But once the PNPN
 device is
get triggered by its gate signal a large currentstarts
to flow through it and it continues to flow even if the
gate terminal is removed

summary
latch
up is a phenomenon of activating the parasitic Bit's in a

Chaos circuit which forms a low impedance path between

the power and ground terminals

This lowimpedance path draws a large current and heats

up the IC Integrated Chip which cause permanent damage to
IC

TEMP IN VERSION

Normal Case Worstsetup timingcritical corner

Slow process Minimum Voltage high temperature

Temperature Inversion worstsetuptiming critical corner s

Slow process MinimumVoltage low Temperature

Drain Current Id Lunch Was Utn

E
where u is mobility and Ut has threshold Voltage
 uniting
Id a µ
Id Th y 3h
Ith
Temp
1 J UTA

i
to the phenomenon

ofelectrons decreases
of

leading o so 100 1so 7

temperature Cc
to larger delays

In this case Vas Uth is constant because in largertechnology

mode Vans 7 vth

HiTemptnversion
In lower technology nodes Vas has a lower value and

Vas Vin is not constant anymore

Sowith increase in temperature x'decreases and Vas Un

increases therefore In increases leading to less delay This
phenomenon is known as Temperature Inversion
 IME Borrowing
WTime borrowing is the property of latch by virtue ofwhich
a latch can borrow time
a path ending at from next
path in pipeline such that the overall time of two paths
remains the same The time borrowed
by latch fromnest
stage in pipeline is then subtracted from the next path
time

Time borrowing
property of latches is due to the fact that
latches are level sensitive hence
they can capture data
times than a singletime the entire
over a
range of
duration time over which they are transparent Ifthey
of
capture data when they are transparent the same pointof
time can launch the data
for the next stage

Example Time borrowingusing negative triggered latch

 MET A STABILITI
W Metastability is a phenomenon of unstable equilibrium in

digital electronics in whichthe sequential element is not

able to resolve the state of the inputsignal hence the output
goes into unresolved state of an unbound interval oftime

when data transitions close

always this happens
Almost
very
to active edge ofthe clock hence violating setup and hold
requirements

Sincedata makestransition close to active edge ofclock

the flop is not able to capture data completty The flop
starts to capture the data and output also starts to
transition But before output has changed its states the
 Butinput is cut off from the output also starts to transition
before output has changed its state the input is cut off
the output as clock edge has arrived The output is left
from
hanging between o and state
smallinterval
for
0 Thismetastable state can lead to system failure
 LOCK UP LATCH

lock up latch play an important role in time fixing problem especially

hold timing closure A lock up latch is a transparent
for
latch used to avoid largeskew and mitigate the problem in
closing hold due to large uncommon clock path

lock
up
latches are used two scan flopshaving large
in between
hold failure probability due to uncommon clock path so that
there is no issue in
closing timing in a scan chain across
domains in scan shift mode

From timing lockuplatches can be the bestsolution

prospective
to avoid large uncommon path between the clocks of
two flops

lock up latch insertion duringscan sticking

a Concatenation
of Scan chains of different Clockdomains
There is aneed of concatenation of scan chainsof different
domains lock in order to mitigate
up latch is
clock inserted
large clock skew and uncommon path
Scanchain I
I
Yahn
Simms I
 but to eachother
lil Flops within same domain are
far apart
when flops are sitting
far apart the same clock
but within
domain so to avoid
large clock skew and uncommon path
lock up latch is inserted in between

Figs lock
up latch connecting far apartflops within the
same clock domain

0 Issues due to lock up latch insertion

a lock uplatches on the path act as breakpoints across which

flops cannot be recorded

b Due to lock up latch on scan
path tool is not able to
improve the chain length byreordering in efficient
Manner

there is a lock chain

1 Whenever
up latch in the Chain the scan
is broken into smaller segments These segments in turn
have their own start and end points which are fined
and cannot be reordered This results in longer scanchain
wire length
d Poor seem chain
reordering substantially increases the length
of scan chain andhence the congestion which unnecessary
increases
the Capacitance offlops outputs i e more wading of
of A pin which leads to more chippower dissipation

DOUBLE PATTERNINI
The fabrication MOSFET's
i's done using light of Wavelength 193mm
of
in a process called optical lithography Now as we
move lower Technology nodes i e channel below 30 nm the
process can loose its accuracy The quality is lost dueto
the diffraction of light around the corners and edgesofthe
mask since the features are so small compared to the
wavelength oflight The result in uneven edges ofthe mask
since the features are too smaller as compared to the
Wavelen th
of light This results in uneven edges shorts or the
complete absence
of metal to be etched this is where
double
patterning comes into picture

In this method densepatterns

of metals
single mask
in a are

split into 2 different mask that can be interleaved to

get the original pattern as desired and the masks are
colors to the metals
identified by
assigning

Since the masks are fabricated seperatty this can be corrected

This better resolution and higher layout
way we can
get
density
 atom pompom

ibis pjak idgaf ia.gg

iaghga ibook

gig's
intparaara

Maska Task I
Result

HEIRARCHICAL BLOCK

Etangeneration Primetime
This ETMs are generated
by Tempus
Once the placement is done this placement db is given to
Primetime Tempus to generate ETMs
 The tool will generate ETMs which contains theenactinternal delaysof
Childblock

A Inter logic Module ILM's are same like ETMs but this
model is
for Chiplevel
Person I childblock Person 2 Parent
Block

stage Floorplanning is
complete but Person I has to

give floorplan LEF to person2

É Now whenperson 2 is
doing floorplan it mustindu
the floorplan LEF received from
person 1

Stage Person 1 will Complete ETMs will beshared to

Placementand will generate ETMs PlacementLEF parent block for accurate
Etty
Primetime the input Regand Reg out
using for given
Placement db
delays
 Stage 3
Person I will run CTS
Sothis stagecontains our max So clock latencyinformat
insertion delay min insertion ion is needed for building
delay and Clock delay values CTS in parent block

Childblock contains information

clock
my latency
latency information This
Clock
insertion delay is embedded in
makeflow

ay
On post cts we generate EtMs Ms For parent block
Because due heed to notethe while doingpostCTS
irate timing information EtMs

Challenges in hierarchial blocks

a Parent block owner will

get
lesstime to fix violation