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The document outlines the process of physical verification in integrated circuit design, detailing inputs and outputs related to design rule checks (DRC) and electrical rule checks (ERC). It emphasizes the importance of rule decks provided by foundries, which guide the verification tools in identifying device structures and connectivity. Common errors during checks include shorts, opens, component mismatches, and parameter mismatches, which can lead to layout issues if not addressed properly.

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Pavan Chowdary
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12 views3 pages

PD Sign Off

The document outlines the process of physical verification in integrated circuit design, detailing inputs and outputs related to design rule checks (DRC) and electrical rule checks (ERC). It emphasizes the importance of rule decks provided by foundries, which guide the verification tools in identifying device structures and connectivity. Common errors during checks include shorts, opens, component mismatches, and parameter mismatches, which can lead to layout issues if not addressed properly.

Uploaded by

Pavan Chowdary
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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PHYSICAL verification

Inputs in Pastroute db
Iii Ruledeckfile
OASIS GDS II
YI

Runtime
Physical verification caliber
Lhs

Output lil DRC


metallayer Base layer
DRC DRC

II ERC
Ciii Antenna Violation
In Metal Go violations
C Lus
Rule deck Rule deck is given from foundry It is a
file file
set of written in standard verification rule format
Code

It guides the tool to extract the devices and the connectivity


layer information to identifythe layers in used
ofIC's It
contains

file and to match it with the location of layer in Gns


Rule deck also contains device structure definitions

Restore the same post route db in which we were implementing Eco


flow
NERI
ERC involves checking a design for all electrical connection
ERC Will check
Unconnected
Inputandshorted output
Gate should not connect directly to supply Must beconnected
TIE
through high and TIE low cells
Iii VDDLuss errors to be connected to
The wellgeometries med

power ground and if the PG connection is notcomplete


as if the pins are not defined the whole layout can

repost error like MWELL notconnected to Uno


Schematicchecks
Linus Layout Vs

Mo ofdevices in schematic layout


devices in schematic
Type of layout
Kill Moofnets in schematic layout

Typicalerrors during Lus checks


lil Shorts opens
Component mismatch Componentmismatch can happen if
component of different types areused Luiinsteadof Srt
Ciii Missing component tf some expected componentis leftout
from layout
Iv Parameter mismatch Allcomponent has its own properties LUS
tool is configured to compare these properties withsome
tolerance tolerance is not met then it will
if give
parameter mismatch

US layoutnetlist
Spice netlist generatedfromspicetool

4 Overlap whenAND gate is overlapped with buffer toolcannot


understand which all should behere iftonsiders
considered

it asbuffer if spice netlistwell showANDgateandlayoutnettist


shows a buffer it will lead to Los
fait

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