Physical verification is the process of checking layout of an integrated circuit to ensure it

meets the design rules and is manufacturable

Inputs

. GDS : It contains inform ation about M acros(height & width), blockages, pins, layout
boundary (die & core), base layers.It can be in the form of gds.gz/<block_name>.oas.

· LVS.v: It contains the logical connectivity inform ation of the design.

· Rule deck file: It contains the rules specified by foundry which is specific to technology.

· PR Summary : It contains inform ation of instance names and their cell count along with
macros count.

PV flow : DRC → LVS → Antenna → ERC → DFM → Tapeout.

DRC

DRC is the process of checking physical layout data against fab rication specific rules
specified by the foundry to ensure successful fabrication.

Inputs : GDS , rule deck file , layermap file Types: Base DRC, metal DRC

Base DRC: OD(oxide diffusion), Poly, N Well, Substrate

Metal DRC:min width, min spacing, via enclosure, notch spacing, via to via spacing.

LVS

LVS involves comparing the netlist extracted from the layout to the netlist derived from the
schematic.The comparison aims to verify that the two netlists are identical, ensuring that
the physical layout will function as intended according to the schematic design.

Inputs for LVS: GDS ,Rule deck file , netlist, Equivalence file

1.Extraction:the tool analyzes the layout data (GDSII file) to identify and extract all the
electrical components.like transistors, resistors, capacitors, and their connectivity
information.

2. Reduction: the tool combines the extracted components into series and parallel
combinations and generates a spice netlist.

3.Comparison:extracted netlist is compared with schem atic netlist and the tool gives clean
result, if both the netlists match completely and if not, the tool generates error reports

Opens -Shapes of the nets having the sa me layout text on them are not intersecting or
touching causes opens in design.
Shorts: -Flat level shorts : These are the PnR level metal shorts . These can be between
signal to signal, signal to power, power to clock.

-Hierarchical shorts : This can be a short between PnR and Macro internals. In a design, due
to the complexity of the design or due to incorrect settings, it can happen that the PnR to ol
routes nets in a way that creates short with the internal geometries of the macros. It can
also happen if routing blockage is missing in LEF of the macro

-Internal shorts : This can be a fill metal short with cell internals . This occurs when refre
shing of the fill after placing the filler cells is not done.

The antenna effect

When a long metal is connected to gate , there is a charge accumulation on the

metal during Chemical Mechanical Planarization (CMP) stage of fabrication which results in
high voltage at the gate of transistors which causes the gate oxide dam age.

· This is also called as Plasm a ind uced gate oxide damage

1.Metal hopping 3.Reverse bias Antenna diode insertion

2.Floating gate / dum my transistor

insertion

antenna ratio= metal area / gate area

Soft Checks:

• Soft checks verifies the layout GDS for electrical correctness.

· Soft checks will perform mainly for prim ary power related issues.· Here, we check for the
shorts and opens that occur in power mesh.·

· Any two different nodes are connected with a high resistive path orconnecting without any
physical routing layer(Metals), it' s called a Soft check. The issues are

PG shorts and PG opens Nwell shorts and opens

Substrate shorts and opens Ports shorts

Stamping Conflict

Electrical Rule Check(ERC)

This check is used to ensure that the electrical characteristics of a design meet specific
standards and do not violate any electrical rules set by design technology

· ERC verifies the Electrical behavior of the design

ERC checks are run to identify the following errors in layout:

. Unconnected input and shorted output

· Gate should not get directly connected to supply(Must be connected through Tie high and
Tie low cells).

· The well geometries need to be connected to power /ground.

· PG shorts & opens

· If there are floating transistors , floating gate pins , floating wells

· Incorrect electrical connections.

. Second ary power open.

· Isolated cell without nwell continuity due to missing filler cells

Soft check is the subset of ERc.

· Signal shorts are not reported in ERC. This check is done based on cells not metal layers

Desian for Manufacturability (DFM)

is a set of techniques used in VLSI layoutdesign to make the m anufacturing process easier
and less expensive and to minimize the risk of costly manufacturing issues and im prove the
overall yield of the product

Max density - having more metal layers -To decreasing the density of metals using etching
process /Min density - having less metal layers - to add dummy metal layers in empty
spaces

PERC(Programmable Electrical Rule Check):

These reliability checks are frequently electrostatic discharge (ESD) related, but they can
extend to other checks as well, including electrical overstress (EOS), dielectric breakdown,
etc.

· PERC will check the electrical related issues based on netlist

· PERC is used to perform electrostatic discharge (ESD) and multiple power dom ain checks

+Netlist Checks, Checks that can be done entirely on a netlist; no layout data is necessary.
+Netlist Driven Layout Checks. Checks that are done on the layout, but a preceding analysis
of a netlist is done to determine the area of interest for the layout check.

+Current Density Checks. Checks done on the layout to determ ine the current carrying
capability of the layout in the ESD discharge path.

+Point-to-Point(P2P) Resistance Checks. Checks done on the layout to determine the

resistance of the ESD discharge path, to verify that it is low resistance ensuring the current
will choose that path.

XOR Check:

XOR Check is used after Base Tape Out(BTO) to check whether there is any modification in
the design or not.

· If there is a difference between BTO and ECO , the output of XOR check will be 1.

· This check is typically run after a metal spin, where the original and modified database are
compared

(EM) is the movement of metal atoms in interconnects due to high current density. Fixes-
Widening the Wire, Use Higher Metal Layers, Add More Vias , Increase Wire Length.

IR drop in the power delivery network due to resistance in metal wires, which can cause
cells to get less voltage than required. Add decap cells

: Latch up refers to short circuit/low impedance path formed between power andground
rails in an IC leading to high current and damage to the IC

· It occurs due to interaction between parasitic pnp and npn transistors.

Guard ring · ESD protection technigues

• Well tap cells · Add Gold impurities in substrate.

· Isolation trench · Avoid Forward bias of source and drain.

· Epitaxial layer

CMOS secind order effects.

1)DIBL(Drain-Induced Barrier lowering) 5)channel length modulation

2)Surface saturating 6)1mpact iconization

3)Hot carrier effect

4) velocity saturation