How to build an AI startup on

open source RISC-V Cores

Frédéric Desbiens frederic.desbiens@eclipse-foundation.org
Jeremy Bennett jeremy.bennett@embecosm.com
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 ● How to Build an AI Startup
Agenda
● Are there any open source,
industrial-grade RISC-V cores?
● Do you want a side of software?

● Join the fun!

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 How to Build an AI startup with
Open Source RISC-V Designs
Case Studies

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AI for Inference

Meta’s in-house AI Accelerator

● Training is infrequent, but
inference is forever
● Enterprise Datacenters
● Significant power consumption
(100’s of watts)
● Large engineering teams

● Yet, a simple design

○ Make a Processing Element (PE)
○ Copy it a few times
○ Add some IO’s
○ Be the best in suggesting yet another Cat video (YACV) to watch
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AI at the Edge

Axelera.AI edge AI
● Low-power (Could run on battery)
● Suitable for deeply embedded
applications
● Available in M.2 form factor

● Again, a simple design

○ Again: Common building blocks
with RISC-V Controller
○ Important: Security on-chip!

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Generic AI Building Blocks

Andes Technology licensed AI building blocks

● RISC-V (maybe with Vector)
● DMA, General Matrix Multiply
● Extensive software stack
○ Compiler
○ RTOS
○ IDE
○ …

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AI in Your Pocket

AI powered by RISC-V is already in your phone!

● Several ARM-based SOCs feature specialised
cores powered by RISC-V
○ Yes, including “fruity” ones
○ Excludes the Nokia 3390

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 Where do I Find Industrial-Grade
Open Source RISC-V Cores?
OpenHW Foundation has them?

For Free?
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 ready
In Develop.
OpenHW RISC-V Roadmap Planning*

CVP8*
Ariane

CV64A60A
CVA6
X

CV32A60X CV32A65X*
CVW
Coherence

CV32E40PX CV32E41
CV32E40P CV32E40X
lowRISC: IBEX
zeroRiscy
CVE4 CV32E40S
OpenHW’s roadmap is member-driven and may change without further notice
*Cores marked as “in planning” are under discussion or expected to be added
CVE2 RI5CY but not yet started, nor guaranteed to be delivered

ARM equivalent ARM M0+ ARM M4/M33 ARM M7 / A7 / A55 …..

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OpenHW Foundation Deliverables

● License
○ Apache 2.0/Solderpad
● Cores
○ System Verilog

RISC-V Core
Families
CVE2, CVE4, CVA6

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OpenHW Foundation Deliverables

● License
○ Apache 2.0/Solderpad
● Cores
○ System Verilog
● Test benches
○ UVM, System Verilog, a little python and tcl
● Tools

System Verilog 2.0

○ Siemens Mentor Questa, Cadence, Synopsys,
Imperas, …

UVM
RISC-V Core
Families
CVE2, CVE4, CVA6

Verification

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OpenHW Foundation Deliverables

● License Linux
○ Apache 2.0/Solderpad
● Cores RTOS, Bare metal
○ System Verilog
Compilers ( LLVM / GCC )
● Test benches
○ UVM, System Verilog, a little python and tcl
● Tools

System Verilog 2.0

○ Siemens Mentor Questa, Cadence, Synopsys,
Imperas, …

UVM
● Support software
○ Compilers (LLVM, GCC) RISC-V Core
○ RTOSes (FreeRTOS, Eclipse ThreadX) Families
CVE2, CVE4, CVA6

Verification

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OpenHW Foundation Deliverables

● License Linux
○ Apache 2.0/Solderpad
● Cores RTOS, Bare metal
○ System Verilog
Compilers ( LLVM / GCC )
● Test benches

Documentation
○ UVM, System Verilog, a little python and tcl
● Tools

System Verilog 2.0

○ Siemens Mentor Questa, Cadence, Synopsys,
Imperas, …

UVM
● Support software
○ Compilers (LLVM, GCC) RISC-V Core
○ RTOSes (FreeRTOS, Eclipse ThreadX) Families
CVE2, CVE4, CVA6
● Documentation

Verification

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OpenHW Foundation Deliverables

● License Linux
○ Apache 2.0/Solderpad
● Cores RTOS, Bare metal

FPGA board images / SoCs

○ System Verilog
Compilers ( LLVM / GCC )
● Test benches

Documentation
○ UVM, System Verilog, a little python and tcl
● Tools

System Verilog 2.0

○ Siemens Mentor Questa, Cadence, Synopsys,
Imperas, …

UVM
● Support software
○ Compilers (LLVM, GCC) RISC-V Core
○ RTOSes (FreeRTOS, Eclipse ThreadX) Families
CVE2, CVE4, CVA6
● Documentation
● FPGA Board Images / SOCs
Verification
○ Digilent Nexys A7
○ Digilent Genesys 2
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 Get Your Compiler Right

Software Will Make or Break Your AI Chip

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OpenHW Software Task Group

● Chair: Paolo Savini, Embecosm

● Define, develop and support toolchains, operating system ports and firmware
for the cores and IP developed within the OpenHW Foundation
● Active Projects:
○ GCC / LLVM
○ IDEs
○ FreeRTOS
○ CORE-V MCU SDK
● Emerging: Cooperation with the Eclipse ThreadX project

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Compilers

● The plan is for all compiler patches to go upstream

○ GCC 14.1 has 5 of the 8 CV32E40Pv2 ISA extensions
○ Clang/LLVM 18 has 4 of the 8 CV32E40Pv2 ISA extensions
○ Support for the rest available out of tree pending upstreaming
● Features:
○ Core awareness
○ Assembler and built-in support of all CORE-V ISA extensions
○ Automatic code generation for key CORE-V ISA extensions
■ including hardware loop support

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Operating Systems and Virtualisation

● QEMU
● RTOS support
○ FreeRTOS => 10.3.0
○ Zephyr 2.4, 2.5, …
● Upcoming: Eclipse ThreadX support
○ Only OSS RTOS certified for safety-critical applications
○ Best-performing open source RTOS
● Linux
○ Linux Kernel 6.2 Support
○ uBoot and OpenSPI
○ Buildroot
○ Fedora and RedHat working on Linux Support

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CORE-V IDE

● CORE-V IDE is an open-source project

under the SW TG at the OpenHW Group
● Based on Eclipse IDE, with native support
for CORE-V development
● Includes the GCC Toolchain for CORE-V
● OpenOCD Debug Support
● “Ready-to-run” examples for Digilent
FPGA boards
● Getting started guides

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CORE-V MCU Non-Interleaved Memories
32KB 32KB
Interleaved Memories

SRAM SRAM 112KB 112KB 112KB 112KB

Bank Bank SRAM SRAM SRAM SRAM
0 1
● Real Time Operating System
(e.g. FreeRTOS) capable JTAG Tightly Coupled Data Memory Interconnect
~400+MHz CV32E4 MCU instr data
2x 2x 2x
System CLK
UART DP DP
● Embedded FPGA fabric with Dual-Clock
2x Me Me
hardware accelerators from QSPI FIFO m m
QuickLogic I/O 4X MAC

I/O MUX
eFPGA CLK CV32E40P
PADs 2xI2Cm

● Multiple low power uDMA eFPGA

GPIO Event Unit
peripheral interfaces (SPI, 24KB RAM, 4 MACs, 1024 SLC, 4K FFs

GPIO, I2C, HyperRAM, CAM

Dual-Clock
CAMIF, etc) for interfacing
SDIO FIFO
with sensors, displays, and
connectivity modules IO_CTRL APB / Peripheral Interconnect
● Built in 22FDX with
GlobalFoundries Clock / Reset Debug
PLLs System Timer
Generator CLK Unit

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CORE-V DevKit

● CORE-V MCU SoC

○ CV32E40P processor core
○ Quicklogic ArticPro eFPGA
○ Global Foundries 22FDX
● Ashling Opella-LD onboard JTAG debug module
● USB-C for terminal and onboard debug access
● JTAG connector for external debug access
● Espressif AWS IoT ExpressLink Module for AWS IoT
cloud interconnect
● mikroBUS onboard socket, allowing access to a vast
range of mikroBUS modules
● 40 pin expansion header
● I2C temperature sensor

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Low Power AI Edge Inference Demonstrator

● Developed in 2021 at the University of

Southampton
● How few instructions are needed to
accelerate AI inference?
● CV32E40P extended with 8 RVV
instructions
● Result: 5-7x speedup in TinyMLPerf
benchmark
● Video: youtu.be/t0Fpy4TzLUE
● GitHub: github.com/AI-Vector-Accelerator

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 Why Work With Us?

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Why Build Your Own AI Chip With our IP?

● RISC-V is already everywhere in AI

● OpenHW as a platform to host, maintain and verify high quality,
industrial-grade cores
○ Open
○ Transparent
○ Meritocratic
● Academia and industry working together
● Fully open cores (RTL, Verification)
○ Challenge our RTL!
● The Eclipse Foundation is the largest open source organisation in Europe

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Call to Action

● Learn
○ Visit openhwfoundation.org
○ Watch OpenHW TV episodes on YouTube
● Try
○ Get the code on GitHub
● Engage

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Towards a
Comprehensive IoT and SDV Building Blocks

IoT Building Blocks

Open Source Integrated Development
Environments (IDEs)
Embedded
RISC-V stack Real-Time Operating
Systems

Tool Chains

Processor Cores
and IP

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 Thank you!

openhwfoundation.org

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