Design and Implementation of A 12-bit 40MS/s

Pipeline ADC
Lan Dai Hui-Zhen Jin Wen-Kai Liu
College of Information Engineering,
North China University of Technology,
perfect_dai@163.com

Abstract—A 12-bits 40MS/s pipeline analog-to-digital con- analog converter (MDAC) including a S/H operation, coarse
verter (ADC) in SMIC035um mixed-signal process is D/A conversion, subtraction(SDAC), and residue amplifier[1-
presented in this paper. The ADC adopts methods below to 4]. Systemic simulation shows that pipeline ADC with 12
improve its performance, a novel bootstrapped switch is identical stages in architecture can achieve less resolution error
used to sample and hold circuit in order to improve the comparatively, so this architecture is adopted in this 12-bit
resolution of ADC, a residue amplifier with gain-boost to 40MS/s pipeline ADC (Fig.1).
eliminate gain error. This ADC achieves a SFDR of 65dB, a
SNDR of 56dB, a SNR of 56.9 dB, an ENOB of 9.1bits with
the resolution of all the measure instruments are below
10bits.

I. INTRODUCTION
ADC is the key components in communication and video
system. With development of these electronics system, high-
resolution and high-speed ADCs are becoming more and more
important. Pipeline ADCs are the architecture of choice for
Fig.1, Structure of the proposal pipeline ADC
ADCs used in such fields, and are ideally suited for realizing
resolution above 10 bits.
In operation, each stage (stage i) takes the residual voltage
from the previous stage as the input signal. The flash ADC
This paper presents a 12 bits 40MS/s pipeline ADC
inside the stage quantizes the input signal into 2 bits. The
implemented in 0.35um CMOS technology. In section II the recovered level is subtracted from the input signal and amplified
selecting Pipeline ADC's structure is introduced. Block circuits, by 2 to generate the residual signal for the next stage. Delay
such as bootstrap switch used in sample-and-hold (S/H) stage elements synchronize the stage outputs and generate the 12 bits
and operational amplifier applied in pipeline stage, are described digital code.
in section III. The measurement results including SNR, SNDR,
SFDR and ENOB are presented in section IV, and at the same III. CIRCUIT IMPLEMENTATION
time carries out analysis aiming at the results. Finally, conclusion
is drawn in section V. This section mainly focuses on the design and
implementation of the principal circuit of pipeline ADC, such as
II. PIPELINE ADC STRUCTURE S/H and Residue amplifier of MDAC circuits, and puts forward
specific circuits accordingly.
Fig. I shows the structure of the proposal pipeline ADC, it
consists of a cascade of a S/H stage and 12 l.5bit-pipeline stages, A. Sample -and-Hold Amplifier(S/H)
some digital circuits including delay elements and digital error
correction logic if desired. All of the pipeline stages are 1) S/H Archtechture: There are Two differential S/H
identical in architecture, but sampling capacitances are scaled
architectures for pipeline ADC. The first architecture, referred
down along stages. Each pipeline stage comprises a sub-analog-
to-digital converter (SADC) and the multiplying digital-to- to as a charge-transferring S/H, acquires the input signal on the

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input capacitors during the track phase, and transfers only the ADC very well.
differential charge to the feedback capacitors during the hold
phase. Since the common-mode charge remains in the input
capacitors, the S/H can handle a wide range of input common
mode signal, and is excellent for single-ended applications. The
second architecture, referred to as a flip-around S/H, acquires
the input on the input capacitors during the track phase, and
flips the same capacitors to the output during the hold phase.
The feedback factor , which measures the portion of the output
signal being fed back to the amplifier’s input, of the charge
transferring S/H is ideally 0.5, while the ideal feedback factor of
the flip-around THA is 1, neglecting parasitic capacitance.
There are two advantages of the flip-around architecture. The
Fig.3, Bootstrap Switch
first advantage is lower power consumption. Since its feedback
factor is twice as high, the flip-around THA ideally needs only B. Residue amplifier of MDAC
50% of the GBW to achieve the same closed-loop bandwidth. As for the MADC of the first stage in 12-bits 40MS/s
This results in significant power saving. The second advantage pipeline ADC, its performance must meet the criterion as
is lower noise. During the track phase, neglecting parasitic follows at least, 12 bits resolution and 40MHz sample rate. The
capacitance, the input-referred noise power of the charge- residue amplifier is the most important circuit and affects the
transferring S/H is twice as much as the flip-around S/H. So performance of MDAC directly. Since residue amplifier operates
flip-around S/H is adopted ( fig.2 ). The S/H includes common in close-loop state, its open-loop gain and unity-gain band-
mode feedback which is consists of switch capacitor circuit, width(GWB) must satisfy the follow functions[7].
operation amplifier(OTA) and bootstrap switch.
A 0 > 2 N +1 / f ˄1˅

3k(N + 1) ln 2
GBW > ˄2˅
2π Tf
Where N=12, f represents the feedback factor and its ideal
value is 0.5, k is similar to 1 and related to parasitic capacitance,
sample capacitance and load capacitance, T is the clock period
and is equal to 12.5ns as for a 12 bits 40MS/s pipeline ADC .
Considering enough margin the open-loop gain of residue
amplifier must exceed 90dB, GBW is greater than 760MHz, and
its setting time must below 10ns. The proposal circuit is shown
in Fig.4.
Fig.2 Architecture of the proposal S/H
2) bootstrap switch:
Sample switch in S/H can cause accuracy and linearity
problem due to the clock feed-through, charge injection and on
resistanceˈso special care on switch selection should be taken.
Many researchers putted attention to it and achieved some
attractive bootstrap switches. Compared with the circuits of
bootstrap switch this paper presents (Fig.3), A. M. Abo. putted
forward a bootstrap switch which connects net n1 and the input
point through a NMOS transistor controlled by the voltage of
net n3, but it can’t eliminate the affect of charge injection
effectively[5]. Mikko Waltari improved the circuit above and
presented a modified bootstrap switch which controls the
NMOS transistor by clock signal, it solves charge injection well
but can cause the switch in a shut state when the amplitude of
input signal is large enough[6]. Fig.4, Residue Amplifier

In this paper a novel bootstrap switch(Fig.3) is presented, The supply voltage of the selecting technology is 3.3V, and
compared with the above bootstrap switch it adopts a CMOS it is easy to produce 2V swing of differential output signal, for
complementary switch to control the sample of input signal, and it that reason telescope operation amplifier which can provide
extends the range of input signal, eliminates the affect of charge high gain is the first choice for residue amplifier, at the same
injection quite well and the on resistance is low. With the novel time residue amplifier enhances its gain through gain-boost
bootstrap switch, the S/H achieves 87.558 dB spurious-free circuit, and uses switch capacitor circuits as the common mode
dynamic range(SFDR), 80.337 dB signal-to-noise ratio(SNDR), feed-back to improve the amplitude of output signal. The
and 84.012 dB total harmonic distortion(THD). All the simulation results of the residue amplifier show it gets 105dB
parameters meet the requirements of a 12 bits 40MS/s pipeline open-loop gain, 60 degree phase margin, 1.1GHz GWB, and in

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close-loop state can gain 12 bits setting resolution within 7.2ns lack of equipment, so the real performance of the ADC may be
when the input is step signal. All the performance parameter better than the test results.
above meets the requirement of this 12 bits 40MS/s pipeline V. CONCLUSION
ADC.
This paper describes the design of a 12 bits 40MS/s pipeline
IV. EXPERIMENTAL RESULTS
ADC implemented in SMIC 0.35um mixed-signal process. It
The converter is fabricated in SMIC 0.35um mixed-signal demonstrates that a switched-capacitor pipeline ADC with a
process. The right part of Fig.5 shows the die photo- micrograph, high-performance bootstrap switch and a MDAC designed well
with a total die area of hmm2 , The THA is located at the is capable of achieving 12 bits linearity without dithering or
lower right corner of the chip, the first stage is just above the calibration. The results show all the design including the novel
THA, the 12 l.5bit-pipeline stages are on the middle of the die, bootstrap switch and residue amplifier with gain-boost meet the
and the bandgap voltage reference lies in the lower left part. requirements of a 12 bits 40MS/s pipeline ADC.
REFERENCES
[1] Siddharth Devarajan and Larry Singer, “A 16-bit, 125 MS/s,
385 mW, 78.7 dB SNR CMOS Pipeline ADC”, IEEE J.
Solid-State Circuits, vol. 44, No.12, pp. 3305-3313, Dec.
2009
[2] Stephen H. Lewis and Paul. Gray, “A Pipelined 5-Msample/s
9-bit Analog-to-Digital Converter”, IEEE J. Solid-State
Circuits, vol. 22, issue.12,pp. 954-961, Dec. 1987
[3]Y. Chiu, P. R. Gray, and B. Nikolic, “A 14-b 12-MS/s
CMOS pipeline ADC with over 100-dB SFDR,” IEEE J.
Fig.5, The PCB testing system and photomicrograph of the die Solid-State Circuits, vol. 39, No. 12, pp. 2139–2151, Dec.
The testing circuit includes Low-pass / band-pass filter, 2004.
single end to differential converter, low dropout regulator, et al. [4] A. M. Abo and P. R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s
The sine signal produced by signal generator is filtered and CMOS pipeline analog-to-digital converter,” IEEE J. Solid-
transformed to differential signal, then transported to the ADC, State Circuits, vol. 34, no. 5, pp. 599–606, May 1999.
the analog circuits get power through low dropout regulator. All
the output digital code of the tested ADC is stored by logic [5] A. M. Abo. “Design for Reliability of Low-voltage
analyzer and analysed with the math tool of Matlab. When the Switched-capacitor Circuit”, Ph.D. Thesis, University of
frequency of the input signal is 400KHz, Spectrum analysis of California, Berkeley, 1999, pp: 53-59, 86-90.
the output codes show the ADC achieves 65dB SFDR, 56 dB [6] Mikko Waltari, “Circuit Techniques for Low-voltage and
SNDR, 56.9 dB SNR and 9.1bits ENOB(Fig.6). High-speed A/D Converters”, Ph.D. Thesis, Helsinki
FFT PLOT University, 2002
0
1st
2nd
[7] Sumanen l, Wal. Tarim, Halonen K, “Optimizing the
-20
SFDR=65dB
3rd number of parallel channels and the stage resolution in time
SNDR=56dB 4th
5th
interleaved pipeline A/ D converters”, IEEE Int. Symp.
SNR=56.9dB
-40 6th Circuit and System . Geneva , Switzerland. 2000 : 613-616.
AMPLITUDE (dB)

7th
8th
-60 9th

-80

-100

-120
0 1 2 3 4 5 6 7 8 9 10
ANALOG INPUT FREQUENCY (MHz)

Fig.6 FFT plots with fin=400KHz

When sample clock frequency changes from 5MHz to
60MHz, the ENOB of this 12 bits 40MS/s pipeline ADC varies
from 7.8bits to 9.1 bits. The worst result appears when the clock
frequency is 60MHz, the main reason is that the setting time
problem of amplifier is becoming worse with the increasing
frequency of clock. At the same time when this frequency is too
low charge leakage limits the resolution of the ADC.
The results is obtained under the condition that the resolution
of all the testing equipment is 10 bits below, and clock and input
signal are generated by the same signal generator because of the

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