DIGITAL LOGIC DESIGN lab

20A04303P

LABORATORY MANUAL

Ii B.TECH iI SEMESTER regulation: r20

AND GATE: 74XX08

Connection Diagram Functional Table

OR GATE:74XX32

Connection Diagram Functional Table

EXPERIMENT NO: DATE:

LOGIC GATES
AIM:
To perform an experiment on logic gates by using digital ICs 74XX.

APPARATUS REQUIRED:

S.No Name of the components Range Quantity

74LS00-QUAD 2-INPUT NAND GATE

74LS02- QUAD 2-INPUT NOR GATE
74LS04- HEX NOT GATE 1
1 -
74LS08- QUAD 2-INPUT AND GATE
74LS32- QUAD 2-INPUT OR GATE
74LS86- QUAD 2-INPUT EX-OR GATE

2 Fixed power supply 5V 1

LEDS
3 - 2
Connecting Wires
4 - 10
Bread Board
5 - 1

PROCEDURE FOR HARDWARE VERIFICATION:

1. Check the components for their working.

2. Connect the circuit on breadboard according to the logic symbol.
3. Apply +5V for Vcc & 0V for GND.
4. Provide input data and verify the outputs through LEDs for all input combinations
and compare with truth table.
NAND GATE:74XX00

Connection Diagram Functional Table

NOR GATE:74XX02

Connection Diagram Functional Table

EXCLUSIVE-OR GATE:74XX86

Connection Diagram Functional Table

EXCLUSIVE-NOR GATE:74XX266

Connection Diagram Functional Table

Z= A’B’+AB

NOT GATE:74XX04

Connection Diagram Functional Table: Y=A’

RESULT:
Realization using NOR gates

Given Boolean Expression is Y=AB’+CD’

EXPERIMENT NO: DATE:

 BOOLEAN FUNCTION USING LOGIC GATES
AIM:
To perform an experiment on Boolean function by using digital ICs 74XX.

APPARATUS REQUIRED:

S.No Name of the components Range Quantity

74LS00-QUAD 2-INPUT NAND GATE

74LS02- QUAD 2-INPUT NOR GATE
1
1 74LS04- HEX NOT GATE -
74LS08- QUAD 2-INPUT AND GATE
74LS32- QUAD 2-INPUT OR GATE

2 Fixed power supply 5V 1

LEDS
3 - 2
Connecting Wires
4 - 10
Bread Board
5 - 1

PROCEDURE FOR HARDWARE VERIFICATION:

1. Check the components for their working.

2. Connect the circuit on breadboard according to the logic symbol.
3. Apply +5V for Vcc & 0V for GND.
4. Provide input data and verify the outputs through LEDs for all input combinations
and compare with truth table.
RESULT:
FULL ADDER :

Logic Diagram Functional Table

EXPERIMENT NO: DATE:
FULL ADDER

AIM:

To perform an experiment on Full Adder by using digital ICs.

APPARATUS REQUIRED:

S.No Name of the components Range Quantity

74LS08, 74LS32 Each 1

1 -
74LS86, 74LS04

2 Fixed power supply 5V 1

LEDS
3 - 2
Connecting Wires
4 - 10
Bread Board
5 - 1

THEORY:
A half adder has two inputs, generally labelled A and B, and two outputs, the sum S and carry C. S
is the two-bit XOR of A and B, and C is the AND of A and B. Essentially the output of a half adder is the
sum of two one-bit numbers, with C being the most significant of these two outputs. A half adder is a
logical circuit that performs an addition operation on two binary digits. The half adder produces a sum and
a carry value which are both binary digits. The drawback of this circuit is that in case of a multibit
addition, it cannot include a carry.

A full adder has three inputs - A, B, and a carry in C, such that multiple adders can be used to add larger
numbers. To remove ambiguity between the input and output carry lines, the carry in is labelled Ci or Cin
while the carry out is labelled Co or Cout. A full adder is a logical circuit that performs an addition
operation on three binary digits. The full adders produces a sum and carry value, which are both binary
digits

The Half-Subtractor is a combinational circuit which is used to perform subtraction of two bits. It
has two inputs, X(minuend) and Y(subtrahend) and two outputs D (difference) and B (borrow).
 The full subtractor is a combinational circuit which is used to perform subtraction of three input bits
the minuend X, subtrahend Y, and borrow Bin .The full subtractor generates two output bits the difference
D and borrow Bout .Bin is set when the previous digit is borrowed from X.Thus, Bin is also subtracted
from X as well as the subtrahend Y. Like the half subtractor, the full subtractor generates a borrow out
when it needs to borrow from the next digit. Since we are subtracting Y and Bin from X, a borrow out
needs to be generated when X<Y+B in .When a borrow out is generated, 2 is added in the current digit.This
is similar to
The subtraction algorithm in decimal. Instead of adding 2, we add 10 when we borrow.

Therefore, D=X-Y-Bin+2Bout

PROCEDURE FOR HARDWARE VERIFICATION:

1. Check the components for their working.

2. Connect the circuit on breadboard according to the logic symbol.
3. Apply +5V for Vcc & 0V for GND.
4. Provide input data and verify the outputs through LEDs for all input combinations
and compare with truth table.
RESULT:
74LS151 MULTIPLEXER:
LOGIC SYMBOL TRUTH TABLE

LOGIC DIAGRAM FOR 8X1 MUX:

EXPERIMENT NO: DATE:
8X1 MULTIPLEXER-74X151

AIM:

To construct multiplexer circuit using IC-74X151 .

APPARATUS REQUIRED:

Name of the components Range Quantity

S.No

1 74LS151 - 1

2 5V 1
Fixed power supply
3 LEDS - 2

4 Connecting Wires - 10

5 Bread Board - 1

THEORY:

The multiplexers contains full on-chip decoding unit to select desired data source. The 74151
selects one-of-eight data sources. It has a enable input which must be at a LOW logic level to enable these
devices. These perform parallel-to-serial conversion. The 74150 selects one-of sixteen data sources.
The 74155 sends the data source to one of four data destinations. It has a enable input which must
be at a LOW logic level to enable these devices. The binary decoder with enable input connected to data
line known as De multiplexer.
PROCEDURE FOR HARDWARE VERIFICATION:

1. Check the components for their working.

2. Connect the circuit on breadboard according to the logic symbol.
3. Apply +5V for Vcc & 0V for GND.
4. Provide input data and verify the outputs through LEDs for all input combinations
and compare with truth table.

RESULT:
74LS138 DECODER

LOGIC SYMBOL TRUTH TABLE

NOTE1 G2 : G2A+G2B

LOGIC DIAGRAM
EXPERIMENT NO: DATE:
74X138 – DECODER

AIM:
To perform an experiment on 74LS138 by using hardware circuit & verify its function using truth table.

APPARATUS REQUIRED:

S.No Name of the components Range Quantity

74LS138 1
1 -

Fixed power supply

2 5V 1

LEDS
3 - 8

Connecting Wires
4 - 10

Bread Board
5 - 1

THEORY: The 74138 decodes one-of-eight lines based upon the conditions at the three binary select inputs and the
three enable inputs. Two active low and one active-high enable inputs reduce the need for external gates or inverters
when expanding. A 24-line decoder can be implemented with no external inverters, and a 32-line decoder requires
only one inverter. An enable input can be used as a data input for demultiplexing applications.
The Binary Encoder encodes the data input into coded output, but simultaneously two input
data appears it cannot give the correct output code. In order to overcome the ambiguities in binary encoder. Priority
encoder was designed by assigning the priorities to the input. If simultaneously two inputs are present it gives the
output code to highest priority data input request.
PROCEDURE FOR HARDWARE VERIFICATION:

1. Connect the circuit on breadboard according to the logic diagram

2. Apply +5V for Vcc & 0V for GND
3. Outputs will be verified for different combinations of inputs.

RESULT:
D-FLIP FLOP:

Connection Diagram Functional Table

 EXPERIMENT NO: DATE:

74X74 D Flip Flop

AIM:

To perform an experiment on 74LS74 by using hardware circuit & verify its function using truth table.

APPARATUS REQUIRED:

S.No Name of Apparatus Range Quantity

1 74LS74 - 1

2 5V 1
Fixed power supply

3 LEDS - 2

4 Connecting Wires - 10

5 Bread Board - 1

THEORY:
This device contains two independent positive edge-triggered D flipflop with complementary
outputs. The information on the D input is accepted by the flip-flops on the positive going edge of the
clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the
rising edge of the clock. The data on the D may be changed while the clock is low or high without
affecting the outputs as long as the data setup and hold times are not violated. A LOW logic level on the
preset or clear inputs will set or reset the outputs regardless of the logic levels on the other inputs.
PROCEDURE FOR HARDWARE VERIFICATION:

1. Make the connections as per the logic symbol.

2. Apply +5V for Vcc & 0V for GND
3. Verify the output for different combinations of inputs.

RESULT:
CIRCUIT IMPLEMENTATION

FIG: J – K FLIP – FLOP CIRCUIT

Characteristic eqn Q t+1 =JQ+KQ

Fig: Pin diagram of 7476

EXPERIMENT NO: DATE:

 JK FLIPFLOP

AIM: Verification of functional tables of (i) JK Edge triggered Flip–Flop (ii) JK Master Slav Flip– Flop
APPARATUS REQUIRED:

7485,7408, 8411,7421, 7432, digital IC Trainer Kit, Patch Chord.

THEORY:

Basically Flip-Flops are the bistable multi vibrators that stores logic 1 and logic 0.Shift registers, memory,
and counters are built by using Flip – Flops. Any complex sequential machines are build using Flip –
Flops. Sequential circuit (machine) output depends on the present state and input applied at that instant.
Mealy Machine is one whose output depends on both the present state and the input. Moore machines
one whose output depends only on the present state of the sequential circuit. Note that the truth table of J –
K Flip – Flop is same as the Master – Slave.
J – K Flip Flop and they must be remain same because IC – 7476 is –ve edge trigged flip
– flop and we know that race around condition is eliminated by edge triggered flip – flop. Another way of
eliminating race around condition is by using Master – Slave J –K Flip – Flop. When J = K = 1 (logic HIGH), J – K
Flip – Flop changes output many times for single clock pulse, it is Smaller than width of the clock pulse

PROCEDURE:
1) Connections are made as per the circuit diagram.
2) Apply negative edge triggered ,positive edge triggered and level sensitive clock pulses required
3) Verify the truth tables of all flip flops
4) Switch off the power supply and disconnect the circuit
 Master Slave J K Flip – Flop

Truth Table of JK FlipFlop

Inputs Outputs
Q J K Qt + 1
0 0 0 0
0 0 1 0

0 1 0 1
0 1 1 1

1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
RESULT:
LOGIC DIAGRAM:

FIG: RING COUNTER

EXPERIMENT NO: DATE:

 RING COUNTER

AIM: Design a four-bit ring counter using D Flip–Flops/JK Flip Flop.

APPARATUS REQUIRED:

Digital IC trainer kit, IC 7476

THEORY:

Ring counter and Johnson counters are basically shift registers Ring

Ring counter:

It is made by connecting Q&Q‟ output of one JK FF to J&K input of next FF respectively.

The output of final FF is connected to the input of first FF. To start the counter the first
FF is set by using preset facility and the remaining FF are reset input. When the clock arrives
the set condition continues to shift around the ring ,

As it can be seen from the truth table there are four unique output stages for this counter. The
modulus value of a ring counter is n, where n is the number of flip flops. Ring
counter iscalled divided by N counter where N is the number of FF

PROCEDURE:

1. Set up the ring counter and set clear Q outputs using PRESET and apply monopulse.
2. Note down the state of the ring counter on the truth table for successive clock 0.

RESULT:

LOGIC DIAGRAM:
EXPERIMENT NO: DATE:

JOHNSON’S COUNTER
AIM: Design a four bit Johnson’s counter using D Flip-Flops/JK Flip Flops.

APPARATUS REQUIRED:

Digital IC trainer kit, IC 7476

THEORY:

Johnson counter (Twisted ring counter)

The modulus value of a ring counter can be doubled by making a small change in the ring counter circuit.
The Q‟ and Q of the last FFS are connected to the J and K input of the first FF respectively. This is the
Johnson counter. Initially the FFs are reset. After first clock pulse FF0 is set and the remaining FFs are
reset. After the eight clock pulse all the FFS are reset. There are eight different conditions creating a mode
8 Johnson counter. Johnson counter is called a twisted ring counter or divide by 2N counter.

PROCEDURE:

1.Set up the Johnson counter and set clear Q outputs using PRESET and apply mono pulse.
2.Note down the state of the Johnson counter on the truth table for successive clock 0.

RESULT:

LOGIC DIAGRAM:
 fig: universal shift register diagram

EXPERIMENT NO: DATE:

UNIVERSAL SHIFT REGISTER

AIM: Verify the operation of 4-bit Universal Shift Register for different Modes of operation.

APPARATUS REQUIRED: IC 74291, IC 74395

THEORY:

Shift registers are the sequential logic circuits that can store the data temporarily and provides the data
transfer towards its output device for every clock pulse. These are capable of transferring/shifting the data
either towards the right or left in serial and parallel modes. Based on the mode of input/output operations,
shift registers can be used as a serial-in-parallel-out shift register, serial-in-serial-out shift register, parallel-
in-parallel-out shift register, parallel-in- parallel-out shift register. Based on shifting the data, there are
universal shift registers and bidirectional shift registers. Here is a complete description of the universal
shift register.
What is a Universal Shift Register?
Definition: A register that can store the data and /shifts the data towards the right and left along with the
parallel load capability is known as a universal shift register. It can be used to perform input/output
operations in both serial and parallel modes. Unidirectional shift registers and bidirectional shift registers
are combined together to get the design of the universal shift register. It is also known as a parallel-in-
parallel-out shift register or shift register with the parallel load.
Universal shift registers are capable of performing 3 operations as listed below.
Parallel load operation – stores the data in parallel as well as the data in parallel
Shift left operation – stores the data and transfers the data shifting towards left in the serial path
Shift right operation – stores the data and transfers the data by shifting towards right in the serial path.
Hence, Universal shift registers can perform input/output operations with both serial and parallel loads.
Serial input for shift-right control enables the data transfer towards the right and all the serial input and
output lines are connected to the shift-right mode. The input is given to the AND gate-1 of the flip-flop -1
as shown in the figure via serial input pin.
Serial input for shift-left enables the data transfer towards the left and all the serial input and output lines
are connected to shift-left mode.
In parallel data transfer, all the parallel inputs and outputs lines are associated with the parallel load.
Clear pin clears the register and set to 0.
CLK pin provides clock pulses to synchronize all the operations.
In the control state, the information or data in the register would not change even though the clock pulse is
applied.
If the register operates with a parallel load and shifts the data towards the right and left, then it acts as a
universal shift register.
From the above figure, selected pins the mode of operation of the universal shift register. Serial input shifts
the data towards the right and left and stores the data within the register.
S0 S1 Mode of Operation
0
0 Locked state (No change)
0
1 Shift-Left
Shift-Right
1 0
Parallel Loading
1 1
 Universal shift register

Clear pin and CLK pin are connected to the flip-flop.

M0, M1, M2, M3 are the parallel inputs while F0, F1, F2, F3 are the parallel outputs of flip-flops
When the input pin is active HIGH, then the universal shift register loads / retrieve the data in parallel. In
this case, the input pin is directly connected to 4×1 MUX
When the input pin (mode) is active LOW, then the universal shift register shifts the data. In this case, the
input pin is connected to 4×1 MUX via NOT gate.
When the input pin (mode) is connected to GND (Ground), then the universal shift register acts as a Bi-
directional shift register.
To perform the shift-right operation, the input pin is fed to the 1st AND gate of the 1st flip-flop via serial
input for shit-right.
To perform the shift-left operation, the input pin is fed to the 8th AND gate of the last flip-flop via input
M.
If the selected pins S0= 0 and S1 = 0, then this register doesn’t operate in any mode. That means it will be
in a Locked state or no change state even though the clock pulses are applied.
If the selected pins S0 = 0 and S1 = 1, then this register transfers or shifts the data to left and stores the
data.
If the selected pins S0 = 1 and S1 = 0, then this register shifts the data to right and hence performs the
shift-right operation.
If the selected pins S0 = 1 and S1 = 1, then this register loads the data in parallel. Hence it performs the
parallel loading operation and stores the data.

PROCEDURE:

1. S0 and S1 are the selected pins that are used to select the mode of operation of this register. It
may be shift left operation or shift right operation or parallel mode.
2. Pin-0 of first 4×1Mux is fed to the output pin of the first flip-flop. Observe the connections as shown
in the figure.
3. Pin-1 of the first 4X1 MUX is connected to serial input for shift right. In this mode, the register shifts
the data towards the right.
4. Similarly, pin-2 of 4X1 MUX is connected to the serial input for shift-left. In this mode, the universal
shift register shifts the data towards the left.
5. M1 is the parallel input data given to the pin-3 of the first 4×1 MUX to provide parallel mode
operation and stores the data into the register.
6. Similarly, remaining individual parallel input data bits are given to the pin-3 of related 4X1MUX to
provide parallel loading.
7. F1, F2, F3, and F4 are the parallel outputs of Flip-flops, which are associated with the 4×1 MUX.
 RESULT:

Counter States F/F Output Counter States F/F Output

QA QB QC Truth tables QA QB QC
0 0 0 0 7 1 1 1
1 0 0 1 6 1 1 0
2 0 1 0 5 1 0 1
3 0 1 1 4 1 0 1
4 1 0 0 3 0 1 1
5 1 0 1 2 0 1 0
6 1 1 0 1 0 0 1
7 1 1 1 0 0 0 0
 Up counter Down counter

FIG: 3- BIT ASYNCHRONOUS UP COUNTER

EXPERIMENT NO: DATE:

MOD-8 RIPPLE COUNTER

 AIM: Draw the circuit diagram of MOD-8 ripple counter and construct a circuit using T-
Flip-Flops and Test It with a low frequency clock and sketch the output wave forms.

APPARATUS REQUIRED:
IC 7474 (T- Flip-flop), Digital Trainer Kit, patch cords, +5V power supply.
THEORY:
synchronous counter:

A digital counter is a set of flip flop. An Asynchronous counter uses T flip flop to perform a
counting function. The actual hardware used is usually J-K flip-flop connected to logic 1.
In ripple counter, the first flip-flop is clocked by the external clock pulse & then each successive
flip-flop is clocked by the Q or /Q‘ output the previous flip-flop. Therefore in an asynchronous
counter the flip-flop are not clocked simultaneously. The input of MS-JK is connected to VCC
because when both inputs are one output is toggled. As MS-JK is negative edge triggered at each
high to low transition the next flip-flop is triggered. On this basis the design is done for MOD-8
counter.
1) Up Counter:
Fig shows 3 bit Asynchronous Up Counter. Here Flip-flop A act as a MSB Flip-flop and Flip-
flop C can act as a LSB Flip-flop. Clock pulse is connected to the Clock of flip-flop C. Output of
Flip-flop C (Qc) is connected to clock of next flip-flop(i.e. Flip-flop B) and so on. As soon as
clock pulse changes output is going to -change(at the negative edge of clock pulse) as a Up count
sequence. For 3 bit Up counter Truth table is as shown below.
2) Down Counter:
Fig shows 3 bit Asynchronous Down Counter. Here Flip-flop a act as a MSB Flip-flop
and Flip-flop C can act as a LSB Flip-flop. Clock pulse is connected to the Clock of flip-flop C.
Output of Flip-flop C (Qc‘) is connected to clock of next flip- flop (i.e. Flip-flop B) and so on.
As soon as clock pulse changes output is going to change(at the negative edge of clock pulse) as
a down count sequence. For 3 bit down counter Truth table is as shown below.
 FIG: 3- BIT ASYNCHRONOUS DOWN COUNTER

3 Bit Asynchronous Up Counter

CLK

Qa 0 0 1 0 1 0 1
3

Qb 0 0 1 1 0 0 1 1

Qc 0 0 0 0 1 1 1 1

3 Bit Asynchronous Down Counter

CLK

Qc 0 1 1 0 1 0 1
0

Qb 0 1 1 0 0 1 1 0

Qa 0 0 0 0
1 1 1 1

PROCEDURE:

Department of ECE, JNTUACEK, Kalikiri

 1. Make the connections as per the logic diagram.
2. Connect +5v and ground according to pin configuration.
3. Apply diff combinations of inputs to the i/p terminals.
4. Note o/p for summation.
5. Verify the truth table.

RESULT:

Department of ECE, JNTUACEK, Kalikiri

 MOD -8 COUNTER

FIG: 3 BIT SYNCHRONOUS COUNTER

Present count Next count

TRUTH TABLE: QC QB QA QC QB QA
0 0 0 0 0 1
0 0 1 0 1 0
QC QB QA 0 1 0 0 1 1
0 0 0 0 1 1 1 0 0
0 0 1 1 0 0 1 0 1
0 1 0 1 0 1 1 1 0
0 1 1 1 1 0 1 1 1
1 0 0 1 1 1 0 0 0
1 0 1
1 1 0
1 1 1
0 0 0

T-FLIPFLOP EXCITATION TABLE:

States Input
Present Next T
0 0 0
0 1 1
1 0 1
1 1 0

EXPERIMENT NO: DATE:

Department of ECE, JNTUACEK, Kalikiri

 MOD–8 SYNCHRONOUS COUNTER

AIM: To Design MOD–8 synchronous counter using T Flip-Flop.

APPARATUS REQUIRED:
IC 7474 (T- Flip-flop), Digital Trainer Kit, patch cords, +5V power supply.

THEORY:

A counter in which each flip-flop is triggered by the output goes to previous flip-
flop.As all the flip-flops do not change states simultaneously in asynchronous counter,
spike occur at the output. To avoid this, strobe pulse is required. Because of the
propagation delay the operating speed of asynchronous counter is low. This problem
can be solved by triggering all the flip-flops in synchronous with the clock signal and
such counters are called synchronous counters.

PROCEDURE:
 Check all the components for their working.
 Insert the appropriate IC into the IC base.
 Make connections as shown in the circuit diagram.
 Verify the Truth Table and observe the outputs.

RESULT:

Department of ECE, JNTUACEK, Kalikiri

LOGIC DIAGRAM:

Fig:1-BIT COMPARATOR

TRUTHTABLE

INPUTS OUTPUTS
A B A>B A=B A<B
0 0 0 1 0
0 1 0 0 1
1 0 1 0 0
1 1 0 1 0

EXPERIMENT NO: DATE:

SINGLE BIT COMPARATOR

Department of ECE, JNTUACEK, Kalikiri
 AIM: Draw the circuit diagram of a single bit comparator and test the output.

APPARATUSREQUIRED:
IC7400,IC7410,IC7420,IC7432,IC7486,IC7402,IC7408,IC7404,

IC7485,Patch Cords & IC Trainer Kit.

PROCEDURE:
1. Check all the components for their working.
2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit diagram.
4. Verify the Truth Table and observe the outputs.

RESULT:

CIRCUITDIAGRAM:

Department of ECE, JNTUACEK, Kalikiri

 FIG:SEVEN SEGMENT DISPLAY

TRUTHTABLE:
Display
D C B A a b c d e f g
Number

0 0 0 0 0 0 0 0 0 0 1

0 0 0 1 1 0 0 1 1 1 1

0 0 1 0 0 0 1 0 0 1 0

0 0 1 1 0 0 0 0 1 1 0

0 1 0 0 1 0 0 1 1 0 0

0 1 0 1 0 1 0 0 1 0 0

0 1 1 0 1 1 0 0 0 0 0

0 1 1 1 0 0 0 1 1 1 1

1 0 0 0 0 0 0 0 0 0 0

1 0 0 1 0 0 0 1 1 0 0

EXPERIMENT NO: DATE:

7 SEGMENT DISPLAY

Department of ECE, JNTUACEK, Kalikiri

 AIM: Construct 7 Segment Display Circuit Using Decoder and 7 Segment LED and
test it.

APPARATUSREQUIRED:
IC 7447, IC FND507
THEORY:

The functions of LT, RBI, RBO and BI are given below. LT This is called the LAMP
TEST terminal and is used for segment testing. If it is connected to logic ‘0’ level, all
the segements of the display connected to the decoder will be ON. For normal decoding
operation, this terminal is to be connected to logic ‘1’ level. RBI For normal decoding
operation, this is connected to logic‘1’ level. If it is connected to logic ‘0’, the segment
outputs will generate the data for normal 7-segment decoding, for all BCD inputs
except Zero. Whenever the BCD inputs correspond to Zero, the 7-segment display
switches off. This is used for zero blanking in multi-digit displays.BI If it is connected
to logic ‘0’ level, the display is switched-off irrespective of the BCD inputs. This is
used for conserving the power in multiplexed displays. RBO This output is used for
cascading purposes and is connected to the RBI terminal of the succeeding stage.
PROCEDURE:
Setup the Ckt as shown in fig.
Apply logic‘0’level to LT and observe the seven segments of the LED. All the
segments must be ON.
Apply logic‘0’level to BI/RBO and observe the seven segments of the LED. All the
segments must be OFF.
Apply logic ‘1’ to LT and RBI and observe the number displayed on the LED for all
the inputs 0000 through 1111.This is the normal decoding mode.
Apply logic ‘1’ to LT and logic ‘0’ to RBI, and observe the BI/RBO output and the
number displayed on the LED for all the inputs 0000 through 1111.This is the normal
decoding mode with zero blanking.

RESULT:

Department of ECE, JNTUACEK, Kalikiri