Microprocessors & Interfacing

UNIT-I

MICROPROCESSOR EVOLUTION AND INTRODUCTION

Microprocessor:
It is a semiconductor device consisting of electronic logic circuits manufactured by using
either a Large scale (LSI) or Very Large Scale (VLSI) Integration Technique. It includes the ALU,
register arrays and control circuits on a single chip.

The microprocessor has a set of instructions, designed internally, to manipulate data and
communicate with peripherals. This process of data manipulation and communication is
determined by the logic design of the microprocessor called the architecture.

Microcontroller:
A microcontroller is a compact integrated circuit designed to govern a specific operation in
an embedded system. A typical microcontroller includes a processor, memory and input/output
(I/O) peripherals on a single chip.

Microprocessor VS Microcontroller:

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Origin of Microprocessor:
The breakthrough in transistor technology led to the introduction of minicomputers of the
1960s and the personal computer revolution of the 1970s. Intel was the first MPU producer and has
been holding a large share in the world market of this product. Microprocessors evolution is
categorized into five generations first, second, third, fourth, and fifth generations.

First Generation (1971-73):

The microprocessors that were introduced in 1971 to 1972 were referred to as the first
generation systems. Intel Corporation introduced 4-bit 4004 at 108 kHz, the first microprocessor in
1971, co-developed by Busicom, a Japanese manufacturer of calculators. In 1972, Intel made the 8-
bit 8008 and 8080 microprocessors.

Second Generation (1974-78)

Very large-scale integration (VLSI) lead to chips which had speeds up to hundreds of
millions of switching per second. The second generation marked the beginning of very efficient 8 –
bit microprocessors. Some of the popular processors were Motorola’s 6800 and 6809 and Intel’s
8085, Zilog’s Z80. The distinction between the first and second generation devices was primarily
the use of newer semiconductor technology to fabricate the chips. They were manufactured using
NMOS technology.

Third Generation (1979-80)

Introduced in 1978, dominated by Intel’s 8086 and the Zilog Z8000, which were 16-bit
processors with minicomputer-like performance, have 16-bit arithmetic and pipelined instruction
processing. Transistor counts about 250,000. Motorola’s MC68020 incorporated an on-chip cache
for the first time and the depth of the pipeline increased to five or more stages. HMOS - speed-
power-product of HMOS is four times better than that of NMOS. HMOS can accommodate twice
the circuit density compared to NMOS.

Fourth Generation (1981-95)

Designs with more than a million transistors in a package. 32 bits microprocessors

introduced – Intel 80386 and Motorola 68020/68030. Fabricated using low-power version of the
HMOS technology called HCMOS.

Fifth Generation (1995 till date)

Employed decoupled super scalar processing. Chips carry on-chip functionalities and
improvements in the speed of memory and I/O devices Design surpassed 10 million transistors per
chip. Introduction of 64-bit processors Intel leads the show with Pentium, Celeron and dual and
quad core processors working with up to 3.5GHz speed.

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Comparison of General Purpose Processors:

Classification of Microprocessors:
Microprocessors can be classified based on their purpose, architecture, specifications and
applications. Based on the size of the data that the microprocessor can handle, they are
classified as 4-bit, 8-bit, 16-bit, 32-bit and 64-bit microprocessors. Based on the application of
the processors, they are classified as

i) General purpose processors,

ii) Microcontrollers and
iii) Special purpose processors

General Purpose Processors:

• General purpose processors are those which are used in general computer system
integration and can be used by the programmer for any application.
• Common microprocessor such as Intel 8085 to Intel Pentium processors are examples of
general purpose processors.
Microcontrollers:
• Microcontrollers are the microprocessor chips within built hardware for the memory and
ports.
• These chips are can be programmed by the user for any generic control applications.

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Special Purpose Processor:

• Special purpose processors are designed specifically to handle special functions required
for an application.
• The digital signal processors are examples for the special purpose processors and these
have special instructions to handle signal processing.
• The Application Specific Integrated Circuits (ASIC) chips are also the examples of this
category of microprocessors.

Classification of Microprocessor Based on Architecture and Hardware:

Based on the architecture and hardware of the processors, they are classified as

a. RISC processors
b. CISC processors
c. VLIW processors and
d. Superscalar processors.
Reduced Instruction Set Architecture:
RISC stands for Reduced Instruction Set Computer. It is designed to reduce the execution
time by simplifying the instruction set of the computer. Using RISC processors, each instruction
requires only one clock cycle to execute results in uniform execution time. This reduces the
efficiency as there are more lines of code; hence more RAM is needed to store the instructions.
The compiler also has to work more to convert high-level language instructions into machine
code.
Some of the RISC processors are
Power PC : 601, 604, 615, 620
DEC Alpha : 210642, 211066, 21068, 21164
MIPS : TS (R10000) RISC Processor
PA-RISC : HP 7100LC
Architecture of RISC Processor:

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The major characteristics of a RISC processor are as follows −
• It consists of simple instructions.
• It supports various data-type formats.
• It utilizes simple addressing modes and fixed length instructions for pipelining.
• It supports register to use in any context.
• One cycle execution time.
• “LOAD” and “STORE” instructions are used to access the memory location.
• It consists of larger number of registers.
• It consists of less number of transistors.

Complex Instruction Set Computing Architecture:

CISC stands for Complex Instruction Set Computer. It is designed to minimize the number
of instructions per program, ignoring the number of cycles per instruction. The emphasis is on
building complex instructions directly into the hardware.

The compiler has to do very little work to translate a high-level language into assembly
level language/machine code because the length of the code is relatively short, so very little RAM
is required to store the instructions.

Some of the CISC Processors are

• IBM 370/168
• VAX 11/780
• Intel 80486

Its architecture is designed to decrease the memory cost because more storage is needed in
larger programs resulting in higher memory cost. To resolve this, the number of instructions per
program can be reduced by embedding the number of operations in a single instruction.
Architecture of CISC Processor:

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Characteristics of CISC processor are

• Variety of addressing modes.

• Larger number of instructions.
• Variable length of instruction formats.
• Several cycles may be required to execute one instruction.
• Instruction-decoding logic is complex.
• One instruction is required to support multiple addressing modes.

Very Long Instruction Word (VLIW) processors:

• VLIW Processors have instruction composed of many machine operations which can be
executed in parallel.
• This is achieved by many functional units operating in parallel.
• It has large number of registers and instruction level parallelism.
Superscalar Processors:
• Superscalar processors are using complex hardware to achieve parallelism.
• It is possible to have overlapping of execution of instructions in order to increase the
speed of execution.

Special Processors:
These are the processors which are designed for some special purposes. Few of the special
processors are briefly discussed

Coprocessor
A coprocessor is a specially designed microprocessor, which can handle its particular
function many times faster than the ordinary microprocessor.

For example − Math Coprocessor.

Some Intel math-coprocessors are −

• 8087-used with 8086

• 80287-used with 80286
• 80387-used with 80386
Input/Output Processor:
It is a specially designed microprocessor having a local memory of its own, which is used
to control I/O devices with minimum CPU involvement.

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For example −

• DMA (direct Memory Access) controller

• Keyboard/mouse controller
• Graphic display controller
• SCSI(Small Computer System Interface) port controller
DSP (Digital Signal Processor)
This processor is specially designed to process the analog signals into a digital form. This
is done by sampling the voltage level at regular time intervals and converting the voltage at that
instant into a digital form. This process is performed by a circuit called an analogue to digital
converter, A to D converter or ADC.

A DSP contains the following components −

➢ Program Memory − It stores the programs that DSP will use to process data.

➢ Data Memory − It stores the information to be processed.

➢ Compute Engine − It performs the mathematical processing, accessing the program from
the program memory and the data from the data memory.

➢ Input/Output − It connects to the outside world.

Its applications are −

• Sound and music synthesis

• Audio and video compression
• Video signal processing
• 2D and 3d graphics acceleration.
For example − Texas Instrument’s TMS 320 series, e.g., TMS 320C40, TMS320C50.

TYPES OF MEMORY:

➢ A microcomputer memory can be logically divided into four groups

a. Processor memory/ register

b. Cache memory

c. Primary or Main Memory

d. Secondary memory

➢ Processor Memory refers to a set of CPU registers. Processor registers are the first set of
storage device available for the programmers to store any data.

➢ But they are generally few in number up to about few tens to hundreds.
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➢ As these registers are available within the processor, they are the fastest memory registers.

➢ The main disadvantage is the cost involved which forces to restrict the number to very few
registers of few bytes.

➢ Cache memory is the fastest external memory to the processor and they are placed close to
the processor.

➢ The instructions to be executed are placed in cache memory for access by the processor.
These are in few kilobytes in size.

➢ These are semiconductor RAMs and are volatile.

➢ The processor will fetch the next instruction from the cache memory and if the instruction
is not in cache, it will refer to primary memory.

➢ Primary memory is the storage area from which all the programs are executed.

➢ All the programs and corresponding data must be within primary memory prior to
execution.

➢ The size of primary memory is much larger compared to processor memory and cache
memory but its operating speed is slower than them.

➢ The primary memory in a system varies from few Kilobytes to about 1 Megabyte.

➢ These are not accessed directly and very frequently by the microprocessor in a computer
system.

➢ They comprises of slow devices such as magnetic tapes and optical disks.

➢ Sometimes they are referred to as auxiliary or backup store.

➢ Stored information in a magnetic tape or magnetic disk is not lost when the power is turned
off.

PRIMARY MEMORY CLASSIFICATION:

➢ Primary memory normally includes ROM (Read Only Memory) and RAM (Random
Access Memory).

➢ Microprocessor based systems have at least one RAM and ROM chips in it.

➢ Information stored in semiconductor random access memories RAM will be lost if the
power is turned off.

➢ This property is known as volatility and hence, RAMs are usually called volatile memories.

➢ ROM is a nonvolatile memory.

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➢ As the name implies, a ROM permits only a read access. There are many kinds of this
category.

➢ Mask Programmable ROMS are custom made for the customer and their contents are
programmed by the manufacturer.

➢ Since they are mass produced, they are inexpensive. The customer can not erase or
program it afterwards.

➢ Programmable ROMs are the devices which can be programmed by the user at the user’s
place or field.

➢ The main disadvantage of PROMs is that they cannot be erased and reprogrammed

EPROM:

➢ Erasable and Programmable ROMs (EPROMs) allow the erasure and reprogramming of
the content by the user.

➢ In an EPROM, programs are entered using electrical impulses and the stored information is
erased using UV rays.

➢ Electrically Erasable PROMs (EEPROMs) or Electrically Alterable ROMs (EAROMs)

allow the users to erase its contents by electrical means and also reprogramming by electrical
signals.

➢ EEPROMs are different from RAMs in the electrical signal required to erase and program.
EEPROMs require a higher voltage for erasing and programming other than the normal 5V supply.

Static RAM:

➢ In a semiconductor memory constructed using bipolar transistors, the information is stored

in the form of voltage levels in flip-flops.

➢ Such memories are called static RAMs because stored information remains constant for
some period of time.

➢ Static RAM maintains information in active circuits, power is required even when the chip
is inactive or standby mode.
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➢ Hence, static RAMs require large power supplies.

➢ Also each static RAM cell is about four times larger in area than an equivalent dynamic
cell.

Dynamic RAM:

➢ Semiconductor memories designed using MOS transistors, the information is held in the
form of electrical charges in capacitors.

➢ The stored charge has the tendency of get leaked away. These memories are referred to as
dynamic RAMs.

➢ In order to prevent any information loss, dynamic RAMS have to be refreshed at regular
intervals. Refreshing means boosting the signal level and writing it back.

➢ This activity is performed using a hardware unit called “refresh logic”.

INPUT AND OUTPUT DEVICES:

➢ The input/output or I/O section allows the computer to take in data from the outside world or
send data to the outside world.

➢ Peripherals such as keyboards, video display terminals, printers, and modems are connected
to the I/O section.

➢ These allow the user and the computer to communicate with each other.

➢ The actual physical devices used to interface the computer buses to external systems are often
called ports.

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Function of I/O Ports:

➢ An input port allows data from a keyboard, an A/D converter, or some other source to be read
into the computer under control of the CPU.

➢ An output port is used to send data from the computer to peripheral devices, such as a video
display terminal, a printer, or a D/A converter.

➢ Simplest type of input or output port is just a set of parallel D flip-flops.

➢ If they are being used as an input port, the D inputs are connected to the external device, and
the Q outputs are connected to the data bus which can take the data to the CPU.

➢ Data will then be transferred to the data bus when they are enabled by a control signal from the
CPU.

➢ In a system, where they are being used as an output port, the D inputs of the latches are
connected to the data bus, and the Q outputs are connected to some external device.

➢ Data sent out on the data bus by the CPU will be transferred to the external device when the
latches are enabled by a control signal from the CPU.

Input Devices:

➢ Input devices include typewriter-like keyboards; hand-held devices such as the mouse,
trackball, joystick, and special pen with pressure sensitive pad; and microphones.

➢ The simplest input device is a switch.

➢ Input devices can also be sensors that provide information about their environment
temperature, pressure, and so forth to a computer.

➢ Another direct-entry mechanism is the optical laser scanner (e.g., scanners used with point-
of-sale terminals in retail stores) that can read bar-coded data or optical character fonts.

Output Devices:

➢ An output is any device through which the user can receive the results from the computer.

➢ The output can be any display which can be changing fast or hard copies print out. Some
other forms of output are sounds and alarms.

➢ The simplest output devices used in almost all microprocessor based systems or computer
systems are the LEDs or the seven segment LED displays and LCD.

➢ The advanced video display terminals (either cathode-ray tubes or liquid crystal displays),
ink-jet and laser printers, are the common output devices nowadays.

➢ Some output devices can be used to directly control machineries. Some devices, such as
display terminals with touch screen, may provide both input and output.

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➢ Modems and other network interface cards can also be called as output devices as they
enable the transmission and reception of data between computers.
TECHNOLOGICAL IMPROVEMENTS:
• Technology improvements are taking place fast in the microprocessor, microcomputer and
personal computer systems.

• The technical and research improvements in the field of microprocessor technology is listed
below.

❖ Increase in data bus / address bus width. The processing capability of the
microprocessor can be drastically improved by increasing data size.
• Increase in speed
❖ As the data to be processed by the microprocessors and computers increased in
volume, it became a necessity to increase the speed of the processor.

❖ By high speed processors, the user can get the results faster even with the large
data volumes.

• Reduction in size and increase in capability

❖ The trend in microprocessor technology is to include large amount of peripherals

such as memory and I/O ports within a single chip.

❖ Microcontrollers are manufactured by all semiconductor manufacturers in this

aspect.

❖ Development in the processing of large scale integration has lead to small chips of
microprocessors with large built in peripherals.

❖ We have now processors with large amount of flash memory available in the
market.

• Development of external peripherals

❖ The use of computers in all the fields have resulted in the development of many fast
and advanced peripheral devices to be interfaced with the microprocessor.

❖ For example, applications of microprocessors in medical field has resulted in many

handheld electronic devices with the specialized input sensors and output printers
etc.

❖ The faster peripherals can increase the speed of processor execution and a good
user interface.

• Increase in memory size and speed

❖ The developments in the Integrated circuit technology have lead to developments in

the reduction of the memory size and the increase in memory speed.
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❖ This reduces the memory access time of the processor and so will result in the
higher speed of execution.

❖ Also more amount of memory per unit area is possible.

• The microprocessors are largely used in handheld devices operated from the battery source.

• This has resulted in the research towards reduction of power consumption in the
microprocessor chips.

• As power consumption is reduced, the devices can work for more time with one full charge
of batteries.

• There are many devices operating at 3.3V are even lower and have low power
consumption.
Microprocessor Based System:

The Central Processing Unit (CPU):

This device coordinates all operations of a micro computer. It fetches programs stored in
ROM‟s or RAMs and executes the instructions depending one a specific Instructions set, which is
characteristic of each type of CPU, and which is recognized by the CPU.

The Random Access Memory (RAM): Temporary or trail programs are written.

Besides the ROM area, every computer has some memory space for temporary storage of
data as well as for programs under development. These memory devices are RAMs or Read – write
memory. The contents of it are not permanent and are altered when power is turned off. So the
RAM memory is considered to be volatile memory.

The Read Only Memory (ROM): Permanent programs are stored.

The permanent memory device/area is called ROM, because whatever be the memory
contents of ROMs, they cannot be over written with some other information. For a blank ROM,
the manufacturer supplies the device without any inf. In it, information can be entered electrically
into the memory space. This is called burning a ROM or PROM.

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Data Lines/Data Bus:

The number of data lines, like add. Lines vary with the specific CPU .The set of data lines
is database like the address bus unlike add. Bus, the data bus is bidirectional because while the
information on the address Bus always flows out of the CPU; the data can flow both out of the
CPU as well as into the CPU.

Control lines/ control Bus:

The no. of control lines also depends on the specific CPU one is using.
Ex: Read; Write lines are examples of control lines
Clock: The clock is a symmetrical square wave signal that drives the CPU

The Salient Features of 8085 Microprocessor:

➢ 8085 is an 8 bit microprocessor, manufactured with N-MOS technology.
➢ It has 16-bit address bus and hence can address up to 216 = 65536 bytes (64KB) memory
locations through A0-A15.
➢ The first 8 lines of address bus and 8 lines of data bus are multiplexed AD0 - AD7. Data
bus is a group of 8 lines D0 - D7.
➢ It supports external interrupt request.8085 consists of 16 bit program counter (PC) and
stack pointer (SP).
➢ Six 8-bit general purpose register arranged in pairs: BC, DE, HL.
➢ It requires a signal +5V power supply and can operate at 3 MHz, 5 MHz and 6 MHz Serial
in/Serial out Port.
➢ It is enclosed with 40 pins DIP (Dual in line package).
ARCHITECTURE OF 8085:

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8085 Bus Structure: Address Bus:

➢ The address bus is a group of 16 lines generally identified as A0 to A15.

➢ The address bus is unidirectional: bits flow in one direction-from the MPU to peripheral
devices.

➢ The MPU uses the address bus to perform the first function: identifying a peripheral or a
memory location.

Data Bus:

➢ The data bus is a group of eight lines used for data flow.

➢ These lines are bi-directional - data flow in both directions between the MPU andmemory
and peripheral devices.

➢ The MPU uses the data bus to perform the second function: transferring binaryinformation.

➢ The eight data lines enable the MPU to manipulate 8-bit data ranging from 00 to FF (28
=256 numbers).

➢ The largest number that can appear on the data bus is 11111111.

Control Bus:

➢ The control bus carries synchronization signals and providing timing signals.
➢ The MPU generates specific control signals for every operation it performs. These signals
are used to identify a device type with which the MPU wants to communicate.

Registers of 8085:

➢ The 8085 have six general-purpose registers to store 8-bit data during program execution.

➢ These registers are identified as B, C, D, E, H, and L.

➢ They can be combined as register pairs-BC, DE, and HL-to perform some 16-bit
operations.

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Accumulator (A):

➢ The accumulator is an 8-bit register that is part of the arithmetic/logic unit (ALU).
➢ This register is used to store 8-bit data and to perform arithmetic and logical operations.
➢ The result of an operation is stored in the accumulator.

Flags:

➢ The ALU includes five flip-flops that are set or reset according to the result of an operation.
➢ The microprocessor uses the flags for testing the data conditions.
➢ They are Zero (Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags. The
most -commonly used flags are Sign, Zero, and Carry.
The bit position for the flags in flag register is,

1. Sign Flag (S):

After execution of any arithmetic and logical operation, if D7 of the result is 1, the sign flag
is set. Otherwise it is reset. D7 is reserved for indicating the sign; the remaining is the magnitude of
number. If D7 is 1, the number will be viewed as negative number. If D7 is 0, the number will be
viewed as positive number.

2. Zero Flag (z):

If the result of arithmetic and logical operation is zero, then zero flag is set otherwise it is
reset.

3. Auxiliary Carry Flag (AC):

If D3 generates any carry when doing any arithmetic and logical operation, this flag is set.
Otherwise it is reset.

14. Parity Flag (P):

If the result of arithmetic and logical operation contains even number of 1's then this flag
will be set and if it is odd number of 1's it will be reset.

5. Carry Flag (CY):

If any arithmetic and logical operation result any carry then carry flag is set otherwise it is
reset.
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Arithmetic and Logic Unit (ALU):

➢ It is used to perform the arithmetic operations like addition, subtraction, multiplication,

division, increment and decrement and logical operations like AND, OR and EX-OR.
➢ It receives the data from accumulator and registers.
➢ According to the result it set or reset the flags.

Program Counter (PC):

➢ This 16-bit register sequencing the execution of instructions.

➢ It is a memory pointer. Memory locations have 16-bit addresses, and that is why this is a
16-bit register.
➢ The function of the program counter is to point to the memory address of the next
instruction to be executed.
➢ When an opcode is being fetched, the program counter is incremented by one to point to the
next memory location.

Stack Pointer (SP):

➢ The stack pointer is also a 16-bit register used as a memory pointer.

➢ It points to a memory location in R/W memory, called the stack.
➢ The beginning of the stack is defined by loading a 16-bit address in the stack pointer
(register).

Temporary Register: It is used to hold the data during the arithmetic and logical operations.
Instruction Register: When an instruction is fetched from the memory, it is loaded in the
instruction register.
Instruction Decoder: It gets the instruction from the instruction register and decodes the
instruction. It identifies the instruction to be performed.

Serial I/O Control: It has two control signals named SID and SOD for serial data transmission.
Timing and Control unit:
➢ It has three control signals ALE, RD (Active low) and WR (Active low) and three status
signals IO/M(Active low), S0 and S1.

➢ ALE is used for provide control signal to synchronize the components of microprocessor
and timing for instruction to perform the operation.

➢ RD (Active low) and WR (Active low) are used to indicate whether the operation is reading
the data from memory or writing the data into memory respectively.
➢ IO/M(Active low) is used to indicate whether the operation is belongs to the memory or
peripherals.
➢ If,

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Interrupt Control Unit:

➢ It receives hardware interrupt signals and sends an acknowledgement for receiving the interrupt
signal.

Pin Diagram and Pin Description Of 8085

8085 is a 40 pin IC, DIP package. The signals from the pins can be grouped as follows
1. Power supply and clock signals
2. Address bus
3. Data bus
4. Control and status signals
5. Interrupts and externally initiated signals
6. Serial I/O ports

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1. Power supply and clock frequency signals

• Vcc + 5 volt power supply

• Vss Ground
• X1, X2: Crystal or R/C network or LC network connections to set the frequency of internal
clock generator.
• The frequency is internally divided by two. Since the basic operating timing frequency is 3
MHz, a 6 MHz crystal is connected externally.
• CLK (output)-Clock Output is used as the system clock for peripheral and devices
interfaced with the microprocessor.

2. Address Bus:

• A8 - A15 (output; 3-state)

• It carries the most significant 8 bits of the memory address or the 8 bits of the I/O address;

3. Multiplexed Address / Data Bus:

• AD0 - AD7 (input/output; 3-state)

• These multiplexed set of lines used to carry the lower order 8 bit address as well as data
bus.

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• During the opcode fetch operation, in the first clock cycle, the lines deliver the lower order
address A0 - A7.

• In the subsequent IO / memory, read / write clock cycle the lines are used as data bus. The
CPU may read or write out data through these lines.

4. Control and Status signals:

• ALE (output) - Address Latch Enable.

• This signal helps to capture the lower order address presented on the multiplexed address /
data bus.

• RD (output 3-state, active low) - Read memory or IO device.

• This indicates that the selected memory location or I/O device is to be read and that the data
bus is ready for accepting data from the memory or I/O device.

• WR (output 3-state, active low) - Write memory or IO device.

• This indicates that the data on the data bus is to be written into the selected memory
location or I/O device.

• IO/M (output) - Select memory or an IO device.

• This status signal indicates that the read / write operation relates to whether the memory or
I/O device.

• It goes high to indicate an I/O operation.

• It goes low for memory operations.

5. Status Signals:

• It is used to know the type of current operation of the microprocessor.

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6. Interrupts and externally initiated operations:

• They are the signals initiated by an external device to request the microprocessor to do a
particular task or work.
• There are five hardware interrupts called,


• On receipt of an interrupt, the microprocessor acknowledges the interrupt by the active low
INTA (Interrupt Acknowledge) signal.

Reset In (input, active low)

• This signal is used to reset the microprocessor.

• The program counter inside the microprocessor is set to zero.

• The buses are tri-stated.

Reset Out (Output)

• It indicates CPU is being reset.

• Used to reset all the connected devices when the microprocessor is reset

7. Direct Memory Access (DMA):

Tri state devices:

• 3 output states are high & low states and additionally a high impedance state.
• When enable E is high the gate is enabled and the output Q can be 1 or 0 (if A is 0, Q is 1,
otherwise Q is 0). However, when E is low the gate is disabled and the output Q enters into
a high impedance state.

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• For both high and low states, the output Q draws a current from the input of the OR gate.

• When E is low, Q enters a high impedance state; high impedance means it is electrically
isolated from the OR gate's input, though it is physically connected. Therefore, it does not
draw any current from the OR gate's input.

• When 2 or more devices are connected to a common bus, to prevent the devices from
interfering with each other, the tristate gates are used to disconnect all devices except the
one that is communicating at a given instant.

• The CPU controls the data transfer operation between memory and I/O device. Direct
Memory Access operation is used for large volume data transfer between memory and an
I/O device directly.

• The CPU is disabled by tri-stating its buses and the transfer is effected directly by external
control circuits.
• HOLD signal is generated by the DMA controller circuit. On receipt of this signal, the
microprocessor acknowledges the request by sending out HLDA signal and leaves out the
control of the buses. After the HLDA signal the DMA controller starts the direct transfer of
data.

READY (input)

• Memory and I/O devices will have slower response compared to microprocessors.

• Before completing the present job such a slow peripheral may not be able to handle further
data or control signal from CPU.

• The processor sets the READY signal after completing the present job to access the data.

• The microprocessor enters into WAIT state while the READY pin is disabled.

8. Single Bit Serial I/O ports:

• SID (input) - Serial input data line

• SOD (output) - Serial output data line

• These signals are used for serial communication.

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Addressing Modes of 8085
To perform any operation, we have to give the corresponding instructions to the
microprocessor. In each instruction, programmer has to specify 3 things:
• Operation to be performed.
• Address of source of data.
• Address of destination of result.

The method by which the address of source of data or the address of destination of result is
given in the instruction is called Addressing Modes. The term addressing mode refers to the way in
which the operand of the instruction is specified.

Types of Addressing Mode

Intel 8085 uses the following addressing modes:

1. Direct Addressing Mode
2. Register Addressing Mode
3. Register Indirect Addressing Mode
4. Immediate Addressing Mode
5. Implicit Addressing Mode

1. Direct Addressing Mode:

In this mode, the address of the operand is given in the instruction itself.

• LDA is the operation.

• 2500 H is the address of source.
• Accumulator is the destination.

2. Register Addressing Mode:

In this mode, both the operands are in general purpose registers.

• MOV is the operation.

• B is the source of data.
• A is the destination

3. Register Indirect Addressing Mode:

In this mode, the address of operand is specified by a register pair.

• MOV is the operation.

• M is the memory location specified by H-L register pair.
• A is the destination.
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4. Immediate Addressing Mode:

In this mode, the operand is specified within the instruction itself.

• MVI is the operation.

• 05 H is the immediate data (source).
• A is the destination.

5. Implicit Addressing Mode:

If address of source of data as well as address of destination of result is fixed, then there is
no need to give any operand along with the instruction.

• CMA is the operation.

• A is the source.
• A is the destination.

INSTRUCTION SET OF 8085:

An instruction is a binary pattern designed inside a microprocessor to perform a specific
function. The entire group of instructions, called the instruction set, determines what functions the
microprocessor can perform. These instructions can be classified into the following five functional
categories: data transfer (copy) operations, arithmetic operations, logical operations, branching
operations, and machine-control operations.
1 Data Transfer Croup
The data transfer instructions move data between registers or between memory and
registers.
MOV Move
MVI Move Immediate
LDA Load Accumulator Directly from Memory
STA Store Accumulator Directly in Memory
LHLD Load H & L Registers Directly from Memory
SHLD Store H & L Registers Directly in Memory

An 'X' in the name of a data transfer instruction implies that it deals with a register pair (16-
bits);
LXI Load Register Pair with Immediate data
LDAX Load Accumulator from Address in Register Pair
STAX Store Accumulator in Address in Register Pair
XCHG Exchange H & L with D & E
XTHL Exchange Top of Stack with H & L
2 Arithmetic Group
The arithmetic instructions add, subtract, increment, or decrement data in registers or memory.
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ADD Add to Accumulator
ADI Add Immediate Data to Accumulator
ADC Add to Accumulator Using Carry Flag
ACI Add immediate data to Accumulator Using Carry
SUB Subtract from Accumulator
SUI Subtract Immediate Data from Accumulator
SBB Subtract from Accumulator Using Borrow (Carry) Flag
SBI Subtract Immediate from Accumulator Using Borrow (Carry) Flag
INR Increment Specified Byte by One
DCR Decrement Specified Byte by One
INX Increment Register Pair by One
DCX Decrement Register Pair by One
DAD Double Register Add; Add Content of Register Pair to H & L
Register Pair

3 Logical Group
This group performs logical (Boolean) operations on data in registers and memory and on
condition flags. The logical AND, OR, and Exclusive OR instructions enable you to set specific
bits in the accumulator ON or OFF.
ANA Logical AND with Accumulator
ANI Logical AND with Accumulator Using Immediate Data
ORA Logical OR with Accumulator
OR Logical OR with Accumulator Using Immediate Data
XRA Exclusive Logical OR with Accumulator
XRI Exclusive OR Using Immediate Data

The Compare instructions compare the content of an 8-bit value with the contents of the
accumulator;

CMP Compare
CPI Compare Using Immediate Data

The rotate instructions shift the contents of the accumulator one bit position to the left or right:

RLC Rotate Accumulator Left

RRC Rotate Accumulator Right

RAL Rotate Left through Carry

RAR Rotate Right through Carry

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Complement and carry flag instructions:

CMA Complement Accumulator

CMC Complement Carry Flag
STC Set Carry Flag
4 Branch Group
The branching instructions alter normal sequential program flow, either unconditionally or
conditionally. The unconditional branching instructions are as follows:

JMP Jump

CALL Call

RET Return

Conditional branching instructions examine the status of one of four condition flags to
determine whether the specified branch is to be executed. The conditions that may be specified are
as follows:
NZ Not Zero (Z = 0)
Z Zero (Z = 1)
NC No Carry (C = 0)
C Carry (C = 1)
PO Parity Odd (P = 0)
PE Parity Even (P = 1)
P Plus (S = 0)
M Minus (S = 1)

Thus, the conditional branching instructions are specified as follows:

Jumps Calls Returns
INC CNC RNC (No Carry)
JNZ CNZ RNZ (Not Zero)
JM CM RM (Minus)
JPO CPO RPO (Parity Odd)
JM CM RM (Minus)
JPE CPE RPE (Parity Even)
JPO CPO RPO (Parity Odd)
Two other instructions can affect a branch by replacing the contents or the program
counter:
PCHL Move H & L to Program Counter
RST Special Restart Instruction Used with Interrupts

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5 Stack Instructions
The following instructions affect the Stack and/or Stack Pointer
PUSH Push Two bytes of Data onto the Stack
POP Pop Two Bytes of Data off the Stack
XTHL Exchange Top of Stack with H & L
SPHL Move content of H & L to Stack Pointer
6 I/0 instructions
IN Initiate Input Operation
OUT Initiate Output Operation
7 Machine Control instructions
EI Enable Interrupt System
DI Disable Interrupt System
HLT Halt
NOP No Operation

FEATURES OF 8086 MICROPROCESSOR:

1. The 8086 is the first 16-bit processor by the Intel.
2. It is available in 40 pin DIP Integrated Circuit and operates at 5 volts dc supply.
3. It is implemented in N- channel, silicon gate technology i.e., HMOS (High density MOS) and its
electronic circuitry consist of 29000 transistors.
4. It is available in 3-versions: the 8086, 8086-2 and 8086-1. These can operate at clock frequencies
5 MHz for 8086, 8 MHz for 8086-2 and 10 MHz for 8086-1.
5. The 8086 has 20 address lines. Using 20 address lines it can directly address up to 220 = 1 Mega
Bytes (1MB) of memory.
6. It supports 16- bit ALU, a set of 16- bit registers and provides segmented memory addressing
capability.
7. It is powerful interrupt structure, a rich instruction set.
8. It has fetched instruction queue for overlapped fetching and execution.
9. The 8086 provides fourteen 16-bit registers.
10. The Intel 8086 supports multi programming.
11. The 8086 has two modes of operation: the minimum mode and maximum mode.

MEMORY SEGMENTATION:

Memory is a physically, a linear sequence of addresses, each address holding a single byte. The
lowest memory address is 0, the next address is address 1, and so on until the highest memory address
is reached. The highest memory address for the 8086 microprocessor is address FFFFFH.

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In 8086, available memory space is divided in to “chunks” called segments; such a memory is
known as segment memory. The 8086 is able to address in bytes of physical memory. The complete 1
MB of memory can be divided in to 16 segments, each of 64 Kbytes size. The addresses of the
segment may be assigned as 0000H to FFFFH. The above case segments are non-overlapped
segments. In some cases, segments may be overlapping. To address a specific memory location within
a segment, an offset address is needed.

Fig: One way four 64 Kbytes segments might be positioned within 1MB address space of an
8086(Non-Overlapping)

Fig: Overlapping Segmentation

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The main advantages of the segmented memory scheme are as follows.

1. Allows the memory capacity to be 1 Mbytes although the actual addresses to be handled
are of 16 bit size.
2. Allows the placing of code, data and stack portions of the same program in different parts
(segment) of memory, for data and code protection.
3. Permits a program and/or its data to be put into different areas of memory each time
program is executed, i.e., provision for relocation may be done.
4. It allows program to be loaded and read anywhere in the memory.
5. It enables multiprogramming.
6. It simplifies handling of growing data structure.
REGISTER ORGANIZATION 8086:

The 8086 has a powerful set of registers known as general purpose and special purpose
registers. All the registers of 8086 are 16-bit registers. The 8086 contains fourteen 16-bit registers.
They are grouped in to the following categories.

i) General Purpose Registers

ii) Pointers
iii) Index Registers
iv) Segment Registers
v) Flag Register

Fig: Schematic Diagram of Intel 8086 Registers

General Purpose Registers: There are four 16-bit general purpose registers: AX, BX, CX and
DX. Each of these general purpose registers can be used either as 16-bit register or as two 8-bit
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registers. Usually letters L and H specify the lower and bytes of a particular register. The letter X is
used to specify the complete 16-bit register. These registers are used to hold arithmetic and logical
operand and results.

16-Bit Registers 8-Bit High-order Registers 8-Bit Low-order Registers

AX AH AL

BX BH BL

CX CH CL

DX DH DL

* The register AX serves as an Accumulator, with the lower 8-bits of AX designated as AL and
higher 8-bits as AH. The AL can be used as an 8-bit accumulator for 8-bit operations.

The BX, CX and DX are primarily meant to hold data, but also serve as special purpose
registers.

* The register BX is used as a base register for offset storage to form physical memory address.
* The register CX is used as a default counter in case of certain string and loop instructions.
* The DX is used to hold I/O addresses during certain I/O instructions.
- If the result of a multiplication is more than 16 bit the lower order bits are stored in AX,
the higher order 16 bits are stored in DX register.
- If divided is of 32 bit, high order 16 bits are contained in DX register. After division, the
16 bit quotient is placed is placed in AX and the remainder in DX.
Pointers: The pointers contain offset within the particular segments. The pointers IP, BP and SP
usually contain offsets within the code (IP) and stack (BP & SP) segments.

Index Registers: The index registers are used as general purpose registers as well as for offset
storage. The register SI is used to store the offset of source data in data segment. The register DI is
used to store the offset of destination in extra segment.

The index registers particularly used for string manipulations. In certain string
instructions, SI is used to indicate source index and DI to destination index. In such cases, the
contents of SI are added to the contents of DS to get the actual source address of the data. The
contents of DI are added to the contents of ES to get the actual destination address of the data.

Segment Registers: The 8086 addresses a segmented memory. The complete 1 MB is divided into
16 logical segments. Each segment thus contains 64 Kbytes of memory. At a particular time, the
8086 works with only four segments within 1MB of memory. In 1MB memory there may be
several sets of four segments. All these segment are logical segments i.e., they may or may not be
physically separated. The four segments are, i.e., Code, Stack, Data and Extra segments.

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The code segment contains instruction codes of the program. The stack segment is that
segment of memory which is used to store stack data. The data segment contains program’s
defined data, variables and constants. The extra segment is another data segment, contains the
destination of source data of certain string instruction.

There are four segment registers. They are code segment register (CS), data segment
register (DS), stack segment register (SS) and extra segment register (ES). These segment registers
contain the high order 16 bits of the starting addresses of four memory segments.

* The code segment register is used for addressing a memory location in the code segment of the
memory, where the executable program is stored.

* The data segment register points to the data segment of the memory, where the data is resided.

* The ES register addresses extra segment of memory (which is another data segment of
memory), which contains destination of some data of certain string instructions.

* The SS register is used for addressing stack segment of memory, which is used to store stack
data.

Flag Register:

A flag is a flip-flop which indicates some condition produced by the execution of an

instruction. The 8086 has 16-bit flag registers. It is also called status register or program status
word (PSW). It has nine flags. Seven bit positions of status register are undefined. Out of nine
flags six are condition flags. They are set or reset by the processor depending on the result of same
architecture and logic operations. The six conditional flags are CF, OF, PF, AF, ZF and SF. The
remaining three flags are control flags. These flags are set or reset by the programmer as required
by certain instructions in a program. These control flags are TF, DF, IF.

The format of 8086 flag register is shown in the figure below. The lower byte of this flag
register is compatible with 8085 flag register.

Fig: Flag Register of Intel 8086

Conditional Flags:

Carry Flag (CF): This flag is set whenever a carry /borrow occurs during arithmetic operations
such as addition or subtraction. Otherwise it is reset.

Parity Flag (PF): This flag is set to 1, if the lower byte of the result contains even number of 1`s.
If the lower byte of the result contains odd number of 1`s, the parity flag is set to zero.
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Auxiliary Carry Flag (AF): This is set, if there is a carry from the lowest nibble, i.e., bit three
during addition or borrow for the lowest nibble, i.e., bit three, during subtraction.

Sign Flag (SF): This flag is set, when the result of any computation is negative. It is reset, if the
MSB of the result is zero, it is set to zero.

Zero Flag (ZF): This flag is set, if the result of an arithmetic or logic operation is zero. In the case
of nonzero result, this flag is set zero.

Over Flow Flag (OF): This flag is set, if an over flow occurs, i.e., if the result of a signed
operation is large enough to be accumulated in a destination register. The overflow flag has no
significance in unsigned arithmetic operation.

Control Flags:

Trap Flag (TF): It is used for single step control. If this flag is set, the processor enters the single
step execution mode. It allows user to execute one instruction of a program at a time for
debugging.

Interrupt Flag (IF): It is an interrupt enable/disable flag. If this flag is set, the CPU recognizes the
maskable interrupts, otherwise, they are ignored.

Direction Flag (DF): This is used by string manipulation instructions. If this flag bit is `0`, the
string is processed beginning from the lowest address to the highest address i.e., auto incrementing
mode. Otherwise, the string is processed from the highest address towards lowest address i.e., auto
decrementing mode.

Pin Diagram of 8086 microprocessor

The 8086 microprocessor is a 16-bit CPU available in three clock rates, i.e., 5.8 and 10MHZ. It is
available in 40 pin DIP. The 8086 operates in single processor or multiprocessor configuration to achieve
high performance.

The single processor mode is called “MINIMUM mode”, there is only one bus master, which is a
single processor with few peripherals such as latches, transceivers, and memory and I/O devices.

The multiprocessor mode is called “MAXIMUM mode”, there may be more than one
microprocessor or coprocessor in the system. Any one of them can gain control over the system and acts as
bus master.

The 8086 signals can be categorized in three groups.

• Signals having common functions in minimum as well as maximum mode.

• Signals having special functions for minimum mode.
• Signals having special functions for maximum mode.
Signals with Common Functions in Both Modes:
AD0-AD15 (Address/Data Bus): These are the time multiplexed memory I/O address and data lines.
Address remains on the line during T1 clock cycle of bus cycle, while the data is available on the data bus
during T2, T3, Tw and T4. These are bidirectional lines.

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A16/S3-A19/S6 (Address/Status):(output): These are the time multiplexed address and status lines. During
T1 these are the most significant address lines for memory operations. During I/O operations, these lines are
low.

During memory or I/O operations, status information is available on those lines for T2, T3, Tw and
T4. The status line S6 is always low. The status line S5 indicates the status of interrupt enable flag bit and it
is updated at the beginning of each clock cycle. The S4 and S3 combinedly indicate which segment register
is presently being used for memory access.

(Bus High Enable/Status)( BHE /S7) (Output): It is a time multiplexed line. The BHE remains low
during T1, and it is used to indicate the transfer data over the higher order (D15-D8) data bus. During T2 to T4,
the status signal is transmitted on this line. It remains active high.

The BHE in conjunction with A0 determines whether a byte or word will be transferred from/to
memory locations.

RD (Read)(Output): It is a read signal issued by the processor. It is an active low signal. It indicates that
the processor performing read operation with memory or I/O.

READY (Input): It is an active high signal. It is an acknowledgement received from the addressed memory
or I/O device. When high, it indicates that the peripheral device is ready to transfer data.

RESET (Input): This input causes the processor to terminate the current activity and start execution from
FFFF0H. The signal is active high and must be active for at least four clock cycles.

CLK-Clock Input: The clock input provides the basic timing for processor operation and bus control
activity. It is an asymmetric square wave with 33% duty cycle. The range of frequency for different 8086
versions is from 5MHZ to 10MHZ.

TEST (Input): The TEST input is tested by the WAIT instruction. The 8086 will enter a wait state after
execution of the WAIT instruction and it enters into execution only TEST is made low by an external
hardware. This is used to synchronize an external activity to the processor execution.

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This signal is used to test the status of math coprocessor 8087. The BUSY pin of 8087 is connected
to the TEST pin of 8086. Sometimes the 8086 needs the result of some computation that 8087 is doing,
before it can go to the next instruction of the program. If TEST is high, ‘WAIT’ instruction causes 8086 to
wait in an idle state. When 8087 completes computation, it makes BUSY signal low, there by making
TEST low. When TEST becomes low, the 8086 goes to the next instruction and continues execution of the
program.

INTR (Interrupt Request) (Input): This is a level triggered input. This is sampled during the last clock
cycle of each instruction to determine the availability of the request. If any interrupt request is pending, the
processor enters the interrupt acknowledge cycle. This can be internally masked by resetting the interrupt
enable flag.

NMI-Non Maskable Interrupt (Input): This is an edge triggered input which causes a Type 2 interrupt.
The NMI is not maskable internally by software. A transition from low to high initiates the interrupt
response at the end of the current instruction.

VCC: +5V power supply for the operation of the internal circuit.

GND: Ground for the internal circuit.

MN / MX (Input): The logic level at these pin decides whether the processor is to operate in either
minimum or maximum mode. When high, the processor operates in the minimum mode. When low, it
operates in the maximum mode.

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Minimum Mode Signals:
INTA (Interrupt Acknowledge) (Output): This signal is used as a read strobe for interrupt acknowledge
cycles. In other words, when it goes low, it means that the processor has accepted the interrupt. It is active
low during T2, T3 and Tw of each interrupt acknowledge cycle.

ALE (Address Latch Enable)(Output):This output signal indicates the availability of the valid address on
the address/data lines, and is connected to latch enable input of location latches. It is used to demultiplex the
address and data lines.

DEN (Data Enable)(Output): This signal indicates the availability of valid data over the address/data
lines. It is used to enable the transreceivers (bidirectional buffers) to separate the data from the multiplexed
address/data signals. It is active from the middle of T2 until the middle of T4.

DT / R (Data Transmit/Receive)(Output): This output is used to decide the direction of data flow through
the transreceivers (bidirectional buffers). When the processor sends out data, this signal is high and when
the processor is receiving data, this signal is low. Logically it is equivalent to S1 in maximum mode.

M / IO - (Memory/IO) (Output): It is logically equivalent to S2 in maximum mode. It is issued by

processor to distinguish a memory access from an I/O access. When this signal is high memory is accessed
and when it is low, an I/O device is accessed.

WR (Write) (Output): When this signal is low, the processor performs memory write or I/O write
operation depending on the status of M / IO signal.

HOLD (Input): It is an active high signal. It is an input signal to the processor from other bus masters to
request the control of the bus. It is usually used by the DMA controller to get the control of the bus.

HLDA (Hold Acknowledge) (Output):It is an active high signal. On receiving HOLD signal, the

Processor issues a HOLD acknowledge signal through this pin, to the master requesting the control of the
bus.

Maximum Mode Signals:

QS1, QS0 (Queue Status)(Output): These two signals reflect the status of instruction queue. These signals
provide status to allow external tracking of the instruction queue.

S2 ,S1 ,S0 (Status lines)(Output): These status signals are used by 8288 bus controller to generate all
memory and I/O access control signals. These become active during T 4 of the previous cycle and remain
active during T1 and T2 of the current bus cycle. These are encoded as follows:

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LOCK (Output): The LOCK, a prefix instruction activates LOCK signal. It is an active low signal. It
remains active until the completion of next instruction. When it goes low all interrupts are masked and
HOLD request is not granted. Consequently other devices do not get control over the system bus while
LOCK is low.

RQ / GT0 , RQ / GT1 (Request/Grant)(Bidirectional): These pins are used by other local bus masters, in
maximum mode to force the processor to release the local bus at the end of processor’s current bus cycle.
Each of these pins is bidirectional with RQ / GT0 having higher priority than RQ / GT1 . After receiving
hold request, the processor sends acknowledge signal through these lines.

ARCHITECTURE OF 8086 MICROPROCESSOR:

The 8086 has pipelined architecture. In the pipelined architecture the processor
will have number of functional units and the executions of functional units are overlapped.
The complete architecture of 8086 can be divided in to two parts

a) Bus interface unit (BIU) and

b) Execution unit (EU)

Bus Interface Unit: The bus interface unit contains

i. The circuit for physical address calculation (Adder)

ii. Predecoding instruction byte queue
iii. Segment registers
iv. Instruction pointer

The main functions of BIU are

a) The BIU handles the all interface with the external bus and generates external memory and I/O
addresses.
b) The BIU reads data from the memory and ports.
c) It fetches instruction codes from the memory and keeps them in to a 6- byte instruction queue.
d) It fills up the queue whenever the bus is idle and 2 bytes of the queue are vacant.
e) In the case of jump and call instruction, the BIU dumps the queue and then starts reloading it
from a new address.

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Adder:
The 8086 addresses a segmented memory. The complete physical address which is 20 bit
long is generated using segment and offset registers , each 16- bit long. For generating a physical
address from content of these two registers , the content of a segment register also called a
segment address is shifted left bit wise four times and to the result, content of an offset register
also called as offset address is added , to produce a 20 bit physical address .
For example, if the segment address is 1005H and offset is 5555H, then the physical address is
calculated as follows.

Segment address-------1005H

Offset address--------- 5555H

Segment address1005H0001000000000101

Shifted by 4- bit position -0001 0000 0000 0101 0000

Offset address 0101 0101 0101 0101

_____________________________

Physical address--- 0001 0101 0101 1010 0101

1 5 5 A 5

The segment register indicates the base address of a particular segment, while the offset
indicates the distance of the required memory location in the segment from the base address. Since
the offset is 16 bit number each segment can have a max of 64k locations. The segment address is
taken from an appropriate segment register depending upon whether code, data or stack are to be
accessed, while the offset may be the contents of IP,BX,SI,DI,SP or an immediate 16 bit value.

How far a memory location is within a memory segment from the starting address is called offset
or effective address.

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Instruction Queue: In case of 8085, once the opcode is fetched and decoded, the external bus
remains free for some time, while the processor internally executes the instruction. The time slot is
utilized in 8086 to achieve the overlapped fetch and execution cycles. While the fetched instruction
is executed internally, the externally bus is used to fetch the machine code of the next instruction
and arrange it in a queue called as predecoded instruction byte queue. It is a 6 bytes long, first in
first out structure. The instructions from the queue are taken for decoding sequentially. Once a byte
is decoded, the queue is rearranged by pushing it out and the queue status is checked for the
possibility of the next opcode fetch cycle.

Segment Registers: The 8086 addresses a segmented memory. The complete 1 MB is divided
into 16 logical segments. Each segment thus contains 64 Kbytes of memory. At a particular time,
the 8086 works with only four segments within 1MB of memory. In 1MB memory there may be
several sets of four segments. All these segment are logical segments i.e., they may or may not be
physically separated. The four segments are , i.e., Code, Stack, Data and Extra segments.

The code segment contains instruction codes of the program. The stack segment is that segment of
memory which is used to store stack data. The data segment contains program’s defined data,
variables and constants. The extra segment is another data segment, contains the destination of
source data of certain string instruction.

There are four segment registers. They are code segment register (CS), data segment
register (DS), stack segment register (SS) and extra segment register (ES). These segment registers
contain the high order 16 bits of the starting addresses of four memory segments.

* The code segment register is used for addressing a memory location in the code segment of the
memory, where the executable program is stored.

* The data segment register points to the data segment of the memory, where the data is resided.

* The ES register addresses extra segment of memory (which is another data segment of
memory), which contains destination of some data of certain string instructions.

* The SS register is used for addressing stack segment of memory, which is used to store stack
data.

Instruction Pointer: It acts a program counter. It holds 16-bit offset pointing to the next
instruction code with in the current 64KB code segment. It points to the next instruction to be
executed within the currently executing code segment. Its content is automatically incremented as
the execution of a program proceeds.

Execution Unit: The execution unit receives prefetched instructions from the queue, decodes them
and then executes them. The queue acts as first in first out for EU. If the queue is empty, the EU
waits till the queue gets at least one byte. Such situation arises after the execution of a jump
instruction.

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Fig: Architecture of 8086

The execution unit contains the register set of 8086 except segment registers and IP. The
EU has 8 GPR’s labeled as AH, AL, BH, BL, CH, CL, DH, DL and used individually for
temporary storage of 8-bit data. The advantage of using internal registers for temporary storage is
that, since the data is already in the EU, it can be accessed in external memory.

It has a 16 bit ALU, able to perform arithmetic & logic operations. The 16 bit flag register
reflects the result of execution by the ALU. The decoding unit decodes the opcode bytes issued
from the instruction byte queue. The timing and control unit derives the necessary control signals
to execute the instruction opcode received from the queue. The EU may pass the result to the BIU
for storing them in memory.

PHYSICAL ADDRESS CALCULATION:

The complete physical address which is 20 bit long is generated using segment and offset
registers , each 16- bit long. For generating a physical address from content of these two registers ,
the content of a segment register also called a segment address is shifted left bit wise four times
and to the result, content of an offset register also called as offset address is added , to produce a
20 bit physical address .

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Fig: Addition of IP to CS to produce the Fig: Addition of SP to SS to produce the

Physical address of the code byte physical address of the top of the stack
a) Diagram b) Computation a) Diagram b) Computation

Fig: Addition of data segment register and effective address to produce the physical
address of the data byte a) diagram b) computation

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General Bus Operation of 8086:

The 8086 has a combined address and data bus commonly referred as a time multiplexed
address and data bus. The main reason behind multiplexing address and data over the same pins is
the maximum utilization of processor pins and it facilitates the use of 40 pin standard DIP
package. The bus can be demultiplexed using a few latches and transreceivers, whenever required.

Basically, all the processor bus cycles consist of at least four clock cycles. These are
referred to as T1, T2, T3, T4. The address is transmitted by the processor during T1, It is present
on the bus only for one cycle. The negative edge of this ALE pulse is used to separate the address
and the data or status information.

In maximum mode, the status lines S0, S1 and S2 are used to indicate the type of
operation. Status bits S3 to S7 are multiplexed with higher order address bits and the BHE signal.
Address is valid during T1 while status bits S3 to S7 are valid during T2 through T4.

General Bus Operation (Read/Write) Cycles of 8086

Maximum Mode
i. In the maximum mode, the 8086 is operated by strapping the MN/MX pin to ground.
ii. In this mode, the processor derives the status signal S2, S1, S0. Another chip called bus
controller derives the control signal using this status information.
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iii. In the maximum mode, there may be more than one microprocessor in the system
configuration.
Minimum Mode
i. In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by
strapping its MN/MX pin to logic 1.
ii. In this mode, all the control signals are given out by the microprocessor chip itself.

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UNIT-II
ADDRESSING MODES, INSTRUCTION SET AND PROGRAMMING
ADDRESSING MODES OF 8086:

Each instruction performs an operation on the specified data (operand). Hence, an operand
must be specified for an instruction to be executed. The operand may reside in the accumulator, in
a general-purpose register or in a memory location. The way by which an operand is specified for
an instruction is called “Addressing Mode’.

According to the flow of instruction execution, the instruction may be categorized as

I) Sequential control flow instructions and

II) Control transfer instructions

 Sequential control flow instructions which after execution, control transfer to the next
instruction appearing immediately after it in the program.

Ex.:- Arithmetic, Logic, Data Transfer and Processor Control Instructions

 The control transfer instructions, transfer control to the some predefined address or the address
somehow specified in the instruction, after their execution.

Ex.:- INT, CALL, RET and JUMP instructions.

There are total 8 addressing modes for the sequential control transfer instructions. Out of
these, two addressing modes are provided for instructions which operate on the contents of register
or immediate operands. The remaining six addressing modes are for specifying an operand stored
in the memory.

Addressing Modes for Register or Immediate Operand Instructions:

1.Register Addressing Mode: In register addressing mode, data is stored in the register. All the
registers except IP may be used in this mode.

Ex: MOV BX,AX : move the contents of AX reg to BX reg

ADD CX,DX : add the contents of DX to the contents of CX

ADD AL,CH : add the content of CH to the content of CL.

2. Immediate Addressing: In immediate addressing mode, the operand is contained in the

instruction itself. The operand forms a part of the instruction.

Ex: MOV AL,58H : move 58H to AL register

ADD AX, 0359H : Add 0395H to the content of AX reg

MOV AX,0005H : Here 0005H is the immediate data.

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Addressing modes for an operand stored in memory:

The memory address of an operand consists of two 16 bit components: the starting address
of a memory address and an offset. The offset is determined by adding any combination of the
following three offset address elements: displacement, base and index.

Displacement: It is an 8 bit or 16 bit operand

Base: It is the content of base reg, BX or BP

Index: It is the content of index reg, SI or DI

3. Direct Addressing Mode: In this mode of addressing, an effective address or offset is given in
the instruction itself.

Ex. MOV AX, [5000H]; here data resides in a memory location in the data segment, where
offset is 5000H. The physical addresses is 10H* DS+5000H

MOV AL,[0300H]; move the contents of offset 0300H to AL.

4. Register Indirect Addressing Mode: In this mode of addressing, the offset address of data is in
either BX or SI or DI registers. The default segment is either DS or ES.

Ex. MOV AX,[BX] : here data is in memory location in DS, where offset address is in
BX. The physical address is 10H * DS+[BX]

ADD CX,[BX]

5. Indexed Addressing Mode: In this addressing mode, offset the operand is stored in one of the
indexed registers. DS and ES are the default segments for index registers SI and DI respectively.

Ex. MOV AX, [SI] :here data is available at an offset address stored in the SI in DS .
The physical address is 10H*DS+[SI]

6. Register Relative Addressing Mode: In this , the data is available at an effective address
formed by adding an 8 bit or 16 bit displacement with the content of any one of the registers
BX,BP,SI and DI

Ex. MOV AX,[BX+10H] The physical address is 10H*DS+10H[BX]

7. Based Index Addressing Mode: In this, the effective address of the data is formed by adding
content of a base register (BX or BP) to the content of an index register (SI or DI).

Offset = [BX or BP+ SI or DI]

Ex. MOV AX,[BX+SI]; Here BX is the base register and SI is the index register. The
physical address is 10H*DS+[BX]+[SI]

8. Relative Based Indexed Addressing Mode: In this addressing mode, the effective address is
formed by adding 8 or 16 bit displacement with in the sum of contents of any one of the register
(BX or BP) and any one of the index register (SI or DI)

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Offset = [BX or BP+ SI or DI] + DISPLACEMENT

Ex. MOV AX,[BX+SI+1523H]; Here 1523H is immediate displacement. BX is base

register and SI is an index register. The physical address is 10H*DS+[BX]+[SI]+1523

INSTRUCTION SET OF 8086:

An instruction is a basic command given to a microprocessor to perform a specific
operation on the given data. An instruction has two groups of field is an opcode which defines the
operation to be performed by the instruction. The other field called operand specifies data on which
the computer has to perform the specified operation. The collection of instructions that a
microprocessor is designed to execute, is known as instruction set of that microprocessor.

The 8086 instruction can be categorized into the following types

1. Data Transfer Instructions

2. Arithmetic and Logic Instructions
3. Branch Instructions
4. String Instructions
5. Loop Instructions
6. Flag Manipulation Instructions
7. Shift and Rotate Instructions
8. Machine Control Instructions (or) Processor Control Instructions

Data Transfer Instructions:

This type of instructions is used to transfer data from source operand to destination
operand. All the store, move, load, exchange, input and output instructions belong to this category.
The various types of data transfer instructions are described below.

MOV (move): The MOV instruction copies a word or byte of data from a specified source to a
specified destination. The source can be a reg, a memory location, or an immediate number. The
destination can be a register or a memory location. But both can’t be memory locations. MOV
instructions do not affect any flags. The transfer of immediate data to a segment register is not
permitted.

Eg. MOV AX,5000H

MOV BX,AX

MOV AX,[2000H]

MOV DS,AX

PUSH (push to stack): This instruction pushes the content of the specified registers/ memory
location on the stack. The stack pointer is decremented by 2, after each execution of the
instruction. No flags are affected by the instruction.

E.g. PUSH BX

PUSH DS
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PUSH [5000H]

POP (pop from stack): This instruction when executed, loads the specified register/memory
location with the content from stack pointed by the stack pointer. The stack pointer is automatically
incremented by 2 after this instruction execution. No flags are affected by this instruction.

E.g.:- POP BX

POP DS

POP [5000H]

XCHG (Exchange): This instruction exchanges the content of the specified source and destination
operands, which may be registers or one of them, may be memory locations. However, exchange
of data contents of the memory locations is not permitted. No flags are affected.

E.g.:- XCHG BX

XCHG [500H],AX

XLAT (Translate): It is used for finding out the codes in case of code conversion problems, using
look up table technique. It is used to translate a byte from code to another code.

Eg. :- Conversion of ASCII code to EBCDIC

MOV AL,Code

MOV BX,OFFSET EBCDIC_TABLE

XLAT

It replaces a byte of in AL reg with a byte pointed by BX in a lookup table in memory. Before the
XLAT instruction can be executed, the lookup table containing values for the new code must be
put in the memory and the offset of the starting address of the lookup table must be loaded in BX.

LEA (load effective address): This instruction loads the offset of an operand in the specified
registers. No flags affected.

E.g.:- LEA BP,STACK_TOP

LEA CX,[BX+DI]

LDS (Load pointer to DS): This instruction copies a word from two memory locations into the
register specified in the instruction. It then copies a word next two memory locations into the DS
register. No flags affected.

E.g.:- LDS BX,[5000]

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LES (Load pointer to ES): This instruction copies the word from first two memory locations
copied into the specified register and it then copies a word from next two memory locations is
copied into ES register .No flags affected.

E.g.:- LES BX,[789A]

LES DI,[BX]

IN (input the port) (IN accumulator): The IN instruction will copy data from a port to the AL or
AX register. It is used for reading an input port.

E.g.:- IN AL,0300H; here 0300 is address of 8 bit port

IN AX,34H; here 34 is the address of 16 bit

IN AX; here 16 bit port address is in DX reg.

OUT (output to the port): This instruction is used for writing to an output port. It copies a byte
from AL or a word from AX to the specified port. The address of output port specified in
instruction directly or implicitly in DX. No flags affected.

E.g.:- OUT 0300H,AL

OUT AX

LAHF (load AH from lower byte of flag): This instruction loads the AH register with the lower
byte of the flag reg. It is used to observe the status of all condition code flags except overflow flag.

SAHF(store AH to lower byte of flag register): This instruction sets or resets the condition code
flags (except overflow) in the lower byte of flag register depending upon the corresponding bit
positions in AH. If a bit in AH is 1, the flag corresponding to the bit position is set, else it is reset.

PUSHF (push flags to stack): It pushes the flag register on to the stack; first the upper byte and
then the lower byte will be pushed on to the stack. The SP is decremented by 2, after each push
operation.

POPF (pop flags from stack): It loads the flag register completely (both bytes) from the word
contents of the word location currently addresses by SP. The SP is incremented by 2, for each pop
operation.

Arithmetic Instructions:
These instructions perform the arithmetic operations like addition, subtraction and division
along with respective ASCII and decimal adjust instructions. The increment and decrement
operations also belong to this type of instructions.
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Addition Instructions:

ADD (add): This instruction adds a number from a source to a number from a destination and put
the result in the specified destination. Source may be an immediate data or register or memory
location. The destination may be a register or memory location. The source and destination can’t
be memory operands. All the condition code flags are affected, depending upon the result.

E.g. ADD AX,0100H Immediate

ADD AX,BX Register

ADD DX,[SI] Register Indirect

ADD AX,[5000H] Direct

ADC (add with carry): This instruction adds the source operand to the destination operand with the
status of the carry flag. All the condition code flags are affected by this instruction.

E.g. ADC 0100H Immediate

ADC AL,BL Register

ADC AX,[0300H] Direct

INC (increment): This instruction increments the content of the specified register or memory
location by 1. All the condition code flags are affected expect the CF. Immediate data can not be
the operand of this instruction.

E.g. INC AX Register

INC [5000H] Register Indirect

INC [BX] Direct

AAA (ASCII Adjust after Addition): The AAA instruction is executed after an ADD instruction
that adds two ASCII coded operands to give a byte of result in AL.

The numerical data entered into the computer from a keyboard is usually in ASCII code. The digits
0 to 9 are represented in ASCII codes by 30H to 39H. The 8086 allows to add the ASCII codes for
two decimal digits without masking off the “3” in the upper nibble of each. After the addition, the
AAA instruction is used to make sure the result is the correct unpacked BCD.

 Numbers represented as one BCD digit per byte is called unpacked BCD.

 When two BCD digits are represented by a single byte, it is called packed BCD.

Suppose, we want to add 6 and 8. The result should be 14. In ASCII Codes 6 is 36H and 8
is 38H. When 36H and 38H are added, the result is 6EH. If AAA instruction is used after ASCII
addition, the result will be 0104, which is unpacked BCD.

The AAA instruction is used to adjust the result in the AL register, after addition of two
ASCII numbers. The adjustment is done as follows. But the AH must be cleared before addition.

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i) If the 4 LSB’s of the AL register are between 0 and 9, and AF is zero, then 4 MSB`S of AL
register are cleared and 4 LSB`S are remain unaltered.

ii) If the 4 LSB`S of AL register are between A and F or AF flag is one, then 06 is added to AL
register , 01 is added to the AH register , AF flag is set to 1 and 4 MSB`S of AL are cleared.

DAA (decimal adjust AL after BCD addition): This instruction is used to convert the result of the
addition of two packed BCD numbers to a valid BCD numbers. The result has to be only in AL. If
the lower nibble in AL after an addition is greater than 9 or AF was set by the addition, then the
DAA instruction will add 06 to the lower nibble in AL. If the result in the upper nibble of AL is
now greater than 9 or if carry flag is set by the addition or correction, then DAA instruction will
add 60H to AL. The DAA affects AF, CF, PF and ZF flags.

Subtraction Instructions:

SUB (subtract): The subtract instruction subtracts the source operand from the destination operand
and the result is left in the destination operand. Source operand may be a register, memory location
or immediate data .The destination operand may be a register or memory location but cannot be an
immediate data. Both source and destination can be memory operands.

E.g. SUB AX,0140H Immediate (destination in AX)

SUB AX,BX Register

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SUB AX,[5000H] Direct

SUB [5000H],0100 Immediate

SBB (subtract with borrow): It subtracts the source operand and the borrow flag (CF) from the
destination operand.

e.g. SBB AX,BX

SBB AX,[5000H]

SBB BX,[3427H]

DEC (decrement): The decrement instruction subtracts 1 from the contents of the specified register
or memory location. All the condition code flags are affected except CF. Immediate data can not be
the operand of this instruction.

e.g. DEC CL

DEC AX

DEC BP

DEC [5000H]

NEG (negate): The negate instruction forms 2`s complement of the specified destination in the
instruction. For obtaining 2`s complement, it subtracts the content of destination from zero. The
result is stored back in the destination operand which may be a register or a memory location .It
affects all condition code flags.

e.g. NEG AL

NEG BX

CMP(compare): This instruction compares a byte or word from the specified source with a byte or
word from the specified destination .For comparison it subtracts the source operand from the
destination operand but does not store the result anywhere, but the flags are changed to indicate the
result of comparison .If both operands are equal zero flag is set. If source operand is greater than
the destination operand carry flag is set or else carry flag is reset.

e.g. CMP AL,01H

CMP BH,CL

CMP [5000H],0100H

CMP BX,[SI]

AAS (ASCII adjust AL after subtraction): This instruction is used to adjust the result in AL register
after performing subtraction, when the operands are ASCII numbers. The adjustment is done as
follows.

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i) If the last significant (LS) hex digit of AL register is less than or equal to 9 and auxiliary carry
flag is 0, then the most significant hex digit of AL register is cleared (i.e., made 0) and LS hex digit
is unaltered.

ii) If the LS hex digit of AL register is greater than 9 or auxiliary carry (AF) flag is 1, the following
adjustments are made:

a) 6 is subtracted from LS hex digit of AL register

b) The 4 MSB`s of AL register are cleared.

c) Contents of AH are decremented by 1

d) Carry and auxiliary carry flags are set to 1

EX: 8-6  38-36 = 02 --- 0002 (AX) ------------- case (i)

6-8  36-38 = FE --- FF08 (AX) ------------ case (ii)

In case (ii) example, FF indicates the result is negative & 08 is result in 10’s complement

DAS (decimal adjust AL after BCD subtraction): This instruction converts the result of subtraction
of two packed BCD numbers to a valid BCD number. The subtraction has to be in AL only. If the
lower nibble in AL after a subtraction is greater than 9 or if AF is set by subtraction, then DAA
will subtract 6 from the lower nibble of AL. If the result in the upper nibbles now greater than 9 or
if CF was set, DAA will subtract 60 from AL.

Multiplication Instructions:

MUL (unsigned multiplication byte or word): This instruction is used for multiplication of two
unsigned numbers. The contents of specified register or memory location can be multiplied by the
contents of AL (if 8 bit) or AX (if 16 bit) register. The result is placed in AX (for 8 bit
multiplication) or DX:AX (for 16 bit multiplication). In case of 16 bit multiplication lower
significant word is placed in AX and higher significant is placed in DX register. It will affect CF
and OF.

e.g. MUL BH; (AX)AL* BH

MUL CX; (DX) (AX)(AX)*(CX)

IMUL (signed multiplication): This instruction is used for multiplication of two signed numbers.
This instruction multiplies a signed byte in source operand by a signed byte in AL (or) signed word
in source operand by signed word in AX. The source can be a reg or memory operand, not
immediate data. The CF and AF are affected.

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E.g. IMUL CL

IMUL CX

IMUL [SI]

AAM (ASCII adjust after multiplication): Before multiply two ASCII digits, first mask the upper 4
bits of each. This leaves unpacked BCD in each byte. The AAM instruction is used to adjust the
result in the AL register, after the multiplication of two unpacked BCD numbers.

To give result in BCD the following steps are taken: The AL register is divided by OA hex.
Quotient is stored in AH and the remainder is stored in the AL.

Division Instructions:

DIV (unsigned division): This instruction performs unsigned division. This instruction is used to
divide an unsigned word by a byte or to divide an unsigned double word by a word.

When a word is divided by a byte, the word must be in the AX register. The divisor must be a
register or memory location. After the division, AL will contain quotient and AH will contain
remainder. If the quotient is too large to fit in AL (greater than FF), type 0 (divide by zero)
interrupt is generated.

When a double word is divided by a word, the most significant word of double word must be in
DX, and the least significant word of double word in AX. After the division, AX will contain 16
bit quotient and DX will contain 16 bit remainder. If the quotient is too large to fit in AX (greater
than FFFF), type 0 (divide by zero) interrupt is generated.

E.g. DIV BL; divide word in AX by byte in BL & quotient in AL and remain in AH

DIV CX; divide double word in DX: AX by word in CX & Quotient in AX and remainder in
DX

IDIV (signed division): This instruction performs the same operation as the DIV instruction, but
with signed operands. It is used to divide a 16 bit signed number by an 8 bit number (or) to divide a
32 bit number by a 16 bit signed number. No flags will be affected by this instruction.

E.g. IDIV CL

IDIV BP

AAD (ASCII Adjustment before Division): This instruction adjusts unpacked BCD dividend in AX
register before the division operation is performed. The AAD instruction converts two unpacked
BCD digits in AH and AL to the equivalent binary number in AL. This adjustment is made before
dividing the two unpacked BCD digits in AX by an unpacked BCD byte. After division, AL will
contain the unpacked BCD quotient and AH will contain the unpacked BCD remainder.
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The adjustments steps are as follows:

a) AH is multiplied by 0AH and added to AL

b) AH is set to zero.

E.g. AX=0609, CH=09

AADAX=0043H --------------- 67 Decimal

DIV CH  Quotient AL=07, Remainder AH=04

CBW (convert signed byte to signed word): This instruction converts a signed byte to a signed
word. This instruction copies the sign of a byte in AL to all the bits in AH. Then AH is said to be
the sign extension of AL. The CBW operation must be done before a signed byte in AL can be
divided by another signed byte with the IDIV instruction. It affects no flags.

e.g. AX=00000000 10011011= -155 decimal

CBW; AX=11111111 10011011= -155 decimal

CWD (convert signed word to signed double word): The CWD copies the sign bit of a word in
AX to all the bits of the DX register. i.e., it extends the sign of AX into all of the DX. The CWD
operation must be done before a signed word in AX can be divided by another signed word with
the IDIV instruction. It affects no flags.

e.g. DX =00000000 00000000

AX=11110000 11000111 = -3897 decimal

CWD; DX: AX  11111111 11111111 11110000 11000111 = -3897 decimal

Logical Instructions:

This type of instructions is used for carrying out the bit by operation. All the condition code
flags are affected depending upon the result. Basic logical operations available with 8086
instructions are AND, OR, NOT and XOR.

AND (Logical AND): This instruction ANDs each bit in a source byte or word with the same
number bit in a destination byte or word. The result is put in the specified destination. The contents
of specific source will not be changed.

The source operand that may be an immediate number, contents of a register or the contents
of a memory location. The destination operand can be a register or a memory location. Both
operands cannot be memory locations or immediate operands.

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OR (Logical OR): This instruction ORs each bit in the source byte or word with the corresponding
bit in the destination byte or word and stores the result in the destination. The contents of specific
source will not be changed. The source may be an immediate number, a register or a memory
location. The destination may be a register or memory location. Both source and memory cannot
be memory locations.

E.g. OR AH,CL

OR BP,SI

OR AX,0098H

OR [3000H],0008H

NOT (Logical Invert): The NOT instruction inverts the contents of an operand or a memory
location, bit by bit. It forms 1`s complement for a given byte or word.

E.g. NOT BX; Complement contents of BX register

NOT [5000H]

XOR (Logical Exclusive OR): This instruction Exclusive-ORs each bit in a source byte or word
with the same number of a bit in a destination byte or word. The result is in specified destination.

e.g.:- XOR AX,0098H

XOR AX,BX

XOR AX,[3200H]

TEST (Logical Compare Instruction): The TEST instruction performs a bit by bit logical AND
operation on the two operands. Flags are updated, but neither operand is changed. It is often used
to set flags before conditional jump instruction.

E.g. TEST AX,BX

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TEST CX,0001H

Shift Instructions:

SHL/SAL (Shift Logical/ Arithmetic Left): SAL and SAR are two mnemonics for the same
instruction. This instruction shifts each bit in the specified destination to the left and as a bit is
shifted out of the LSB position, a zero is put in the LSB position. The MSB will be shifted into the
CF. In the case of multiple-bit shifts, CF will contain the bit most recently shifted from the MSB.
Bits previously shifted into CF will be lost.

If the desired number of shifts is one, this can be specified by putting a 1 in the count
position of the instruction. For shifts of more than 1 bit position, the desired number of shifts is
loaded into the CL register, and CL is put in the count position of the instruction.

CF  MSB LSB  0

E.g. SAL BX,01

SAL AL,CL

SHR (Shift Logical Right): This instruction shifts each bit in the specified destination some no. of
bit positions to the right. As a bit is shifted right out of the MSB position, a zero is put in its place.
The bit shifted out of LSB position goes to CF. In the case of multiple-bit shifts, CF will contain
the bit most recently shifted from the LSB. Bits previously shifted into CF will be lost.

If the desired number of shifts is one, this can be specified by putting a 1 in the count
position of the instruction. For shifts of more than 1 bit position, the desired number of shifts is
loaded into the CL register, and CL is put in the count position of the instruction.

E.g. :- SHR BP,1

SHR AL,CL

SAR (Shift Arithmetic Right): This instruction shifts each bit in the specified destination some no.
of bit positions to the right. As a bit shifted out of MSB positions, a copy of old MSB is put in the

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MSB position. The LSB will be shifted into CF. In case of multiple bit shifts, CF will contain the
bit most recently shifted in from the LSB.

MSB  MSB LSB  CF

E.g.:- SAR DI,1H

SAR BX,CL

Rotate Instructions:

ROR (Rotate Right without Carry): This instruction rotate the contents of the destination operand
to the right (bit wise) either by one or by the count specified in CL, excluding carry. The LSB is
pushed into the carry flag and simultaneously it is transferred into the MSB position at each
operation.The remaining bits is shifted right by the specified count positions.

Ex: ROR BL,1

ROR AL,CL

ROL (Rotate Left without Carry): This instruction rotates the contents of the destination operand
to the left (bit wise) either by one or by the count specified in CL, excluding carry. The MSB is
pushed into the carry flag as well as the LSB position at each operation. The remaining bits are
shifted left sequentially by the specified count positions.

Ex: ROL AX,1

ROL BL,CL

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RCR (Rotate Right through Carry): This instruction rotates the contents(bit wise) of the
destination operand right either by one or by the specified count in CL, through CF. For each
operation, the carry flag is pushed into the MSB of the operand, and the LSB is pushed into carry
flag. The remaining bits are shifted right by the specified count positions. The PF,SF,ZF are
unchanged.

Ex: RCR BX,1

RCR AL,CL

RCL (Rotate Left through Carry): This instruction rotates the contents(bit wise) of the destination
operand left either by one or by the specified count in CL, through CF. For each operation, the
carry flag is pushed into the LSB, the MSB of the operand is pushed into carry flag. The remaining
bits are shifted left by the specified count positions. The PF,SF,ZF are unchanged.

Ex: RCL BX,1

RCL AL,CL

Flag Manipulation Instructions:

The flag manipulation instructions directly modify some of the flags of 8086. These
instructions modify the Carry (CF), Direction (DF) and Interrupt (IF) flags directly. The flag
manipulation instructions and their functions are listed below.

CLC - Clear Carry Flag

CMC - Complement Carry Flag

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STC - Set Carry Flag

CLD - Clear Direction Flag

STD - Set Direction Flag

CLI - Clear Interrupt Flag

STI - Set Interrupt Flag

CLC: This instruction resets the carry flag to 0.

CMC: If the carry flag is 0 before the instruction, it will be set to a 1 after the instruction. If the
carry flag is 1 before the instruction, it will be set to a 0 after the instruction executes.

STC: This instruction sets the carry flag to a 1.

CLI: This instruction resets the interrupt flag to 0.If the interrupt flag is reset, the 8086 will not to
respond to an interrupt signal on its INTR input. However, it has no effect on the nonmaskable
interrupt input, NMI.

STI: Setting the interrupt flag to a 1 enables the INTR interrupt input of the 8086.

CLD: This instruction resets the direction flag to 0.If the direction flag is reset, SI and DI will
automatically be incremented when one of the string instructions, such as MOVS,CMPS or SCAS
executes.

STD: STD is used to set the direction flag to a 1 so that SI and DI will automatically be
decremented to point the next string element when one of the string instructions executes.

String Instructions:

A series of data bytes or words available in memory at consecutive locations, are called as
byte strings or word strings. For referring to a string, two parameters are required.

a) Starting or end address of the string and

b) Length of the string. The length of the string is usually stored as count in CX register

REP (Repeat Instruction Prefix): This instruction is used as a prefix to other instructions. The
instruction to which the REP prefix is provided, is executed repeatedly until the CX register
becomes zero.

Ex: REP MOVSB  it will continue to copy string bytes until CX is zero.

There are two more options for the REP instruction .The first is REPE/REPZ.
The second is REPNE/PEPNZ.

REPE/REPZ (Repeat if Equal / Repeat if Zero): REPE and REPZ are two mnemonics for the
same prefix. These are used with compare string instruction.

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The REPE or REPZ will cause the string instruction to be repeated as long as the
compared bytes or words are equal (ZF=1) and CX is not yet counted down to 0. In other words,
there are two conditions that will stop the repetition: CX=0 (or) string bytes or words are not equal.

EX: REPE CMPSB  compare sting bytes until string bytes not equal.

REPNE/REPNZ (Repeat if Not Equal/ Repeat if Not Zero): The REPNE or REPNZ is used with
scan string instruction. It will cause string instruction to be repeated until the compared bytes of
words are not equal (ZF≠1) or until CX is zero.

EX: REPNE SCASW;  scan a string of words until a word in the string matches the word in
AX (or) until all of the string has been scanned.

MOVSB/MOVSW (Move String Byte or String Word): This instruction copies a byte or word
from a location in the data segment to a location in the extra segment. The offset of byte or word in
the DS must be in SI register. The offset of byte or word in the ES must be in DI register.

After the MOVS instruction is executed once, the index registers are automatically updated and
CX is decremented .The incrementing or decrementing of the SI and DI depends upon the direction
flag (DF).

When DF=0, SI and DI are incremented by one after MOVSB

SI & DI are incremented by two after MOVSW.

When DF=1, SI and DI are decremented by one after MOVSB

SI & DI are decremented by two after MOVSW.

CMPSB/CMPSW (Compare String Bytes or String Words): The CMPS instruction can be used to
compare two strings of bytes or words. The length of strings is store in CX register. The SI is used
to hold the offset of a byte or word in the source string and DI is used to hold the offset of a byte or
a word in the destination string. If both strings are equal, zero flag is set.

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SCASB/SCASW (Scan a String Byte or String Word): This instruction scans a string of bytes or
words for an operand byte or word in the AL or AX register. The string to be scanned must be in
the ES & DI contains the offset of string byte or word. Whenever a match to the specified operand
is found in the string execution stops and the zero flag is set. If no match found ZF is reset. The
REPNE prefix is used with SCAS instruction.

LODSB/LODSW (Load String Byte or String Word): This instruction loads the AL/AX register
by the content of a string pointed by DS:SI register pair .The SI is modified automatically
depending upon DF.

Ex: CLD

MOV SI, OFFSET Source_String

LODSB

STOSB / STOSW (Store String Byte or String Word): This instruction stores or copies a byte
from AL or a word from AX to a memory location in the ES pointed by DI register. After copy DI
is automatically incremented or decremented to point to the next string element is memory.

If DF=0, DI incremented by one for byte string.

DI is incremented by two for word string.

If DF=1, DI is decremented by one for byte string.

DI is decremented by two for word string.

Ex: - CLD

MOV DI, OFFSET Target_String

STOSB

Loop Instructions (or) Iteration Control Instructions:

These instructions can be used to execute a series of instructions some number of times.
The number of times the instruction sequence is to be repeated is loaded into CX. The conditional
and unconditional loop instructions and their functions are listed in the table.

LOOP (Loop unconditionally): This instruction is used to repeat a series of instructions some
number of times. The number of times the instruction sequence is to be repeated is loaded into CX.
Each time the loop instruction executes, CX is automatically decremented by 1.If CX is not zero,

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execution will jump to a destination specified by a label in the instruction. If CX = 0 after the auto
decrement, execution will simply go on to the next instruction after LOOP instruction.

Ex: - MOV BX, OFFSET; Point BX at first element in Array

MOV CX,40H; Load CX with number of elements in array.

Label: MOV AL,[BX] ; Get the element from array

ADD AL,07H ; Add correction factor

DAA; decimal adjust result

MOV [BX],AL; Put result back in array

INC BX

LOOP Label; Repeat until all elements adjusted.

Loop Instructions Function

Unconditional Loop:
Loop through a sequence of instructions from ‘Label’ until
1.LOOP Label
CX=0.

Conditional Loops:
Loop through a sequence of instructions from ‘Label’ while
1.LOOPE/LOOPZ Label (Loop if ZF=1 & CX≠0.
Equal/Zero)

2. LOOPNE/LOOPNZ Label (Loop

Loop through a sequence of instructions from ‘Label’ while
if Not Equal/Not Zero)
ZF=0 & CX≠0.

LOOPE/LOOPZ (Loop if Equal / Loop if Zero): This instruction is used to repeat a group of
instructions some number of times or until the zero flag becomes 0. The number of times the
instruction sequence is to be repeated is loaded into CX. Each time loop executes, CX is
automatically decremented by 1.

 If CX≠0 & ZF=1, execution will jump to a destination specified by label in the instruction.

 If CX=0 after auto decrement or if ZF=0, execution will simply go on to the next instruction
after LOOPE/LOOPZ.

Ex: MOV BX,OFFSET ARRAY

DEC BX
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MOV CX,100

NEXT: INC BX

CMP [BX],0FFH

LOOPE NEXT

In above example, the next element is checked if the element equals FFH.

LOOPNE / LOOPNZ (Loop if Not Equal / Loop if Not Zero): This instruction is used to repeat a
group of instructions some number of times or until the zero flag becomes a 1. The number of
times the instruction sequence is to be repeated is loaded into CX. Each time loop executes, CX is
automatically decremented by 1.

 If CX≠0 & ZF= 0, execution will jump to a destination specified by label in the instruction.

 If CX=0 after auto decrement or if ZF=1, execution will simply go on to the next instruction
after LOOPNE/LOOPNZ.

Ex: MOV BX,OFFSET ARRAY; point BX to just before start of array

DEC BX

MOV CX,100; put no. of array elements in CX

NEXT: INC BX point to next element in array

CMP [BX],0DH compare element with 0DH

LOOPNE NEXT

Branch Instructions (or) Control Transfer Instructions:

The control transfer or branch instructions transfer the flow of execution of the program to
a new address specified in the instruction directly or indirectly. When this type of instruction is
executed, the CS & IP registers get loaded with new values of CS & IP corresponding to the
location where the flow of execution is going to be transferred. These types of instructions are
classified in two types.

(i) Unconditional Branch (Control Transfer) Instructions: In case of unconditional control

transfer instructions, the execution control is transferred to the specified location independent of
any condition.

CALL (unconditional CALL (or) CALL a procedure): The CALL instruction is used to transfer
execution to a subprogram or procedure. There are two types of calls, Near and Far.

A near call is a call to a procedure which is in the same code segment as the CALL
instruction. When the 8086 executes a near CALL instruction, it decrements the stack pointer by 2
and copies the offset of the next instruction after the CALL on to the stack. This offset saved on the
stack is referred to as the return address. It also loads IP with the offset of the first instruction in

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the procedure. A RET instruction at the end of the procedure will return the execution to the
instruction after the call by copying the offset saved on the stack back to IP.

A far call is a call to procedure which is in a different segment from the one that contains
the CALL instruction. When the 8086 executes a far call, it decrements the stack pointer by 2 again
and copies the contents of CS register to stack. It then decrements the stack pointer by 2 again and
copies the offset of the instruction to the stack .Finally it loads the CS with the segment base of the
segment which contains the procedure, and loads IP with the offset of the first instruction of the
procedure in that segment. A RET instruction at the end of the procedure will return execution to
the next instruction after the CALL by restoring the saved values of CS and IP from the stack.

Fig: Stack diagram for a) Near CALL b) Far CALL

Ex: CALL MULTO;  MULTO is the name of the procedure

CALL BX;  BX contains the offset of the first instruction of the procedure

RET (Return from the procedure): The RET instruction will return execution from a procedure to
the next instruction after the CALL instruction which was used to call the procedure. At the end of
procedure, the RET instruction must be executed .When it is executed the previously stored content
of IP and CS are retrieved into the CS, IP registers from the stack, and the execution of the main
program continues further. The RET instruction affects no flags.

INT (Interrupt Type N): In the interrupt structure of 8086, 256 interrupts are defined
corresponding to the types from 00H to FFH. When an INT N instruction is executed, the TYPE
byte N is multiplied by 4 and the content of IP & CS of interrupt service routine will be taken from
Hexa multiplication (NX4) as offset address and 0000 as segment address. For the execution of this
IF must be enabled.

Ex: INT 20H

Type*4 = 20*4 = 80H

Pointer to CS and IP of the ISR is 0000:0080H

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INTO (Interrupt on Overflow): If the overflow (OF) flag is set, this instruction is executed. This is
equivalent to a TYPE 4 interrupt instruction. It will read a new value for IP from address 00010H
and a new value for CS from address 00012H.

Ex: INTO; Call interrupt procedure if OF=1

IRET (Interrupt Return or Return from ISR): This IRET instruction is used at the end of the
interrupt service routine (ISR) to return execution to the interrupted program. At the end of each
ISR, the IRET instruction must be executed. When IRET is executed, the stored values of IP, CS
and flags are retrieved from the stack to continue the execution of the main program.

JMP (unconditional Jump): This instruction unconditionally transfers the control of execution to
the specified address using 8-bit or 16-bit displacement or CS: IP. The JMP instruction affects no
flags. The JMP instruction may have the following three formats. The change in program flow that
can be caused by jump instruction is shown in below figure.

(ii) Conditional Branch Instructions: In the conditional branch instructions, the control is
transferred to the specified location provided the result of previous operation satisfies a particular
condition; otherwise, the execution continues a normal flow sequence.

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These instructions are often used after a compare instruction. The terms below and above
refer to unsigned binary numbers .Above means larger in magnitude .The terms greater than or less
than refer to signed binary numbers .Greater than means more positive.

S.NO MNEMONIC ‘JUMP IF …’ CONDITION TESTED

1. JA / JNBE Above / Not Below or Equal CF=0 or ZF=0

2. JAE / JNB Above or Equal / Not Below CF=0

3. JB / JNAE Below / Not Above or Equal CF=1

4. JNB / JAE Below or Equal / Not Above CF=1 or ZF=1

5. JG / JNLE Greater / Not Less nor Equal ZF=0 and SF=OF

6. JGE / JNL Greater or Equal / Not Less SF=OF

7. JL / JNGE Less / Not Greater nor Equal SF≠OF

8. JLE / JNG Less or Equal / Not Greater ZF=1 or SF≠OF

9. JE / JZ Equal / Zero ZF=1

10. JNE / JNZ Not Equal / Not Zero ZF=0

11. JC Carry CF=1

12. JNC Not Carry CF=0

13. JO Overflow OF=1

14. JNO Not Overflow OF=0

15. JP / JPE Parity / Parity Even PF=1

16. JNP / JPO Not Parity / Parity Odd PF=0

17. JS Sign SF=1

18. JNS Not Sign SF=0

19. JCXZ If CX Register is Zero CX=0

Processor Control Instructions:

The processor control or machine control instructions control the bus usage and execution. These
machine control instructions do not require any operand. They are

WAIT - Wait for TEST input pin to go low

HLT - Halt the Processor

NOP - No Operation

ESC - Escape to external device like numeric co-processor

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LOCK - Bus Lock Instruction Prefix

WAIT: When this instruction executes, the 8086 enters into idle condition, in which it is doing no
processing until the 8086 TEST input pin is made low. The WAIT instruction is used to
synchronize the 8086 with external hardware such as the 8087 math processor.

NOP: When NOP instruction is executed, the processor does not perform any operation till 3 to 4
clock cycles, except increments the IP to point to the next instruction. The NOP instruction can be
used to increase the delay of a delay loop.

HLT: The HLT instruction will cause the 8086 to stop fetching and executing instructions and
8086 will enter a halt state. The ways to get the processor out of the halt state are with an interrupt
signal on INTR pin, an interrupt signal on the NMI pin or a reset signal on the RESET pin.

LOCK: The lock prefix may appear with another instruction. When it is executed, the bus access is
not allowed for another master till the lock prefixed instruction is executed completely.

ESC: When ESC is executed, it frees the bus for an external master like a coprocessor or peripheral
devices. This instruction is used to pass instructions to a co-processor, such as the 8087 math
processor which shares the address and data bus with 8086.

ASSEMBLER DIRECTIVES:

An Assembler is a program which translates assembly language program into machine

language program. The assembler decides the address of each label and substitutes the values for
each of the constants and variables. It then forms the machine code for the mnemonics and data in
the assembly language program. The assembler will find out the syntax errors. The logical errors or
other programming errors are not found out by the assembler.

For executing a program, an assembler needs some hints from the programmer, i.e., the
required storage for a particular constant or variable, logical names of the segments, types of
different routines & modules, end of file etc…These types of hints are given to the assembler using
some predefined alphabetical strings, called Assembler Directives.

An assembly language program contains two types of statements: instructions & directives.
The instructions are translated into machine codes where as directives are not translated into
machine codes. The directives are machine statements to give direction to the assembler to perform
the task of assembly process. They control the organization of the program.

Some popular assemblers are

Intel 8086 macro assembler (ASM 86)

Borland Turbo assembler (TASM)

Microsoft macro assembler (MASM)

A macro assembler is an assembler which allows user to define sequence of

instruction of macro.

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DB (Definition Byte): The DB directive is used to reserve byte or bytes of memory locations in the
available memory.

Ex: RANKS DB 01H,02H,03H,04H

Message DB ‘Good Morning’

VALUE DB 50H

DW (Define Word): It defines a word type variable. It reserves two bytes of consecutive memory
locations and initializes those bytes with the specified values. It can define single or multiple word
variables.

Ex: WORDS DW 4567H,78ABH,045CH

PRODUCT DW 2 DUP(0)  It reserves 2 words of consecutive locations & initialize all the

4 bytes with zeros.

WDATA DW 5 DUP(6666H)  Reserves 10 bytes of memory locations & initializes all word

locations with 6666.

DD (Define Double word): This directive defines a double word variable. It reserves 4 bytes of
consecutive memory locations and initializes these memory locations with the specified values. It
can define single or multiple double word variables.

Ex: - NUMBER DD 12152025

NUMBERS DD 5 DUP(0)  Reserve 20 bytes of consecutive memory locations &

initializes them with zero’s.

DQ (Define Quad word): This directive defines a quad word type variable. It reserves 4 words (8
bytes) of consecutive memory locations and initializes them with the specified values. It can define
a single or multiple quad word variables.

Ex: - NUMBER DQ 0

BIG_NUMBER DQ 234598740192A92B

NUMBERS DQ 10 DUP(0)

DT (Define Ten bytes): The directive DT defines ten bytes variable .It reserves 10 bytes of
consecutive memory locations and initializes them with the specified values .It can define a single
or multiple ten bytes of variables . DT type variable are useful where math coprocessor instructions
are executed. Ex :- RESULTS DT 20 DUP(0)

NUM1 DT 0

ASSUME (Assume logical segment name): This directive is used to inform the Assembler, the
names of logical segments to be assumed for different segments used in the program.

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Ex: - ASSUME CS:CODE; It directs the assembler that the machine codes are available in
segment

named CODE.

ASSUME DS:DATA; It indicates assembler that the data items related to the program are

available in a logical segment named DATA.

END (End of program): The END directive is put after the last statement of a program to tell the
assembler that this is the end of the program module.

PROC (Procedure): This directive is used to identify the start of a procedure. It also specifies the
type of the procedure whether NEAR or FAR.

Ex: - RESULT PROC NEAR

ROUTINE PROC FAR

ENDP (End of Procedure): This directive is used along with the name of the procedure to indicate
the end of a procedure to the assembler.

Ex: - TEMP_CONTROL PROC; Start of procedure

; Procedure instruction statements

TEMP_CONTROL ENDP; End of procedure.

SEGMENT (logical segment): The directive SEGMENT is indicates the beginning of a logical
segment. The name of the segment is written before the directive.

Ex: - CODE SEGMENT

DATA SEGMENT

ENDS (End of Segment): This directive is used along with the name of the segment to indicate the
end of that logical segment.

Ex: - CODE SEGMENT; Start of logical segment

; Instruction statements

CODE ENDS; End of code segment

EQU (Equate): This directive is used to assign a name to some value. Whenever the assembler
finds the assigned name in the program, it replaces the assigned name with value.

Ex: - LABEL EQU 0500H

COUNT EQU 06H

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ORG (Originate): This tells the assembler to assign address to data items or instructions in a
program.

Ex: - ORG 200H

NAME (Logical name of a module): It is used to assign a specific name to an assembly language
program module when programs consisting of several modules are written.

OFFSET (Offset of a label): The OFFSET is an operator which tells the assembler to determine
the offset of a variable (data item) or procedure from the starting address of a segment. The offset
value is usually loaded into the register.

Ex: - MOV SI,OFFSET List

Before the above instruction the variable list has already been defined in data
segment.

PUBLIC: A large program may contain a number of program modules. Each module is
assembled, tested and debugged individually.

The PUBLIC directive is used to inform the assembler that the specified name or label can
be accessed for other program modules.

Ex: PUBLIC DIVISOR,DIVIDEND; which makes the two variables DIVISOR,DIVIDEND

available to other assembly modules.

EXTRN (External): The EXTRN directive is used to tell the assembler that the names or labels or
procedures following the directive are in some other assembly module.

If a variable or label is used in an instruction of another program module, it

must be specified external using EXTRN directive.

GLOBAL (Declare symbols as PUBLIC or EXTRN): The GLOBAL directive can be used in
place of a PUBLIC directive or in place of an EXTRN directive. For a name or symbol defined in
the current assembly module, the GLOBAL directive is used to make the symbol available to other
module.

Ex: GLOBAL MULTIPLIER; makes the variable DIVISOR public so that it can be accessed from
other assembly modules.

GLOBAL MULTIPLIER:WORD; tells the assembler that DIVISOR is a variable type which
is in another assembly module or EXTRN.

GROUP (Group the related segments): This directive is used to form the logical groups of
segments with similar purpose or type.
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Ex: - PROGRAM GROUP CODE, DATA, STACK

EVEN (Align on Even Memory Address): The EVEN directive updates the location counter to the
next even address, if the current location counter contents are not even, and assigns the following
routine or variable or constant to that address.

Ex: SALES DB 9 DUP (?)

EVEN

RECORDS DW 100 DUP(0)

PTR (Pointer): The PTR operator is used to declare the type of a label, variable or memory
operand. The operator PTR is prefixed by either BYTE or WORD.

Ex: - MOV AL, BYTE PTR [SI]

MOV BX, WORD PTR [2000H]

SHORT: This indicates to the assembler that only a 1 byte displacement is needed to code a Jump
instruction. If the jump destination is after the jump instruction in the program, the assembler will
automatically reserve 2 bytes for the displacement. Using the SHORT operator saves 1 byte of
memory by telling the assembler that it needs to reserve only 1 byte for this particular jump. So,
the destination must be in the range of -128 bytes to +127 bytes from the address of the instruction
after jump.

Ex: - JMP SHORT LABEL

TYPE: It directs the assembler to decide the data type of the specified label the “TYPE LABEL”
by the decided data type. For the word type variable the data type is 2, for double word type it is 4,
and for byte type it is 1.

Ex: MOV AX, TYPE STRING; if string is a word 0002H is in AX

PROCEDURES:

Whenever we need to use a group of instructions several times throughout a program, the
particular group of instructions can be written as a subprogram called “PROCEDURE”. Each time
we need to execute the sequence of instructions contained in the procedure, use the CALL
instruction to send the 8086 to the starting address of the procedure in memory. A RET instruction
at the end of the procedure returns execution to the next instruction in the main program .The
procedure can even be “nested” .This means that one procedure calls another procedure as part of
its instruction sequence.

A procedure may be a NEAR or FAR.

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Fig: Program flow to and from procedures a) Single Procedures b) Nested procedures

Passing parameters to and from Procedures: When we call a procedure, we want to make
some data values or addresses available to the procedure. These addresses or data values passed
back and forth between the main program and the procedure are commonly called “parameters”.
The four major ways of passing parameters to and from a procedure are

1. In registers

2. In dedicated memory locations accessed by name

3. With pointers passed in registers

4. With the stack.

Reentrant Procedures: Suppose if the 8086 was in the middle of executing a MULTIPLY
procedure, when the interrupt signal occurred and that also need to use the MULTIPLY procedure
in the interrupt service subroutine.

The below figure shows the program execution flow for this situation. When the interrupt
occurs, execution goes to the interrupt service procedure. The interrupt service procedure then calls
the MULTIPLY procedure when it needs it. The RET instruction at the end of the MULTIPLY
procedure returns execution to the interrupt service procedure. A special return instruction at the
end of interrupt service procedure returns the execution to the MULTIPLY procedure where it was
executing when the interrupt occurred. Here the MULTIPLY procedure must be written in such a
way that it can be interrupted, used, and “reentered” without loosing or writing over anything. A
procedure which can function in this way is said to be reentrant.

To be reentrant, a procedure must first of all push the flags and all registers used in the
procedure. Also, to be reentrant, a program should use only registers or the stack to pass
parameters.

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Fig: Program execution flow for Reentrant Procedure

Recursive Procedure: A recursive procedure is a procedure which calls itself. Recursive

procedures are often used to work with complex data structures called trees.

Example: the factorial of a number is the product of the number and all the positive integers less
than the number. For example, 5 factorial is equal to 5x4x3x2x1. To compute factorial of a number
N, the basic algorithm can be expressed as

IF N=1 THEN factorial=1,

ELSE factorial = N x (factorial of N – 1)

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Fig: Algorithm for program to compute factorial for a number N between 1 to 8

a) Flow diagram for N=1 b) flow diagram for N=3 c) program d) Flowchart

MACRO:

Whenever we need to use a group of instructions several times throughout a program, there
are two ways we can avoid having to write the group of instructions each time we want to use it.
One way is to write the group of instructions as a separate procedure. We can just call the
procedure whenever we need to execute that group of instructions. A big advantage of using a
procedure is that the machine codes for the group of instructions in the procedure only have to be
put in memory once. Disadvantages of using a procedure are the need for a stack, and the overhead
time is required to call the procedure and return to the calling procedure.

When the repeated group of instructions is too short or not appropriate to be written as a
procedure, we use MACRO. A Macro is a group of instructions and gives a name at the start of
program. A MACRO can be defined anywhere in a program using the directives MACRO and
ENDM. The label prior to Macro is the macro name which should be used in the actual program.
The ENDM directive marks the end of the instructions or statements sequence assigned with the
macro name. The following macro DISPLAY displays the message MSG on the CRT. The syntax
is as given,

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DISPLAY MACRO
MOV AX,DATA
MOV DS,AX
MOV DX,OFFSET MSG
MOV AH,09H
INT 21H
ENDM

A Macro may also be used in a data segment. A Macro may also be used to
represent statements. In other words, a macro may also be used to represent statements and
directives. The following examples shows a macro containing statements

STRINGS MACRO
MSG1 DB OAH,ODH,”Program terminated normally”,OAH,ODH,”$”
MSG2 DB OAH,ODH,”Retry, Abort, Fail”,OAH,ODH,”$”
ENDM
Passing parameters to a MACRO:

The programmer specifies the parameters of the macro those are likely to be changed each
time the macro is called. For example, the DISPLAY macro can be made to display two different
messages MSG1 and MSG2, as shown.

This parameter MSG can be replaced by MSG1 and MSG2 while calling the macro as shown.

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There may be more than one parameter appearing in the macro definition, meaning thereby
that there may be more than one parameters to be passed to the macro, and each of them is liable to
be changed. All parameters are specified in the definition sequentially and also in the call with the
same sequence.

Comparison of Procedures and Macros:

PROCEDURE MACRO

Accessed by CALL and RET mechanism Accessed during assembly with name given to
during program execution. macro when defined.

Machine codes for instructions only put in Machine code generated for instructions each time
memory once. called.

Parameters passed in registers, memory Parameters passed as part of statement which calls
locations or stack. macro.

Overhead time required to call the procedure Macro avoids the overhead time required for
and return to the calling program. calling and returning from a procedure.

Program flow is interrupted. Program flow is un interrupted.

Less memory is required to implement More memory is required to implement

procedures. procedures.

MODULAR PROGRAMMING:
Generally, industry-programming projects consist of thousands of lines of instructions or
operation code. This kind of a huge monolithic program would be unmanageable and
incomprehensible. Therefore, it is difficult to design, write, debug and test the project. Then the
complete project is divided into subproblems or small modules. Each independent module is
separately named and has individually invokeable program elements. The sizes of the modules are
reduced to a humanly comprehensible and manageable level. This approach is known as modular
programming. Usually the divide-and-conquer approach is used in programming.

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The characteristics of the module are given below:

1. Each module is independent of other modules.

2. Each module has one input and one output.

3. A module is small in size.

4. Programming a single function per module is a goal.

Advantages of Modular Programming The advantages of modular programming are the

following:

1. It is easy to write, test and debug a module.

2. Generally, the modules of common nature are prepared which can be used at many places.

3. The programmer can divide tasks and use the previously written programs.

4. If a change is to be made, it is made in the particular module; the entire program is not
affected.

5. Pieces can be independently debugged.

6. Work for multiple programmers can be divided.

7. Code can be reused.

8. Manageable Reduces problem to smaller, simpler, humanly comprehensible problems.

9. Divisible Modules can be assigned to different teams/programmers. Enables parallel work,

reducing program development time. Facilitates programming, debugging, testing,
maintenance.

10. Portable Individual modules can be modified to run on other platforms.

11. Re-usable Modules can be re-used within a program and across programs.

Disadvantages of Modular Programming The disadvantages of modular programming are the

following:

1. The combining of modules together is a difficult task.

2. It needs careful documentation as it may affect the other parts of the program.

3. While testing modules, it is found that the module under test may require data from other
modules or its results may be used by other modules. To solve such problems, special
programs called drivers are to be developed to produce the desired data for the testing of
modules. The development of drivers requires extra effort and time.

4. Modular programming requires extra time and memory.

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 Microprocessors & Interfacing
5. The modular programming was originally developed for writing long programs but this
technique can also be used for shorter programs written for microcomputers. Modules are
divided on functional lines and hence, they can form a library of programs. Modules of 20
to 50 lines should be developed. They are very useful. There is unnecessary wastage of
time in preparing shorter modules. Longer modules do not become of general nature. The
modules should be developed for common tasks and should be of general form.

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