VLSI CHIP DESIGN COURSE

MODULE-1
MOSFET: Metal-Oxide-Semiconductor Field-Effect Transistor Types
•Definition: 1.n-channel MOSFET (NMOS):
A MOSFET is a type of transistor used for switching and amplifying Current flows due to electrons (negative charge
electronic signals. carriers).
It is widely used in digital circuits, power electronics, and VLSI design. 2.p-channel MOSFET (PMOS):
Basic Structure Current flows due to holes (positive charge
1.Metal → Gate terminal (control terminal). carriers).
2.Oxide → Insulating layer (usually SiO₂) between gate and channel. Modes
3.Semiconductor → Source, Drain, and the channel (n-type or p- •Enhancement mode: Normally OFF; requires
type). VGS > threshold voltage to turn ON.
•Depletion mode: Normally ON; applying voltage
Terminals depletes channel to turn OFF.
1.Gate (G): Controls the current flow. Applications
2.Source (S): Where carriers enter. •Switching circuits (ON/OFF).
3.Drain (D): Where carriers leave. •Amplifiers in analog electronics.
4.Body (B): Connected to substrate (often grounded). •Digital logic gates in ICs.
Operation Principle •Power electronics (DC-DC converters, motor
•Current flows from Drain to Source when a voltage is drivers).
applied between Gate and Source (VGS).
•The gate voltage creates an electric field that controls
conductivity of the channel.
1.Enhancement Mode MOSFET (E-MOSFET) 2. Pinch-off & Saturation in MOSFET
•Definition:
A MOSFET that is normally OFF at •Pinch-off:
VGS=0V_{GS} = 0VGS​=0. •Happens when VDS=VGS−VTHV_{DS} = V_{GS} -
•How it works: V_{TH}VDS​=VGS​−VTH​.
•At VGS=0V_{GS} = 0VGS​=0 → no channel •The channel at the drain end becomes narrow,
exists. limiting current increase.
•When VGS>VTHV_{GS} > V_{TH}VGS​>VTH​ → •Saturation (Active region):
an inversion layer (channel) forms → current •Condition: VDS≥VGS−VTHV_{DS} \geq V_{GS} -
flows. V_{TH}VDS​≥VGS​−VTH​.
•Threshold Voltage (V_{TH}): Minimum gate voltage •Current equation:ID=1/2k(VGS−VTH)2 I_D =
needed to form a conducting channel. \tfrac{1}{2} k (V_{GS} -
•Types: V_{TH})^2ID​=21​k(VGS​−VTH​)2
•N-channel → needs positive VGSV_{GS}VGS​. •Here, IDI_DID​ depends mostly on
•P-channel → needs negative VGSV_{GS}VGS​. VGSV_{GS}VGS​, not VDSV_{DS}VDS​.
•Symbol: Shown with a broken channel line •Regions recap:
(indicating no natural channel). •Cutoff: VGS<VTHV_{GS} < V_{TH}VGS​<VTH​ → No
•Applications: Used in CMOS logic, amplifiers, current.
power electronics, switching circuits. •Linear (Ohmic): Low VDSV_{DS}VDS​, MOSFET
acts like resistor.
•Saturation: Current saturates, MOSFET behaves as
voltage-controlled current source.0
 AMBA Buses & Protocols
DSP (Digital Signal Processing)
SoC communication.
•Developed by ARM for
: Processing of real-world signals in digital form
•Definition
•APB (Advanced Peripheral Bus):
using mathematical operations.
•For low-bandwidth peripherals (UART, GPIO,
•Steps:
timers).
1.Capture analog signal.
•Simple, low-power, no pipelining.
2.Convert using ADC (Analog → Digital).
•AHB (Advanced High-performance Bus):
3.Apply operations (filtering, FFT, compression).
•For CPU memory DMA.
4.Convert back with DAC (Digital → Analog), if
•Supports pipelining, burst transfers.
needed.
•AXI (Advanced eXtensible Interface):
•Key Operations: Sampling, Filtering, Fourier
•High-performance, parallel read/write, low latency.
Transform (FFT), Modulation, Compression.
•Supports out-of-order transactions.
•Applications:
•Used in modern smartphones, GPUs, AI chips.
•Audio → noise cancellation, speech recognition.
•ACE (AXI Coherency Extensions):
•Image/Video → enhancement, compression.
•Adds cache coherency for multi-core CPUs.
•Communications → modulation, channel
•CHI (Coherent Hub Interface):
equalization.
•Next-gen, scalable, used in server/datacenter
•Medical → ECG/EEG signal analysis.
SoCs.
Performance order:
APB < AHB < AXI < ACE < CHI
SoC (System-on-Chip)
: A single chip that integrates CPU, GPU, DSP,
•Definition . IP Cores (Soft IP vs Hard IP)
memory, peripherals, I/O, power circuits. •IP Core:
A reusable design block (like processor,
•Advantages: Compact, low-power, cheaper, high memory controller, PCIe, DDR interface).
performance. •Soft IP:
•Types: •Delivered as HDL code (Verilog/VHDL).
•General-purpose SoC → CPUs with basic •Portable, flexible, can be optimized.
peripherals. •Example: ARM Cortex-M CPU core.
•Application-specific SoC → Custom-designed •Hard IP:
(e.g., Apple A-series). •Delivered as layout (GDSII).
•Heterogeneous SoC → Mix of CPU + GPU + DSP + •Fixed for a specific process node.
AI accelerators. •Example: DDR PHY, SerDes, ADC, PLL.
•Mobile SoCs → Snapdragon, Apple M-series. •Firm IP (middle ground): Delivered as netlist
•Automotive SoCs → NVIDIA DRIVE, Tesla FSD (partially fixed).
chip.
•IoT SoCs → ESP32, ARM Cortex-M.
•Examples: Snapdragon 8 Gen 3, Apple A16 Bionic,
ESP32.
 DESIGN AND VERIFICATION
2. Testbench
1. DUT (Design Under Test)
•Definition:
Verification environment used to apply inputs
•Definition:
The hardware module/circuit being verified.
•Implemented in RTL and check outputs of the DUT.
(Verilog/VHDL/SystemVerilog). •Written in HDL (Verilog/VHDL/SystemVerilog) but
•Example: ALU, counter, memory controller, etc. does not get synthesized → simulation-only.
•Focus: Correctness of functionality, timing, and •Functions:
protocols. •Generate stimulus (inputs).
Think of DUT as the actual circuit you are •Drive inputs to DUT.
building. •Monitor outputs.
•Compare DUT outputs with expected outputs
(checker/scoreboard).
•Report pass/fail.
Constraints in Physical Design (PD) •Power grid distribution requirements
In VLSI Physical Design (PD), constraints are rules and requirements that
guide synthesis, placement, routing, and timing closure to ensure the chip
4. Routing Constraints
functions correctly.
•Define how interconnects are routed.
1. Timing Constraints •Examples:
•Define how fast the design should operate.
•Wire length limits
•Examples:
•Metal layer usage restrictions
•Clock Period / Frequency (setup & hold
•Crosstalk & coupling noise limits
requirements)
•Routing blockages (reserved areas)
•Input/Output delays (relative to clock)
•Clock Skew & Jitter control 5. Design for Test (DFT) Constraints
•Ensure testability of the chip.
•False Paths & Multi-cycle Paths
•Scan chain insertion, BIST structures.
2. Area Constraints •Control signal routing (scan_enable,
•Define maximum silicon real estate allowed for placement.
•Floorplanning should respect: test_mode).
•Core/Die size limits
•Macro placement regions 6. Physical Verification Constraints
•Blockages & keep-out zones •Check against foundry rules (DRC, LVS, ERC).
3. Power Constraints •Density rules for CMP (Chemical-
•Restrict power consumption to meet spec. Mechanical Polishing).
•Includes: •Antenna effect constraints.
•Dynamic & Leakage power limits
•IR-drop limits
•Electromigration (EM) reliability rules
 In Digital Electronics
A gate is a basic digital circuit that performs a
4.NAND Gate
logical operation on one or more input signals to
•Output is the inverse of AND.
produce a single output. Gates are the building
•Universal gate (can implement any logic
blocks of digital systems.
Basic Logic Gates
function).
1.AND Gate 5.NOR Gate
•Output is 1 only if all inputs are 1. •Output is the inverse of OR.
•Symbol: D-shape with multiple inputs. •Universal gate too.
2.OR Gate 6.XOR Gate (Exclusive OR)
•Output is 1 if any input is 1. •Output is 1 if inputs are different.
3.NOT Gate (Inverter) 7.XNOR Gate (Exclusive NOR)
•Single input; output is the opposite of •Output is 1 if inputs are same
input.
NOTE- NOTE-
Why Universal Gates? NAND vs NOR
because we
•NAND and NOR are called universal gates because it is faster, smaller in size,
•NAND is preferred
can build any other gate (AND, OR, NOT, uses less power, and is easier in CMOS design.
XOR, etc.) using only NANDs or only •NOR is slower, needs more area, and
NORs. consumes more power.
NAND GATE USING CMOS NOR GATE USING CMOS

A B Y A B Y

0 0 1 0 0 1

0 1 1 0 1 0

1 0 1 1 0 0
1 1 0 1 1 0

CMOS NAND Gate CMOS NOR Gate

•Built using PMOS transistors in parallel •Built using PMOS transistors in series (pull-up
(pull-up network) and NMOS transistors network) and NMOS transistors in parallel
in series (pull-down network). (pull-down network).
•Output is LOW only when all inputs •Output is HIGH only when all inputs are
are HIGH. LOW.
•Advantage: Faster operation since PMOS •Disadvantage: Slower operation since PMOS are in
are in parallel → less resistance. series → more resistance.
 2. Sequential Circuits
1.Combinational Circuits
•Definition: Circuits whose output depends on
•Definition: Circuits whose output depends only on
present inputs + past history (previous
the present inputs.
states).
•No memory element is involved.
Have memory elements (like flip-flops, latches).
•Examples: Adders, Multiplexers, Encoders,
•Examples: Counters, Shift Registers, Finite State
Decoders.
Machines (FSM).
Key Points
Key Points
•Faster (no storage delay).
•Slower (due to clocking and memory).
•Easy to design and analyze.
•More complex to design.
•Cannot store past data.
•Can store and remember data.
•Adder: Adds binary numbers (e.g., Half
Adder, Full Adder) Examples:
•Multiplexer (MUX): Selects one input out of •Counters (Up, Down, Up/Down)
many •Shift Registers (SIPO, PISO)
•Encoder/Decoder: Data conversion •Finite State Machines (FSMs)
•Comparator: Compares two numbers •Timers
 SR Latch Using NOR & NAND (Short Notes) 2. NAND-based SR Latch
1. NOR-based SR Latch •Active LOW Inputs: S=0 → Set, R=0 → Reset
•Active HIGH Inputs: S=1 → Set, R=1 → Reset •Truth Table:
•Truth Table: Conditio
S R Q(next) Q'(next)
S Conditi n
R Q(next) Q'(next)
on 1 1 Q(prev) Q'(prev) Hold
0 0 Q(prev) Q'(prev) Hold 0 1 1 0 Set
1 0 0 1 Reset
1 0 1 0 Set
0 0 1 1 Invalid
0 1 0 1 Reset
1 1 0 0 Invalid

•Bistable circuit → Two stable states: Set & Reset.

•NOR latch → Active HIGH (S=1 Set, R=1 Reset).
Key Points •NAND latch → Active LOW (S=0 Set, R=0 Reset).
•NOR Latch → Active HIGH
•Invalid states:NOR: S=1, R=1 NAND: S=0, R=0
•NAND Latch → Active LOW
•Hold state → Output unchanged when inputs inactive.
•Both are bistable (2 stable states)
•Asynchronous → No clock, responds immediately to inpu
•Used for basic memory & flip-
•Applications → Memory, flip-flops, debouncing circuits.
flop designs
A counter is a sequential digital circuit that goes through a Asynchronous T Flip-Flop Counter – Technical
predefined sequence of states (usually binary) when it receives clock Notes
pulses. 1. Definition
Key Points •An asynchronous counter is a sequential circuit
1.Counts pulses → Each pulse changes the output state. built using T (Toggle) flip-flops.
2.Sequential circuit → Uses flip-flops to store states. •Called asynchronous because only the first flip-
3.Types of Counters: flop gets the external clock; others are triggered by
Asynchronous (Ripple): Flip-flops not clocked together → Slower. the output of the previous flip-flop.
Synchronous: All flip-flops clocked together → Faster. 2. Working Principle
Up Counter: Counts 0 → max •T input = 1 → Flip-flop toggles (changes state) at
Down Counter: Counts max → 0. every triggering clock edge.
1. Up/Down Counter: Can count both directions. •The output of each flip-flop acts as the clock input
2. Ring & Johnson Counters: Special counter types for for the next flip-flop → produces a ripple effect
sequences. (hence ripple counter).
Applications •Each flip-flop divides the clock frequency by 2.
•Frequency division 3.Types of Asynchronous T-FF Counters
•Digital clocks & timers •Up Counter: Counts upward (0 → max).
•Event counting •Down Counter: Counts downward (max → 0).
•Digital systems & microprocessors •Up/Down Counter: Can count in both directions
Basic Example (2-bit Up Counter) using control signals.
•Sequence: 00 → 01 → 10 → 11 → 00 → …
•Requires 2 flip-flops for 2 bits.
 Programmable Logic PLA (Programmable Logic Array)
•Definition: Digital circuits whose logic can be programmed •Programmable AND + Programmable OR → High flexibility.
by the user after manufacturing. •Implements multiple logic functions.
•Reprogrammability – Logic functions can be modified after •Slower & costlier than PAL.
manufacturing.
•Flexibility – Supports both combinational and sequential logic
designs.
•Fast Prototyping – Enables quick design testing without custom
IC fabrication.
Types:
•PROM: Fixed data storage PAL (Programmable Array Logic)
•PLA: Programmable AND + OR arrays •Programmable AND + Fixed OR → Lessflexible.
•PAL: Programmable AND + Fixed OR
•Faster & cheaper than PLA.
•CPLD: Multiple PLDs on one chip
•FPGA: Highly flexible, widely used today
•Used for standard logic functions.
Advantages:
•Reprogrammable
•Faster prototyping
•Flexible for combinational & sequential designs
Applications:
•Digital system design
•Communication & signal processing PLA is more flexible because both AND and OR arrays are
•Embedded systems,VLSI prototyping programmable, while PAL is faster and cheaper because only
the AND array is programmable and the OR array is fixed.
FPGA
SRAM in FPGA
•Full Form: Field Programmable Gate Array
•Full Form: Static Random Access Memory
•Definition: An FPGA is a reconfigurable digital logic device
•Role in FPGA:
made up of a grid of programmable logic blocks (CLBs),
• Stores the configuration data (bitstream)
interconnects, and I/O blocks.
that defines FPGA logic functions.
•Purpose: Used to implement custom digital circuits after
• Used as on-chip memory for data storage
manufacturing.
during circuit operation.
•How it works:
Key Points
• Logic is designed using HDL (e.g., Verilog, VHDL).
1.Volatile Memory → Loses data when power is off
• Configuration data is loaded into FPGA.
→ Needs reconfiguration at power-up.
• FPGA behaves like the designed circuit.
2.Fast Access → Ideal for high-speed FPGA
Key Features of FPGA
operations.
1.Reprogrammable → Logic can be changed anytime.
3.Flexibility → Allows FPGA to be reprogrammed
2.Parallel Processing → Multiple tasks can run at once → High
multiple times.
performance.
Usage in FPGA
3.High Logic Density → Supports complex circuits like
•Stores lookup tables (LUTs) for logic
processors, DSPs.
implementation.
4.On-chip Memory → For storing data and instructions.
•Used in Block RAMs (BRAMs) for data
5.I/O Flexibility → Supports various interfaces (UART, SPI, I2C).
processing.
6.Low Development Time → No custom chip fabrication needed.
•Holds routing and interconnect data for circuit
7.Supports Prototyping → Ideal for testing designs before making
connections.
ASICs.
State Machine Design
A State Machine (or Finite State Machine, FSM) is a
sequential circuit that moves through a sequence of states
based on inputs and generates outputs.
Steps in State Machine Design
1.Understand the Problem → Define inputs, outputs, and
behavior.
2.Identify States → Represent different conditions or steps.
3.State Diagram / Table → Show transitions between states. •Moore Machine:
4.State Assignment → Assign binary codes to states. •Output depends only on the current state.
5.Next State & Output Logic → Use Karnaugh Maps or •Synchronous, more stable, but slower (slight
Boolean equations. delay).
6.Implement with Flip-Flops & Logic Gates → D, T, or JK •Mealy Machine:
flip-flops commonly used. •Output depends on state + input.
Types of FSM •Faster, fewer states, but less stable.
1.Moore Machine → Output depends on state only.
2.Mealy Machine → Output depends on state + inputs.
Applications
•Traffic light controllers
•Sequence detectors
•Digital counters & timers
•Communication protocols
A Sequence Detector in FSM (Finite State Machine) is a digital Overlapping Sequence Definition
circuit that detects a specific sequence of bits (like 1011) in a An overlapping sequence detector allows part of the
stream of input data. sequence to be reused for the next detection, so detection
Key Points: can happen even if the sequence bits overlap in the input
•Inputs: Bit stream (0s and 1s) stream.
•Output: 1 when the desired sequence is detected, else 0 Example: Sequence = 1011
•FSM Type: Can be Moore or Mealy machine •Input stream: 1011011
Steps to Design: •If overlapping is allowed, the detector finds two sequences
1.Define Sequence: Example: 1011 • First 1011 → Detected at bits 1–4
2.Draw States: Each state represents how much of the sequence • Second 1011 → Detected at bits 4–7 (notice
has been detected. overlap at bit 4)
3.State Transitions: Based on input (0 or 1), decide next state. Without overlapping, the second detection would only
4.Output: start after the first detection ends, so you'd only detect
1. Moore → Output depends on state once.
2. Mealy → Output depends on state + input Key Points
Example: •Moore Machine: Output depends on the state →
For sequence 1011: Output = 1 when the final state is reached.
•States: S0 (start), S1 (1), S2 (10), S3 (101), S4 (1011 → Output=1) •Mealy Machine: Output depends on state + input →
Applications: Output = 1 immediately when the sequence ends.
•Digital communication •Overlapping means the FSM reuses states for the next
•Pattern detection in streams detection without resetting to the initial state.
•Data decoding
•Verilog is a Hardware Description Language (HDL) used 5.Timing Controls:
to model, design, and verify digital circuits at different levels: 1.#10 → delay by 10 time units.
• Behavioral level (high-level code) 2.@posedge clk → trigger at clock's rising
• Register-Transfer Level (RTL) edge.
• Gate-level modeling 6.Comments:
It is widely used in VLSI design, FPGA programming, and ASIC 1. Single-line: //
development. 2. Multi-line: /* */
Verilog Basics Hierarchies-Top-Down Design
1.Modules: •Start with system-level design → break into subsystems
1. Basic building blocks of Verilog. → modules → components.
2. Define inputs, outputs, and functionality of the circuit. •Flow: Specs → Architecture → Modules → Gates.
3. Example: module, endmodule •Pros: Clear structure, easy verification.
2.Data Types: •Example: CPU → ALU → Logic gates.
1.wire: For connections between hardware components. Bottom-Up Design
2.reg: Stores values like flip-flops. •Start with basic components → build modules →
3Operators: combine into full system.
1. Arithmetic (+, -, *), Logical (&&, ||), Relational (>, <) •Flow: Gates → Modules → Subsystems → System.
4.Procedural Blocks: •Pros: Reuses existing blocks, modular design.
1.initial: Runs once at start. •Example: Gates → ALU → CPU.
2.always: Runs whenever inputs change or at clock
edge.
Behavioral Modeling 1. Keywords
•What: Describes what the circuit does, not how it’s built. •Definition:
•Uses: initial, always blocks, high-level constructs like if, case. Predefined, reserved words in Verilog with special
•Example: meanings.
•always @(posedge clk) •Examples:
• q = d; // Behavior: On clock edge, q takes d module, endmodule, input, output, wire, reg,
•Advantage: Simple, easy to write and understand. always, assign, if, else.
2. Dataflow Modeling •Important:
•What: Describes how data flows through the circuit using • Cannot be used as names for variables,
equations. modules, or signals.
•Uses: assign statements, continuous assignments. • Case-sensitive → always ≠ Always.
•Example: 2. Identifiers
•assign y = a & b; // y = a AND b •Definition:
•Advantage: Good for combinational circuits. User-defined names for variables, signals, modules,can
3. Structural Modeling be 1024 characters etc.
•What: Describes the circuit as a connection of components (like •Rules:
gates). • Must start with a letter or underscore (_)
•Uses: Instantiate predefined modules like AND, OR gates. • Can include letters, digits, and underscores.
•Example: • Case-sensitive → Data ≠ data.
•and g1 (y, a, b); // AND gate named g1 •Examples:
•Advantage: Matches actual hardware structure. count, clk, reset_1, dataBus.
Number Format
[size]'[base][value] <size>'<base><value>
•size → Number of bits (e.g., 4 for 4-bit). Bases and Their Letters
•base → Number system: Base Letter Example Meaning
• b → Binary Binary- b/B 4'b1010 4-bit binary (1010)
• o → Octal Octal- o/O 6'o77 6-bit octal (77)
• d → Decimal Decimal- d/D 8'd25 8-bit decimal (25)
• h → Hexadecimal Hexadecimal- h/H 16'h1F 16-bit hex (1F)
•value → The actual number.
Examples Examples in All Formats
4'b1010 // 4-bit binary → 1010 verilog
8'd25 // 8-bit decimal → 25 Copy code
6'o77 // 6-bit octal → 77 4'b1010 // Binary: 1010 (decimal 10)
(octal) 6'o77 // Octal: 77 (decimal 63)
16'h1F // 16-bit hex → 1F 8'd25 // Decimal: 25
(hexadecimal) 16'h1F // Hex: 1F (decimal 31)
Special Cases Extra Notes
•Underscore _ can be used for readability: Underscores _ improve readability: 8'b1010_1101
8'b1010_1101
•x → Unknown, z → High Impedance: x → Unknown value → 4'b1x0z
4'b1x0z
z → High-impedance value
1. Strings in Verilog 2. Four Values in Verilog c. Concatenation
•A string is a sequence of characters. a. Individual Registers reg [7:0] a, b, c, d;
•Mainly used in testbenches for displaying reg [7:0] a, b, c, d; reg [31:0] all_values;
messages. initial begin initial begin
•In Verilog-2001: use reg [8*N:1] a=10; b=20; c=30; d=40; a=10; b=20; c=30;
•In SystemVerilog: use string $display("Values: %d, d=40;
Example (Verilog-2001): %d, %d, %d", a, b, c, d); all_values = {a, b,
reg [8*20:1] my_string; // 20 end c, d};
characters b. Array of Registers $display("Combined:
initial begin reg [7:0] values[3:0]; %h", all_values);
my_string = "Hello Verilog"; initial begin end
$display("String: %s", values[0]=10;
my_string); values[1]=20; values[2]=30;
end values[3]=40; 3. Display Strings with Values
Example (SystemVerilog): $display("Values: %d, reg [7:0] a,b,c,d;
string my_string; %d, %d, %d", values[0], initial begin
initial begin values[1], values[2], a=5; b=10; c=15;
my_string = "Hello Verilog"; values[3]); d=20;
$display("String: %s", end $display("Values are:
my_string); %d, %d, %d, %d",
end a,b,c,d);
end
1. Wire •Difference
•A wire represents a physical connection between hardware •Wire is like a connection; it cannot store a
elements. value.
•It cannot store a value by itself; its value comes from driving •Reg can store a value and keep it until
logic like assign statements or outputs of modules. changed.
•Usually used in combinational logic. •Wire is used for combinational logic.
Key Points: •Reg is used for sequential logic.
•Cannot be assigned inside always blocks.
•Can be assigned using assign statements. Combination of Reg and Wire
Example:
module wire_reg_example(input a, b, input clk,
wire a, b, c;
output c);
assign c = a & b; // c gets the AND of a and b
wire w; // combinational wire
2. Reg (Register) reg r; // sequential register
•A reg stores a value.
•Can be assigned inside always blocks or initial blocks.
assign w = a & b; // wire gets AND of a and b
•Used in sequential logic (like flip-flops) or testbenches.
always @(posedge clk) begin
Key Points:
r <= w; // register stores the wire value at
•Holds its value until updated. clock edge
•Can represent memory elements in hardware.
end
Example:
assign c = r; // output driven by register
reg a, b, c;
endmodule
always @(posedge clk) begin
Verilog / SystemVerilog Data Types 3. net
1. int- Integer type used to store whole numbers. •Definition: Represents a connection
•Size: 32-bit signed by default in SystemVerilog. between hardware elements.
•Usage: Counters, loops, calculations in testbenches. •Example types: wire, tri, wand,
Example: wor.
int i; •Usage: Used to transfer values
initial begin continuously from drivers to sinks.
i = 10; Example:
i = i + 5; // i becomes 15 wire a, b, c;
end assign c = a & b; // c gets
2. time AND of a and b continuousl
•Definition: Special type to store simulation time values.
Memories in Verilog
•Size: 64-bit unsigned.
•Memories store multiple values as arrays of
•Usage: Measuring time intervals, delays, or timestamps. reg.
Example: •1D memory: reg [7:0]
time t_start, t_end;
memory[3:0]; → 4 elements, 8-bit each.
initial begin
•2D memory: reg [7:0]
t_start = $time; #10;
table[0:3][0:3]; → 4×4 matrix.
t_end = $time;
•Access with index, e.g., memory[0] or
$display("Elapsed time: %0t", t_end -
table[0][1]
t_start);
end
 •Common Use:
Time in Verilog – Key Notes Delays, timing checks, debugging, testbenches.
•Definition: Arrays in Verilog – Key Notes
time is a 64-bit integer used to store simulation time values. •Types:
•Functions: • Packed Arrays: Bits are packed together → Used for
• $time → Returns current simulation time (64-bit). vectors.
• $stime → Returns current simulation time (32-bit). Example: reg [7:0] data; → 8-bit vector.
• $realtime → Returns simulation time as a real • Unpacked Arrays: Collection of variables → Used for
number. memories.
•Directive: Example: reg [7:0] mem[0:15]; → 16 words,
timescale defines time unit and precision: each 8-bit wide.
•`timescale 1ns/1ps •Example – Packed:
•→ 1 ns = time unit, 1 ps = precision. •reg [3:0] a; // 4-bit vector
•Usage: •Example – Unpacked (Memory):
•time t1, t2; •reg [7:0] mem [0:3]; // 4 locations,
•initial begin each 8-bit
• t1 = $time; •initial begin
• #10; • mem[0] = 8'hAA;
• t2 = $time; • mem[1] = 8'hBB;
• $display("Time diff = %0t", t2 - t1); •end
•end •Multi-dimensional Arrays (SystemVerilog):
•int arr[3][4]; // 3x4 matrix
Structure Breakdown of module
1.module ... endmodule → Wraps the design code. module <module_name> (port_list);
2.Port list → Inputs/outputs that connect to the outside // 1. Port Declarations
world. input <input_ports>;
3.Declarations → Internal variables like wire, reg. output <output_ports>;
4.Logic → Continuous assignments (assign) or procedural inout <inout_ports>; // Optional for bidirectional ports
blocks (always). // 2. Internal Declarations
5.Instantiation → Calling another module inside. wire <wire_signals>; // For connecting components
reg <registers>; // For storing values in procedural
1.EX blocks
module d_ff (reset, clk, d, q); // 3. Continuous Assignments or Procedural Blocks
input reset, clk, d; // Inputs assign <signal> = <expression>; // For combinational logic
output reg q; // Output should be reg because it (with wires)
changes in always block // always blocks for sequential/combinational logic
always @(posedge clk or posedge reset) begin always @(sensitivity_list) begin
if (reset) // Behavioral logic
q <= 1'b0; // Reset output to 0 end
else // 4. Instantiations of other modules (if required)
q <= d; // On clock edge, output follows input d // module_name instance_name (.port1(signal1),
end .port2(signal2));
endmodule
endmodule
D Flip-Flop (DFF) Concept of t ff from dff:
Definition:A D flip-flop stores the value of input D at the clock •We know the T flip-flop equation:
edge and outputs it as Q. 𝑄𝑛𝑒𝑥𝑡 = 𝑇 ⊕ 𝑄
•Called Data or Delay flip-flop. •A D flip-flop stores whatever is on D at the next
Working: clock edge:
•On each rising clock edge: 𝑄𝑛𝑒𝑥𝑡 = 𝐷
Qnext=DQ_{next} = DQnext​=D •So, to make a T flip-flop from a D flip-flop, we
•When reset = 1 → Q = 0. connect:
Truth Table: 𝐷 =𝑇⊕𝑄
Applications: That way, when T=1 → Q toggles;
•Data storage When T=0 → Q holds its value.
•Shift registers instantiate means using a module inside
•Counters another module.
T Flip-Flop (TFF) module top;
Definition:A T flip-flop toggles its output when T = reg D, clk, reset; Here:
1 at each clock edge. wire Q; •DFF → module name
T Q(next)
•Called Toggle flip-flop. // Instantiation of DFF (blueprint)
0 Q DFF d1(D, clk, reset, Q); •d1 → instance name (real
Working:
•On each rising clock edge: 1 ~Q // Here d1 is the instance object)
Qnext=T⊕QQ_{next} = T \oplus QQnext​=T⊕Q name
where ⊕ = XOR (toggle when T=1). endmodule
T flip-flop (toggles when T=1) Synchronous Circuits
module TFF(input clk, input reset, input T, output •All flip-flops get the same clock signal at the same time.
reg Q); •All state changes happen together on the clock edge.
always @(posedge clk or posedge reset) Key Points:
if (reset) Q <= 1'b0; •Clock is common → all flip-flops change simultaneously.
else if (T) Q <= ~Q; •Faster operation, predictable timing.
endmodule •Example: Synchronous Counter
4-bit Ripple Counter using TFFs Diagram Idea:
•Tie T=1 for all stages (always toggle). CLK ---> FF1 ---> Q1
•Clock of each stage is the Q of the previous stage (ripple). |-> FF2 ---> Q2
module ripple_counter_4bit(input clk, input reset, |-> FF3 ---> Q3
output [3:0] Q); |-> FF4 ---> Q4
TFF t0(.clk(clk), .reset(reset), .T(1'b1), All flip-flops share the same clock line.
.Q(Q[0])); 2. Asynchronous Circuits (Ripple)
// Next stages clock from previous Q (ripple) •Only the first flip-flop gets the clock directly.
TFF t1(.clk(Q[0]), .reset(reset), .T(1'b1), •The output of one flip-flop acts as the clock for the next one.
.Q(Q[1])); •Changes happen one after the other → ripple effect.
TFF t2(.clk(Q[1]), .reset(reset), .T(1'b1), Key Points:
.Q(Q[2])); •Clock is not common → changes propagate stage by stage.
TFF t3(.clk(Q[2]), .reset(reset), .T(1'b1), •Slower due to ripple delay.
.Q(Q[3])); •Example: Ripple Counter
endmodule Diagram Idea:
What it does CLK ---> FF1 ---> Q1 ---> FF2 ---> Q2 --->
•Counts 0000 → 1111 and rolls over. FF3 ---> Q3 ---> FF4 ---> Q4
•Each higher bit toggles when all lower bits roll over (hence “ripple”). Each flip-flop clock comes from the previous output.
. Basic Gates instantiation in Verilog
Verilog has built-in primitives for logic gates like:
2.Testbench to Check Gates
•and, or, not, nand, nor, xor, xnor
module test;
reg a, b;
Example: Instantiation of Basic Gates
module basic_gates(a, b, y_and, y_or, wire y_and, y_or, y_not,
y_xor;
y_not, y_xor);
input a, b;
// Instantiate the basic
output y_and, y_or, y_not, y_xor;
gates module
// Instantiation of gates basic_gates bg(a, b, y_and,
y_or, y_not, y_xor);
and g1(y_and, a, b); // AND gate
or g2(y_or, a, b); // OR gate
initial begin
not g3(y_not, a); // NOT gate
(single input) a = 0; b = 0;
xor g4(y_xor, a, b); // XOR gate #10 a = 0; b = 1;
#10 a = 1; b = 0;
endmodule
#10 a = 1; b = 1;
Here:
#10 $finish;
•and g1(...) → and is gate name, g1 is instance name.
end
•Inputs come last, output comes first.
1. Arithmetic Operators-Used for basic math. Bitwise OperatorsWorks on each bit separately.
•+ Addition: sum = a + b; → If a=5, b=3 → sum=8 •& AND: bitwise AND → a & b
•- Subtraction: diff = a - b; → 5-3=2 •| OR: bitwise OR → a | b
•* Multiplication: mul = a * b; → 5*3=15 •^ XOR: bitwise XOR → a ^ b
•/ Division: div = a / b; → 5/3=1 •~ NOT: bitwise NOT → ~a
•% Modulus: mod = a % b; → 5%3=2 •^~ or ~^ XNOR: bitwise XNOR → a ~^ b
Example:a = 4'b1010; b = 4'b1100;
Relational Operators-Used in comparisons; output is 1 (true) or 0 (false).
•== Equal: (a==b) → true if a=b y = a & b; // y=1000
•!= Not Equal: (a!=b) → true if a≠b 5. Reduction Operators-Apply operation on all bits of a signal.
•< Less than: (a<b) → true if a < b •&a → AND all bits together
•> Greater than: (a>b) → true if a > b •|a → OR all bits
•<= Less or equal: (a<=b) → true if a ≤ b •^a → XOR all bits
•>= Greater or equal: (a>=b) → true if a ≥ b •~&a → NAND all bits
Example:if(a > b) y = 1; •~|a → NOR all bits
else y = 0; Example:a = 4'b1101;y = &a; //
Logical Operators-Used for conditions, works on 1-bit logic (true/false). 6. Shift Operators-Shift bits left or right.
•&& AND: true if both are true → (a && b) •a << 1 → Shift left by 1 (fills zeros on right)
•|| OR: true if any one is true → (a || b) •a >> 1 → Shift right by 1 (fills zeros on left)
•! NOT: inverts value → !a •a <<< 1 → Arithmetic left shift (keeps sign)
Example:if(a && b) y = 1; // y=1 only if a=1 and b=1 •a >>> 1 → Arithmetic right shift (keeps sign)
Example:a = 4'b1010;
Concatenation & Replication y = a << 1; // y=0100
•Concatenation {a,b} joins bits → {2'b10,2'b01} = 1001
Conditional Operator
•Replication {{n{a}}} repeats n times → {{2{2'b10}}} = 1010
Like if-else in one line:
Example: assign y = (sel) ? a : b; // if sel=1, y=aelse y=b
a = 2'b10; b = 2'b01;y = {a,b}; // y=1001;
operator precedence in Verilog explained in one simple sentence from highest to lowest:First unary operators like ! , ~ , + , - are done, then
multiplication, division, modulus, then addition and subtraction, then shifts, then relational checks, then equality checks, then bitwise AND,
XOR, OR, then logical AND and OR, then conditional operator ?:, then concatenation, and finally assignment operators.
Timing Control in Verilog 4. Forever Loop
Timing control means delaying or scheduling events •Repeats a statement forever, often used for clocks.
in simulation time. It helps to model real hardware •Example:
delays. forever #5 clk = ~clk;//Toggle clk every 5 units
1. Delay Control (#) 5. Repeat Loop
•# introduces a time delay before executing a •Repeats a block fixed number of times.
statement. •Example:
•Example: Repeat(4)#10 a = a + 1;//Repeat 4times with delay
#10 a = 1; // After 10 time units, 6. While / For Loops
assign a = 1 •While: Runs while condition is true
2. Event Control (@) •For: Runs fixed iterations
•Waits for an event like a signal change or clock edge. •Example:
•Examples: for(i=0; i<5; i=i+1) #5 data = data + 1;
@(posedge clk) a = 1; // Execute when 7. Initial and Always Blocks
clk rises •initial: Runs once at simulation start
@(negedge clk) b = 0; // Execute when •always: Runs continuously whenever condition is met
clk falls •Example:
3. Wait Statement initial begin
•Waits until a condition becomes true. #10 a = 1;
•Example: end
wait(a == 1) b = 1; // When a becomes always @(posedge clk) q <= d; // Continuous on
1, then b=1 clock edge
Delay Control in Verilog
Delay control tells when a statement should be executed in simulation
Event-Based Delay Control in Verilog (Short Notes)
time. Waits for signal/event change before executing a statement.
There are three types: Simple Event Control: Executes when a signal changes.
1. Regular Delay Control (#) Example: @(a) b=1; → Run when a changes.
•Adds a fixed time delay before executing the next statement. Edge-Sensitive Event Control: Executes on rising/falling
•Example: edges.
#10 a = 1; // After 10 time units, a becomes 1 Example: @(posedge clk) q=d; → Run on rising edge.
•Used for modeling gate delays, testbenches, etc. Example: @(negedge clk) q=d; → Run on falling edge.
2. Intra-Assignment Delay (# inside assignment) Event OR Control: Executes when any one signal
changes.
•The right-hand side is evaluated immediately, but the assignment
Example: @(a or b) c=1; → Run when a or b changes.
happens after the delay. Event AND Control: Executes when all signals change.
•Example: Example: @(a and b) c=1; → Run when both a and b
a = #5 b + c; // b+c calculated now, assigned to change.
a after 5 time units Named Event Control: Executes on user-defined events
•Useful when you want to delay the assignment, not the calculation. triggered with ->.
3. Inter-Assignment Delay (# before assignment) Example:
•The whole statement is delayed. event start;
-> start; // Trigger
•Example:
always @(start) ... // Run on event
#5 a = b + c; // After 5 units, evaluate b+c and
assign to a
•Useful for testbench stimulus timing.
Procedural Blocks in Verilog . Sequential Blocks (begin–end)
Procedural blocks describe behavioral modeling in Verilog. •Statements inside begin and end run one after
Statements inside these blocks run sequentially rather than in another (in order).
parallel. •Example:
There are mainly two types: initial begin
1. Initial Block a = 1;
•Executes only once at the start of simulation. b = 2;
•Mostly used in testbenches for stimulus generation. c = a + b; // Runs after a & b are
•Example: assigned
initial begin end
a = 0; •Used when order of execution matters.
#10 a = 1; // after 10 units, a=1 2. Parallel Blocks (fork–join)
end •Statements inside fork and join run
2. Always Block simultaneously (in parallel).
•Executes continuously whenever the condition/event is true. •Example:
•Used for modeling combinational and sequential logic. initial fork
•Example: #5 a = 1; // All start together
always @(posedge clk) // sequential logic #10 b = 2;
•The initial block runs only once at the start of simulation, mainly for #15 c = a+b;
testbench and setup purposes, and does not always need event control. join
•The always block runs repeatedly whenever the event occurs, used for •Used when multiple tasks should happen at the same
design logic, and requires event sensitivity.
time.
Blocking Assignment (=) 2. if–else if–else Ladder 5. casez / casex
•Executes in order (one after another). •Checks multiple conditions in •casez ignores z (high-impedance)
•Next statement waits until the current one finishes. order. bits.
•Used for combinational logic mostly. •Example: •casex ignores x (unknown) bits.
•Example: if (a > b)
a = b; // First a=b max = a; •Example:
c = a; // Then c=a else if (b > c) casez(data)
Execution order: a=b → c=a max = b; 4'b1z00: y = 1;
2. Non-Blocking Assignment (<=) else default: y = 0;
•Executes in parallel (all right sides evaluated first, then max = c; endcase
assigned). 3. Nested if–else 6. Conditional Operator (?:)
•Used for sequential logic like flip-flops. •if–else inside another if–else. •Shorthand for if–else in one line.
•Example: •Example:
if (a > b) begin
•Example:
a <= b; // b assigned to a later
c <= a; // a assigned to c later if (a > c) max = a;
max = (a > b) ? a : b;
Execution order: b→a and a→c happen together else max = c; 4. case Statement
CONDITIONAL STATEMENTS end •Selects one block based on expression value
1. if–else Statement •Example:
•Executes a block if the condition is true, otherwise executes case(sel)
the else block. 2'b00: y = a;
•Example: 2'b01: y = b;
if (a > b) 2'b10: y = c;
max = a; default: y = 0;
else endcase
max = b;
Loops in Verilog RTL Modeling in Verilog
Loops help repeat a set of statements multiple 4. forever Loop Definition:
times. •Runs continuously RTL (Register Transfer Level) Modeling describes
1. for Loop forever (often used a digital circuit in terms of data flow between
for clock generation). registers and the logical operations performed on
•Used when number of iterations is known. that data.
•Syntax: •Syntax:
forever #5 clk It focuses on:
for (i=0; i<5; i=i+1) •Registers (storage elements)
$display("i=%d", i); = ~clk; //
•Data Transfers (between registers)
•Runs 5 times from i=0 to i=4. Toggle clock •Operations (arithmetic, logical, etc.)
every 5 time Key Features of RTL Modeling:
2. while Loop
units 1.Uses procedural blocks (always, initial) and
•Runs as long as the condition is true.
•Syntax: 5. Loop Control continuous assignments (assign).
•disable: Terminates a 2.Designed using behavioral or dataflow modeling.
i = 0; 3.Supports sequential (clocked) and
while (i<5) begin loop.
•Example: combinational logic.
$display("i=%d", i); 4.Synthesizable → Can be converted into actual
i = i+1; for(i=0;i<10;i=
hardware.
end i+1) begin Example: RTL for D Flip-Flop
if(i==5) module dff (input clk, d, output reg
3. repeat Loop
disable loop1; q);
•Runs a fixed number of times.
end always @(posedge clk)
•Syntax: q <= d; // Data transferred to
repeat(3) $display("Hello"); q on clock edge
•Prints "Hello" 3 times. endmodule