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Verilog XL Tutorial

This document provides a tutorial on using Verilog XL to simulate Verilog code. It outlines steps to create a basic Verilog file with test stimulus, import the file into the Cadence environment, and run a simulation. The tutorial explains how to run the simulation, view signal waveforms, reset and rerun the simulation. The goal is to familiarize users with basic usage of Verilog XL for simulation through a simple example.

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Vidya Gopala Krishna
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© © All Rights Reserved
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85 views19 pages

Verilog XL Tutorial

This document provides a tutorial on using Verilog XL to simulate Verilog code. It outlines steps to create a basic Verilog file with test stimulus, import the file into the Cadence environment, and run a simulation. The tutorial explains how to run the simulation, view signal waveforms, reset and rerun the simulation. The goal is to familiarize users with basic usage of Verilog XL for simulation through a simple example.

Uploaded by

Vidya Gopala Krishna
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Verilog XL Tutorial

By Greg Edmiston
Scott McClure
August 2004

Tutorial Disclaimer

This tutorial includes one way of


simulating in Verilog XL. This is not
necessarily the best way of simulating,
depending on your requirements. This
tutorial is a simple step-through designed
to familiarize the user with Verilog XL, and
thus is basic in nature. More advance
simulations are not found in this tutorial.

Create Verilog File

Create a text file


with the text shown
here
This code
represents a basic
circuit with delay
and test stimulus
Save as
example.v
Verilog code files
often have a .v
file extension

Enter ICFB

Type who am i
Gives

xhost address

setenv DISPLAY {xhost}


Type icfb & to start Cadence

Import Verilog File in ICFB

Import the
example.v
Verilog file by
choosing File
>> Import >>
Verilog in
ICFB CIW

Importing Verilog File

Verilog In window pops up


Set Target Library Name to
new
Highlight example.v in file
selection box at the top of
the window
Press the Add button on the
Verilog Files to Import line
Click OK at the top of the
Verilog In window

Verify File Import

Open up the
Library Manger
from the CIW and
inspect to ensure
the new library
includes a cell
named
circuit_with_delay

Verify File Import

Open the
Schematic
view of the
circuit_with_
delay from
the Library
Manager and
verify that it
resembles the
screenshot to
the left

Running Verilog XL

Close all windows


except a terminal
From your home
directory type

verilog +gui example.v

Verilog should open


with your example
loaded
Note: example.v has
to be saved in your
home directory for this
command to function

Simulating with Verilog XL


Verilog should open
the SimVision Design
Browser and Console
The stimcrct module
should be displayed
under the simulator
icon

Simulating with Verilog XL


Click on the
stimcrct icon
The circuit
inputs and
outputs should
now be visible
under
Signal/Variable

Simulating with Verilog

With the
stimcrct
highlighted
choose
Select>>Signals

Simulating with Verilog XL

Now that the


signals are
highlighted,
send them to the
logic display by
clicking on the
indicated button

Click Here

Simulating with Verilog XL

Run Button

Click the Play


button to run
the simulation

Simulating with Verilog XL

Since the
simulation has
no initial stop
point the
output will
appear similar
to the window
to the left

Simulating with Verilog XL

To rerun the
simulation it must
first be reset
Reset the
simulation by
choosing
Reinvoke
Simulator from
the simulation
menu

Simulation with Verilog XL

Run Button

Run the
simulation by
pressing the
Run button

Simulation with Verilog XL

Simulation
output
should look
like this

Conclusion
This concludes the Verilog XL Tutorial
This tutorial was derived from the SMU
Cadence Verilog XL Tutorial
http://engr.smu.edu/~mitch/class/3381/veri
log_intro.pdf

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