8051 Instruction Set and
Programming
Programmers model of
8051
As a programmer, the knowledge of
following resources are essential for
programming
Memory
Special Function Registers
Program Status Word
Memory Organization
64KB program memory
64KB external data memory
Data Memory
64 KB of external data memory
128 bytes of internal data memory
21 special function registers
Internal RAM divided as
32 bytes for 4 banks of register R0-R7
16 bytes of direct addressing bits
80 bytes as general purpose RAM
Internal
RAM
partitioning
Mapping
of SFR
Bit
Addresses
of SFR
Operand Types
Supported data types are
Bytes
Short integers
Bits
Bytes and short integer are 8 bit variables
8051 instructions do not facilitate 16 bit
operations
Only MUL instruction produces 16 bit
result stored in register B (higher byte)
and register A (lower byte)
Operand Addressing
Five ways of addressing operands
Register addressing
Direct addressing
Register-indirect addressing
Immediate addressing
Base register plus index register indirect
addressing
Register Addressing
This addressing access 8 registers of
reg bank
4 banks of 8 registers available
Bank selected with RS0, RS1 bit in
PSW
A, B, AB and DPTR are other registers
used
MOV A, R1
R1 and A will have same contents
Register
Addressing
Direct Addressing
Address of the operand specified in the instr.
Operand may be a byte or a bit address
Direct addressing of byte occurs at
Lower 128 bytes of internal data RAM
Special function registers
Direct bit addressing
128 bits subset of internal data RAM (00H to 7FH)
at location 20H 2FH
128 bits subset of SFR address space (80H to FFH)
MOV A, 4EH
Indirect Addressing
Operand address not specified directly
Address of operand is as content of another
register.
Eg. MOV A, @Ri . It implies content of Ri give
address where operand to be picked.
Ri can be R0 or R1 used for accessing 256
locations
This type useful when same set of operations
is performed on different data sets in memory
For accessing external memory 16 bit DPTR
used.
Eg. MOVX A, @DPTR
Immediate Addressing
Operand for the instruction specified
in instruction itself
Eg. ADD A,#0FH
Immediate
Addressing
Base Register Plus Index Register
Indirect Addressing
Indirect instruction used to access
the program memory
Summation of contents of base
address and index address
determines operand address
DPTR or PC acts as base reg
A acts as index reg
MOVC A, @A+DPTR
MOVC A, @A+PC
Data Transfer Instructions
Divided into three classes
General-purpose transfers
Accumulator-specific transfers
Address-object transfers
Only POP and MOV into PSW affect
the flags
General Purpose Transfers
MOV performs bit or byte transfer
from source to destination
PUSH increments SP reg and then
transfer byte from src to stack
element
POP transfers a byte from stack
element pointed by SP to destination
and decrement SP
MOV instruction
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
des.byte, src.byte
A, Rn ; (A)<-(Rn)
A,direct ; MOV A, 55H
A, @Ri
A, #data ; (A)<-#data
Rn, A
Rn, direct
Rn, #data
Cont
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
direct, A
direct, Rn
direct,direct
direct, @Ri
direct,#data
@Ri, A
@Ri, direct
@Ri, #data
Rm, Rn -> not possible
Cont
MOV dest-bit, src-bit
One of the operands must be carry
flag
Other may be any addressable bit
MOV C, bit
MOV bit, C
PUSH direct
SP incremented by one
Contents from direct address
indicated variable copied to internal
RAM
(SP) <- (SP) + 1
((SP)) <- (direct)
POP Direct
Contents of internal RAM pointed by
SP moved to direct address indicated
SP decremented by one
Accumulator Specific
Transfers
XCH exchanges byte source operand
with A
XCHD exchanges low-order nibble of
byte source with low-order nibble of
reg A
MOVX performs a byte move
between external data memory and
reg A
MOVC performs move a byte from
program memory to reg A
XCH A,byte
Source/destination operand can use
register, direct or reg-indirect
addressing
XCH A, Rn ; XCH A, direct ; XCH A,
@Ri
If byte location 208 used, it modifies
flag
XCHD A,@Ri
Ri can be R0 or R1
Lower nibble of ACC exchanged with
internal RAM location lower nibble
MOVX dest-byte,src-byte
Transfer byte between ACC and byte
of external data memory
Ri can be R0 or R1
MOVX A, @Ri ; MOVX @Ri, A
MOVX A, @DPTR ; MOVX @DPTR, A
MOVC A,@A + base-reg
Loads Acc with code byte or constant
from program memory
MOVC A, @A + DPTR ; MOVC A, @A +
PC
Addressable Object Transfer
MOV DPTR, #data loads 16 bit of
immediate data into destination
register pair DPH and DPL
MOV DPTR, #34F3H
Arithmetic Instructions
Addition, subtraction, multiplication,
division, increment, decrement are
basic arithmetic instr.
Only 8 bit unsigned arithmetic
operations directly supported
Overflow flag aids addition and
subtraction operation of unsigned and
signed binary integer
INC & DEC used to modify output port.
Port data is read from latch.
Addition
Four addition operations
ADD performs addition between reg A and
another operand
ADDC does perform addition between reg
A and second operand and adds 1 if C is
set
DA (Decimal Adjust accumulator for BCD
addition)
INC performs addition of source operand
and 1
ADD A, src-byte
ADD adds the src operand with A and
stores result in accumulator A
ADD A, Rn ; ADD A, R7
ADD A, direct ; ADD A, 54H
ADD A, @Ri ; ADD A, @R1
ADD A, #data ; ADD A, #54H
ADDC A, src-byte
Adds src operand, carry flag and
accumulator contents and result
stored back in A
ADDC A, Rn ; ADDC A, R4
ADDC A, direct ; ADDC A, 50H
ADDC A, @Ri ; ADDC A, @R0
ADDC A, #data ; ADDC A, #50H
DA A
Adjusts 8 bit value in accumulator
resulting from addition to valid
packed BCD value
If value of lower nibble in ACC
greater than 9, or if AC flag set, then
6 added to ACC
If value of higher nibble is now
greater than 9, or if CY flag set, then
6 added to higher nibble
INC byte
Increments indicated variable by 1.
No flags affected
INC A; INC Rn; INC direct; INC @Ri
INC DPTR
Increments 16 bit data pointer by 1.
No flags affected
Subtraction
Two subtraction operation
SUBB
DEC
SUBB A, src-byte
Subtracts indicated src operand and
carry flag together from ACC & result
stored in ACC
SUBB A, Rn ; SUBB A, R3
SUBB A, direct ; SUBB A, 45H
SUBB A, @Ri ; SUBB A, @R1
SUBB A, #data ; SUBB A, #45H
DEC byte
Operand is decremented by 1. No
flags affected.
DEC A; DEC Rn; DEC direct; DEC @Ri
Multiplication - MUL AB
Multiplies unsigned 8 bit integers in
ACC and reg B
Result lower order byte stored in ACC
Result higher order byte stored in B
If result greater than 255, overflow
flag is set.
Carry flag is always cleared.
Division DIV AB
Divides unsigned 8 bit integer in ACC
by unsigned 8 bit integer in reg B
Quotient stored in ACC
Reg B receives integer remainder
Carry and overflow flags are cleared
If content of B=00H, values in A & B
after operation undefined and OV =
1, CY =0
Logic instructions Single Operand
Instructions
Seven single operand instructions
CLR, SETB, CPL, RL, RLC, RR, RRC,
SWAP
CPL and CLR can be used to modify
port pins. The value used will be
taken from output data latch.
CLR A
Accumulator is cleared
CLR bit
Bit can be CY flag or directly addressable bit
Indicated bit cleared.No other flag affected.
CLR C ; CLR 45H
SETB bit
Bit can be CY flag or directly addressable bit
Sets indicated bit to 1. No other flag
affected
SETB C ; SETB 45H
CPL A
Each bit of Accumulator is complemented.
CPL bit
Bit can be CY flag or directly addressable
bit
Indicated bit complemented. No other
flag affected.
CPL C ; CPL 45H
RL A (Rotate ACC Left)
8 bits of ACC are rotated 1 bit to the left
Bit 7 rotated to Bit 0. No flags affected
RL A
RLC A (Rotate ACC Left through CY flag)
8 bits of ACC and CY flag are rotated 1
bit to the left
Bit 7 rotated to CY. CY moves to bit 0.
No other flags affected
RLC A
RR A (Rotate ACC right)
8 bits of ACC are rotated 1 bit to the
right
Bit 0 rotated to Bit 7. No flags affected
RR A
RRC A (Rotate ACC Right through CY flag)
8 bits of ACC and CY flag are rotated 1
bit to the right
Bit 0 rotated to CY. CY moves to bit 7.
No other flags affected
RRC A
SWAP A (Swap nibbles within ACC)
Interchanges low and high order nibbles
of A
Equivalent to 4 bit rotation. No flags
affected
SWAP A
Two operand logical
instructions
Three instructions
ANL, ORL, XRL performing bit and
byte operations
They can be used to modify port
pins. The value used will be taken
from output data latch.
ANL dest.byte, src.byte (Logical AND)
Performs bit-wise logical AND between src
and dest operands and stores result in dest
ANL A, Rn ; ANL A, direct ; ANL A, @Ri; ANL
A, #data
ANL direct, A ; ANL direct, #data
ANL C, src.bit (Logical AND for bit variable)
Source bit or its logical complement
ANDed with CY flag and result stored back
at CY
Only direct addressing used. No flags
affected
ANL C, bit ; ANL C, /bit
ORL dest.byte, src.byte (Logical OR)
Performs bit-wise logical OR between src
and dest operands and stores result in dest
ORL A, Rn ; ORL A, direct ; ORL A, @Ri;
ORL A, #data
ORL direct, A ; ORL direct, #data
ORL C, src.bit (Logical OR for bit variable)
Source bit or its logical complement ORed
with CY flag and result stored back at CY
Only direct addressing used. No flags
affected
ORL C, bit ; ORL C, /bit
XRL dest.byte, src.byte (Logical XOR)
Performs bit-wise logical XOR between src
and dest operands and stores result in dest
XRL A, Rn ; XRL A, direct ; XRL A, @Ri; XRL
A, #data
XRL direct, A ; XRL direct, #data
XRL C, src.bit (Logical XOR for bit variable)
Source bit or its logical complement XORed
with CY flag and result stored back at CY
Only direct addressing used. No flags
affected
XRL C, bit ; XRL C, /bit
Control Transfer Instructions
Three classes of control transfer
instructions
Unconditional calls, returns and jumps
Conditional jumps
Interrupts
Cause program execution to be
transferred to non-sequential
location
Unconditional Calls, Returns &
Jumps
ACALL addr11
Unconditionally call subroutine located
at indicated address
2 byte instruction. PC incremented by 2.
Destination address obtained by
successfully concatenating 5 MSbits of
PC + immediate data (11 bits)
No flags affected.
PC value is stored in stack.
LCALL addr16
Unconditionally call subroutine
located at indicated address
3 byte instruction. PC incremented
by 3.
immediate data (16 bits) form
destination address
No flags affected.
PC value is stored in stack.
RET
Pops the return address from stack
and loads into PC.
Program execution continues at
resulting address.
No flags affected.
RETI
Pops the return address from stack
and loads into PC and restores
interrupt logic to accept additional
interrupts.
Program execution continues at
resulting address.
No flags affected.
AJMP addr11
Unconditionally transfer program
execution to indicated address
2 byte instruction. PC incremented
by 2.
Destination address obtained by
successfully concatenating 5 MSbits
of PC + immediate data (11 bits)
LJMP addr16
Unconditionally transfer program
execution to indicated address
3 byte instruction. PC incremented by 3.
immediate data (16 bits) form
destination address
SJMP addr8
Branch destination computed by adding
signed displacement in 2nd byte of
instruction to PC
Range of branch 128 bytes preceding to
127 bytes following PC value
JMP @A + DPTR
8 bit contents of ACC added to 16 bit
data pointer and result loaded to PC
No flags affected
NOP
Execution continues at following
instruction
No registers or flags affected
Conditional Jumps
Transfers execution to indicated
address based on specific condition
Destination will be within 256 byte
range
Branch destination computed by
adding signed relative displacement
to the PC
JB bit, rel (Jump if Bit Set)
If indicated bit 1, jump to address
indicated
Else proceed with next instruction
Bit tested is not affected
JBC bit, rel (Jump if Bit Set and Clear Bit)
If indicated bit 1, jump to address
indicated
Else proceed with next instruction
In either case, clear the designated bit
If it is used to test output pin, value used
is taken from data latch
JC rel (Jump if Carry Set)
If CY flag is 1, jump to address
indicated
Else proceed with next instruction
No flags are affected
JNB bit, rel (Jump if Bit Not Set)
If indicated bit 0, jump to address
indicated
Else proceed with next instruction
designated bit is not affected
JNC rel
If CY flag is 0, jump to address
indicated
Else proceed with next instruction
No flags are affected
JNZ rel (Jump if Accumulator Not Zero)
If any bit of ACC is 1, jump to address
indicated
Else proceed with next instruction
ACC content is not affected
JZ rel
If all bits of ACC is 0, jump to address
indicated
Else proceed with next instruction
No flags are affected
CJNE dest.byte, src.byte, rel
Compares values of first two
operands and branch if values are
not equal
CY = 1, if dest.byte < src.byte
CY = 0, if dest.byte > src.byte
Operands not affected
CJNE A, direct, rel ; CJNE A, #data, rel
CJNE Rn, #data, rel ; CJNE @Ri,
#data,rel
DJNZ byte, rel
Decrements by 1 contents of location
indicated and branches to address
indicated if resulting value is not
zero.
No flags affected.
The decremented byte can be
register or directly addressed byte
DJNZ Rn, rel ; DJNZ direct, rel
Delay By Software
Execution of instructions consumes
machine cycles
For given clock frequency, each
machine cycle takes constant time
MOV R1, #30H 1 MC
INC A 1 MC
Cont
To introduce delay between two instructions,
delay subroutine of known time can be used
Delay subroutine will consist of
Loading a number in Register/Memory
Decrementing it in loop till it become zero
DJNZ takes 2 MC for execution
DEL1S: MOV R1,#07 ;
RPT1: MOV R2,#0FFH
RPT2: MOV R3,#0FFH
L1: DJNZ R3, L1
DJNZ R2, RPT2
DJNZ R1, RPT1
RET
I/O Port Programming
Ports P0 to P3 are bidirectional
Ports are configured as output on
reset
To configure as input, 1 must be
written to port line
SETB P0.4 ; configure Port 0 pin 4 as
i/p
MOV A, #0FFH
MOV P0, A ; configure Port 0 as i/p
Programming of
Timers/Counters
1. Selection of Timer/Counter, mode and
configuration
2. Determine and load the initial count as preset
value
3. Start Timer/Counters
4. When count value overflows from FFFFH to
0000H, then TF0 and TF1 becomes 1
5. For continuous operation of timer/counter
Timer/Counter must be stopped
Timer Interrupt flag cleared
Preset value loaded in Timer register and start
timer again
TCON Timer Control
Upper four bits used to store TF & TR
bits of both timer 0 & 1
TF1 Timer 1 Overflow flag
TR1 Timer 1 Run Control Bit
TF0 Timer 0 Overflow flag
TR0 Timer 0 Run Control Bit
Determination of TF0/TF1
overflow
1. Checking TF0, TF1 in continuous loop
L1: JNB TCON.5, L1 ; JNB TF0,L1
CLR TCON.4
CLR TCON.5
Load preset value
Start Timer, Branch to checking for overflow
2. By using ISR
Stop Timer/Counter
Clear flag TF0
Load preset value
Restart Timer/Counter
Return
Serial I/O Transmission to PC
a) Determine TMOD value and load Timer 1 in
mode 2 (auto reload mode)
b) Based on baud rate, find TH1 reload value
and load value in TH1
c) Determine SCON reg value and load
PC uses 1 start bit, 8 data bit, 1 stop bit
Mode 1 selected
d) Set TR1 bit to start Timer 1
e) Reset TI flag by making SCON.1 = 0
f) Byte to be transmitted loaded to SBUF
g) TI bit monitored. If TI = 1, byte transferred.
h) Go to step e for next byte transmission
SCON Serial Control
Register
Controls operation of serial port
Serial Mode
SM0
SM1
Mode
Descriptio
n
Baud rate
Shift
Register
1/12th of osc
8 bit UART
Variable
9 bit UART
1/64 or 1/32
based on
SMOD = 0/
1
9 bit UART
Variable
Baud Rate Chart
Serial I/O Reception from PC
a) Determine TMOD value and load Timer 1 in
mode 2 (auto reload mode)
b) Based on baud rate, find TH1 reload value and
load value in TH1
c) Determine SCON reg value and load
PC uses 1 start bit, 8 data bit, 1 stop bit
Mode 1 selected
Make REN = 1
d) Set TR1 bit to start Timer 1
e) Reset RI flag by making SCON.0 = 0
f) RI bit monitored. If RI = 1, byte received.
g) Store SBUF in memory/register
Write a program for the 8051 to
transfer YES serially at 9600 baud,
8-bit data, 1 stop bit, do this
continuously
Write a program for the 8051 to
receive bytes of data serially, and
put them in P1, set the baud rate at
4800, 8-bit data, and 1 stop bit
Interrupt Programming
Interrupts may be external interrupt,
Timer/ Counter Interrupt, Serial Port
Interrupt
1. Enable Interrupt using IE SFR
2. If used, Program external interrupts
as edge triggered or level triggered
using TCON reg
3. Program Interrupt Priority using IP
reg
4. ISR written to take required action
IE Interrupt Enable
Register
IP Interrupt Priority
register
Create a square wave that has a high
portion of 1085 us and a low portion
of 15 us. Assume XTAL=11.0592MHz.
Use timer 1.
Serial I/O Interrupt
Serial I/O interrupt caused when
Transmission of a byte completed
Reception of a byte is completed
Design a counter to count pulses received at T0
and determine the no. of pulses received in 1
minute.
Write a program to transmit 10 bytes of data
serially to PC at 2400 baud by 8051 with
11.0592 frequency, 12 clock machine cycle.
Write a program to receive 20 bytes of data
serially from PC at 9600 baud by 8051 with
11.0592 frequency, 12 clock machine cycle.
Generate a pulse train of 1 KHz at P1.0 using
Timer 0 interrupt of 8051 using 11.0592 MHz
clock frequency crystal
Write a program to send 10 bytes of data stored
in internal data RAM (IDR) location 040H onward
serially in mode 1 to PC at baud rate 4800 with
11.0592 MHz crystal.
