HDI Design Rules, Vias &

Structures for BGA Routing

by Happy Holden
PCB INDUSTRY TECHNOLOGIST

PART 1
 AGENDA

• What’s Driving Density?

•Components
•HDI Metrics
•Through-Hole Vs. HDI
•Design Rules and Structures
•Using Blind / Buried Vias
•Via-In-Pad
•HDI Channel Routing
•BGA Design Guidelines
•Design Related Capacitive Loading

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Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
 What's Driving Density?

Higher Silicon Integration-More I/Os

Finer Pitch

Closer Spacing (time-of-flight)

More Discrete (per unit area)

Smaller and Thinner for Lead-Free Assy

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Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
 Dielectric Materials IVH Formation Metalization of Microvia Product Name
1
Photosensitive Liquid Diel. 1 PhotoVia 1 Electroless Cu 1 DV Multi-AD
IBSS-AAP/10
1
2 1 SLC
Photosensitive Dry-Film Diel. 2 2 DVMulti-PID
3 HDI
4 MIKO-BU
5 CLLAVIS
Polyimide Flex Circuit 3
3
3 4 5
Laser Electroplated Cu 6
4 5 HITAVIA
7
Dycostrate
4 6 6 4
Thermal Cure Dry Film 4 5 SSP
7
5
Fact-EV
5 7 10
NA PPBU (HITAVIA
Drill
Thermal Cure Liquid 7
NA Laser-Via
6
8
8 3 OrmeLink
Plasma 6 ALIVH
7
Resin Coated Copper (RCC) Conductive Paste MSF
7
PALUP
9 8
10 6 9 VIL
9 Screen Print Bump Connection 9 Bbit
FR-4 or Aramid Prepreg
8

Photo Lith & Etch Sheet Cu Bumps NMBI

Thermoplastics Tool Foil Conductive Paste Imprinted Circuits 6

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HDI_Design_Rules_Structures_Part_1.PPT
 HDI PLATFORMS
Platform Applications Construction

Miniaturization This technology is the leading edge in

HDI technlogy. The dense designs
offer small form factors and very
dense features including micro BGA or
flip chip footprints.

Packaging This technology is used for flip chip

Substrate or wire bondable substrates. Micro
vias offer the possibility to escape
very dense flip chip areas. Even 2+2
constructions may be needed.

High This technology is used for high layer

Performance boards with high I/O or small pitch
components. A buried board is not
always necessary. The microvias are
used to form the escape area of dense
components (high I/O, micro BGA).
The HDI dielectric can be RCF or
prepreg.

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HDI_Design_Rules_Structures_Part_1.PPT
 Components

SMT Land Pitch (high I/O, fine-pitch)

Ceramic Column Grid Arrays (CCGA)
Ceramic Ball Grid Arrays (CBGA)
Micro Ball Grid Array (uBGA)
Flip Chip on board
Discrete BGAs
Coming: Land Grid Arrays

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HDI_Design_Rules_Structures_Part_1.PPT
Consider: These new Components
Micro Ball Grid Array (18.0mm x Ceramic column grid array
18.0mm) - 384 balls, (52.5mm x 52.5mm) -
0.80 mm pitch 2577 column, 1.00 mm pitch

Star Ball Grid Array

(15.0mm x 15.0mm) - 257 balls,
0.80 mm pitch

Signal: 1768 I/O

Ground: 397 I/O
Chip Scale Pkg. PWR-V1: 204 I/O
(14.0 mm x 14.0 mm) PWR-V2: 52 I/O
PWR-V3: 52 I/O
393 I/O 0.50 mm pitch
PWR-V4: 52 I/O
PWR-V5: 52 I/O

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HDI_Design_Rules_Structures_Part_1.PPT
 Bigger FPGA are Coming !
39x39 rows, 12 deep, 1296 I/O @ 1mm (1417 total)
Structured Standard Cell ASIC
34x34 rows, 1153 I/O @ 1mm

New Actel, Infineon, Xilinx & Altera FPGAs have 256, 348, 396, 456,
564, 692, 804, 860, 996, 1020, 1164, 1296, 1508, 1696, & 1704 I/Os.

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Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
What is Microvia technology ?

Microvias are plated holes with diameters = or below 150µm

Main techniques to fabricate microvias :

Laser technique - UV Laser
Laser technique - CO2 Laser
< 150µ
Plasma etch - DYCOstrate
Mechanical drilling (for samples only)

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HDI_Design_Rules_Structures_Part_1.PPT
HDI Density Metrics for Design

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HDI_Design_Rules_Structures_Part_1.PPT
 HDI Metrics for Design
Boards

Layout: Layout Efficiency

Routability Predictor Components Assembly
Inches per square inch per layer
Components: Ave. Pins per Part
Component Pitch

Boards: Inches per square inch (cm / sq. cm)

Number of traces per square inch (sq cm)

Assembly: Ave. Parts per square inch (sq cm)

Ave. Pins per square inch (sq cm)

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HDI_Design_Rules_Structures_Part_1.PPT
PWB & Interposer Technology Roadmap
vs Assembly
Std FR4 SBU(+1 or +2) SBU(+3)
600
Pad L/S Via Land
500
Feature Size (um)

400

300

200

100

0
1.27 1 0.8 0.64 0.5 0.25 0.2 0.1 0.08
Pitch (mm)
BGA CSP DCA

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HDI_Design_Rules_Structures_Part_1.PPT
High Density Interconnection
Density Enabler - Microvia Board

Internal layers are freed up for routing.

Via Starvation Plane layers no longer exhibit the
“Swiss Cheese” effect.

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HDI_Design_Rules_Structures_Part_1.PPT
 The Thru-Hole Wiring Barrier (Density)
Assuming 3 nodes/net @ 1.0mm & 1.27mm BGAs

Assume:
A SMT pad,
trace and via
per end of net

1.0 inch
1.0 inch

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HDI_Design_Rules_Structures_Part_1.PPT
TH Multilayer Diminishing Returns

When using 1.27mm and 1.0mm BGAs

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 HDI Wiring Density

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HDI_Design_Rules_Structures_Part_1.PPT
Common Microvia Structures
1+N+1
cost: 30% to < 8% as layers go up
Core Prepreg HDI Dielectric HDI Via Fill

IPC Type I cost: 1.00 IPC Type I-Variable Depth

cost: 1.14x IPC Type II-Stacked vias

IPC Type II
2+N+2

IPC Type III cost: 1.71x IPC Type III-Stacked vias

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HDI_Design_Rules_Structures_Part_1.PPT
HDI - Price/Density Comparison

RCI: Rel price to 8L

DEN: Ave pins/sq.inch
FR-4 (low Dk and Dj materials results in MUCH more cost savings)

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Design rules and structures

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21
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HDI Materials

IPC-4104

Resin Coated
Foils
Laminates
Films
Liquids

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Material Options by Reinforcement

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HDI_Design_Rules_Structures_Part_1.PPT
IPC-2226 HDI Constructions

Type I
Type V

Type II
Type VI

Type III

Type IV

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HDI_Design_Rules_Structures_Part_1.PPT
Design Guidelines – IPC 2226

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HDI_Design_Rules_Structures_Part_1.PPT
Thermal Management

IPC-2221 Current
carying capacity
chart is being
replaced by IPC-
2152

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HDI_Design_Rules_Structures_Part_1.PPT
 Thermal Management

New Data on
current
carrying
vs.PCB
thickness for
IPC-2152

Material thermal
conductivity impact

Composite
thermal
conductivity

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HDI_Design_Rules_Structures_Part_1.PPT
Typical Laser Blind Vias

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HDI_Design_Rules_Structures_Part_1.PPT
Conventional Laser Drilled hole Geometry

Microvia 12 Buried via (epoxy filled)

Microvia 13 Drilled PTH

HDI Sequential HDI

BU Layers (+2) Dielectric
Layers

4 Layer
MLB
Core
Laser Drilled Microvia
L1 - L2

HDI Sequential
BU Layers (+2)

2+4+2 HDI Substrate

Aspect ratio on Microvia’s approximately 0.5:1max.
Laser Drilled Microvia
Microvia 1 3 require larger hole diameter L1 - L2 & L3

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HDI_Design_Rules_Structures_Part_1.PPT
Factors Impacting Laser Drilling Time &
Costs

• Copper foil type (new laser coatings)

• Copper foil thickness
• Dielectric thickness
• Hole diameter
• Dielectric composition
– Non-reinforced resin (RCC)
– Non-woven reinforcement (Thermont ®)
– Woven (106, 1080, 1086 glass)
• System Optimization = increases velocity and power

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HDI_Design_Rules_Structures_Part_1.PPT
 Laser Drillable Prepregs
1080 VS 1086 LD
1080

1086 LD

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HDI_Design_Rules_Structures_Part_1.PPT
Comparison Of Via Formation
Productivity (vias/sec)
100000
Chemical Etching

Plasma Etching
10000
Eximer Laser Drilling Photo Polymer Process

1000

UV-YAG Laser Drilling CO2 Laser Drilling

100

NC Drilling
10
0 50 100 150 200 250 300 350

Via Diameter (um)

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HDI_Design_Rules_Structures_Part_1.PPT
Using Blind and Buried
Vias For BGA Routings

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HDI_Design_Rules_Structures_Part_1.PPT
Blind Via-in-Pad Changes

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HDI_Design_Rules_Structures_Part_1.PPT
 Construction Stackup

Via Structure
Design Rules
Via-in-Pad
Breakout Patterns
Channel Structures

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HDI_Design_Rules_Structures_Part_1.PPT
Surface 3 Layers
TYPE I TYPE II TYPE III
SMT/GND SMT/GND SMT/GND
PWR PWR PWR
SIG SIG SIG
SMT/SIG SMT/SIG
GND SMT/GND
SIG
SIG/PWR
SIG
PWR/GND
SMT/GND PWR/GND SMT/SIG
SIG
SIG
SIG SMT/SIG
PWR/GND
SMT/GND SIG/GND SMT/GND
SIG SIG/PWR/GND SIG
PWR
PWR/GND
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HDI_Design_Rules_Structures_Part_1.PPT
Via-in-Pad - The Ideal LF Solder Joint

Chip Scale BGA Package with Microvia in Pad

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HDI_Design_Rules_Structures_Part_1.PPT
Via-in-Pad - The Ideal LF Solder Joint

Chip Scale BGA Package with Microvia in Pad

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Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
HDI Constructions
SIGNAL (PWR) PWR (sig) SIGNAL GND

to this
1. SMT/GND
2. Sig_1
3. PWR (Sig_2)
4. Sig_2 (PWR)
5. .....

or this SIGNAL (PWR) SIGNAL PWR GND

1. SMT/GND
2. PWR D.Cap
3. Sig_1
4. Sig_2
5. GND
6. .....

or this
1. SMT/GND SIGNAL - PWR PWR - SIGNAL SIGNAL- PWR GND
2. PWR / Sig_1 D.Cap
3. PWR / Sig_2 D.Cap
4. GND D.Cap

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COPYRIGHT HHolden 2006 Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
 Various PWRs Closer to the Surface
Single PWR Plane

Split PWR Plane

SMT/GND
PWR
SIG L-1
L-2

Mesh PWR Plane

tied to N-1 Mesh
PWR Plane
L-(N-1)
L-(N)

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HDI_Design_Rules_Structures_Part_1.PPT
Via-In-Pad and Routing

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Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
 HDI MicroVia Structures (VIP)

200 m Land

250 m Land

300 m Land

a. 0.50mm pitch b. 0.65mm pitch c. 0.8mm pitch

Via-in-pad allows plane fill but with or without the assembly via fill
need
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HDI_Design_Rules_Structures_Part_1.PPT
HDI MicroVia Structures (NVIP)

300 m bv 300 m bv

350 m bv 350 m bv

400 m bv 400 m bv
a. 0.8mm b. 1.0mm
pitchLand
350 m SMT pitch
450 m SMT Land
Near via-in-pad allows plane fill but without the assembly via fill need

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HDI_Design_Rules_Structures_Part_1.PPT
END OF PART 1
NVIP Example

720 I/O@1.0 mm pitch BGA

Ave leads per part=6.5
Parts per sq. inch=26.4
Leads per sq. inch=171.3

SMT pad=.020"
bl via =.005"
bl v pad =.013"
bu via =.010"
bu v pad=.022"

layer 1
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Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
NVIP Example
720 I/O@1.0 mm pitch BGA

SMT pad=.020"
bl via =.005"
bl v pad =.013"
bu via =.010"
bu v pad=.022"

layer 2
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Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
NVIP Example
720 I/O@1.0 mm pitch BGA

SMT pad=.020"
bl via =.005"
bl v pad =.013"
bu via =.010"
bu v pad=.022"

layer 16
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Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
HDI BGA Routing - Basics

(Near) Via in pad techniques

µ vias are best placed NOT in

the centre of the BGA pads,
but centered on the Target
Land.

Inset Partial Offset-center

nvip vip vip

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Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
HDI MicroVia Structures
Adjacent vias
(dog-bone)

Inset vias
Solder-Mask Tol

Partial Via-In-Pad
Offset Via-in-Pad
Via-In-Pad
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Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
Via-in-Pad
Microvia in pad
1.0 mm BGA

Two track
signal routing

Interstitial
Microvias

Thermount Dielectric

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HDI_Design_Rules_Structures_Part_1.PPT
Via-in-Pad
39 x 39 1.0 mm BGA

Layer 1 Signal Routing

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Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
HDI Routing with Blind Vias
2 techniques: Perimeter and Channel
Perimeter Channel

Perimeter uses bands of blind Channel uses rows of blind

vias around the perimeter. vias working inwards to create
Works best on small BGAs I/L channels for routing. Works
and low I/O. best on large BGAs and high
I/O.
52
Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
 Via-in-Pad Next layer routing

Plated
via
volume
is <1%
of solder
volume

0.5mm GND connection to

COPYRIGHT HHolden 2006
surface ground-pour

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Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
 HDI MicroVia Structures (SMT Chip)

Edge of via hole is .001" away 0402

from device body outline
0306

0603
Via is tangential to inside edge
of device pad farthest away
0612
from device center
2-microvias in parallel cancels the mutual-self
inductance
COPYRIGHT HHolden 2006
54
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HDI_Design_Rules_Structures_Part_1.PPT
 Filled MicroVias

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HDI_Design_Rules_Structures_Part_1.PPT
"Filled" Microvia Plating

fill &
plate

Panel_plate & pattern_plate

(PPR)

tape barre
fill & r l
plate Rohm & Haas MicroFill

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Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
"Filled" Microvia Plating
Panel plate & PP/R pattern plate with 'surface
ground fill' design

COSTS

No Charge

Superior reliability,
ICT and assembly
panel plate Cu strike

PP/R: pulse plating with periodic reversal

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Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
"Filled" Microvia Plating

Additional via fill, metalization

and cap-plating, alternate is
conductive paste but that costs
more.
COSTS
Additional 7 to 15%

commonly available in Asia

fill & plate

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Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
"Filled" Microvia Plating

Rohm & Haas MicroFill

additional plating process

COSTS
taper
Additional 1% to 10%

But no through holes open from the

surface or they will close down with a
'dogbone' deposit.(great for 100%
SMT cell phones).
barrel not commonly available yet!
Requires new plating equipment

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HDI_Design_Rules_Structures_Part_1.PPT
Stacked Copper Filled MicroVias

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HDI_Design_Rules_Structures_Part_1.PPT
Stacked Copper Filled MicroVias

New lay up technology

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HDI_Design_Rules_Structures_Part_1.PPT
 Preferred Design Guidelines

Stacked copper filled µ-Vias

RCC 60+/-15µm FR4 106 45+/-15µm FR4 1080/1086 65+/-
18µm

Min. 250µm Min. 250µm Min. 250µm

1 1 1
2 2 2

3 3 3

Min. 275µm Min. 275µm Min. 300µm

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Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
Stacked Microvia Design

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Source: DDI Presentation
Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
 Stacked Microvia Design - Buried Via
0.5 mm 1:2 Microvia Full offset "Dog Bone"
Layer 1
Layer 2

Layer 3

Layer 4

"Dog Bone"
hole to layer 4

Source: DDI Presentation

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Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
BGA Routing - HDI Basics
New Lead-Free BGA SMT Lands
BGA land dimensions
1) 1.0 mm Ball Grid Array-
275-350m Pad size

2) 0.8 mm Ball Grid Array-

250-300µm Pad size

3) 0.65 mm Ball Grid Array-

200-250µm Pad size

4) 0.5 mm Ball Grid Array-

175-200µm Pad size

5) 0.4 mm Ball Grid Array-

150-175mm Pad size
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Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
 1.0 mm BGA
HDI Design Guidelines

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HDI_Design_Rules_Structures_Part_1.PPT
 Via-in-Pad Type I Routing
TH &HDI blind vias 1 mm BGA

.0194” (485 µm) via pad

.010” (250 µm) drill
.0046” (115 µm)Trace &
space
6 track routing

Internal Layers
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Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
 1.0 mm HDI Routing
Ball pad Laser drilledhole Buried via (2:N-1)

One track
Route
Between
Capture pad
and buried
via

300mm
750mm anti-pad
capture
pad

PTH
250mm drill
500mm pad
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Source: DDI Presentation
Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
 0.8 mm BGA
Design Guidelines

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HDI_Design_Rules_Structures_Part_1.PPT
Via-in-Pad - 0.8 mm
Through-Hole (12L) vs HDI VIP (4L)

0.8mm GND connection to PTH

GND connection to surface ground-pour

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HDI_Design_Rules_Structures_Part_1.PPT
 1993 VIP Competition
NEXT-GENERATION HDI Power
Distribution
PWR Mesh (no PWR planes)
RF Coplanar PWR on Sig-L 2/3

Top (1)

12-Layer TH
4-Layer VIP HDI
Bot (12)

Conventional PWR / GND Bot (4)

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HDI_Design_Rules_Structures_Part_1.PPT
 Blind Vias Create I/L Channels
HDI blind vias
0.8 mm (31.5 mils) Pitch Effective 1.6 mm pitch
with through holes on drilled holes !
Subsequent Signal Layers 4 channels-5 mil lines,5 mil spaces
only 2 row escaped 5 channels-4 mil lines, 4 mil spaces
3.5 mil line and 4 mil space
5 mil line, 5 mil space

31.5 mils

8 mils 20 mils
8 mils 20 mils

3.5 mil line and 4 mil space

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Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
 Via-in-Pad Type I Routing 0.8 mm BGA
TH & HDI blind vias 0.0315"

.020” (500 µm) via pad

.010” (250 µm) drill
.004” (100 µm) trace & space
5 track routing

Internal Layers
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Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
 Via-in-Pad Type I Routing
0.8 mm BGA
HDI blind vias: INSET MicroVias (NVIP)
0.0315"
.016" (400 µm) SMT land

.014” (350 µm) via pad

.006” (150 µm) Laser drill

.004” (100 µm) trace

.0055" (140 µm) space

.003" (75 µm) S/M Cir.

Surface Layers
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Source: DDI Presentation
Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
 Via-in-Pad Type I Routing 0.8 mm BGA
HDI blind vias 0.0315"

Internal Layers
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Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
 BGA Routing–Basics Design Rules
 0.8 mm BGA:
 Pad size ø 300µm 90µm 100µm 100µm 90µm

 Line: 100µm
Soldermask Etch profile 10µm
Etchprofile10µm

100µm

410 µm
300µm
320µm
Pad diameter Top
Paddiameter
Bottom

Soldermask Registration +/- 45

Pad µm
Soldermask Registration : Line
1/4 * (800 - 320 - 100 - 100 - 100)µm
= 45 µm ( +/- )
800 µm

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HDI_Design_Rules_Structures_Part_1.PPT
Routing Channel Density vs. Via Structure

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HDI_Design_Rules_Structures_Part_1.PPT
0.8 mm HDI Routing

Ball pad
12 mil capture pad
3 Track
routing 2 Track routing layer 1
layer 2

Plated through holes

10 mil drill, 20 mil pad

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Source: DDI Presentation
Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
 0.8 mm HDI Routing
10 mil drill
2 Track routing
layer 2 20 mil pad
0.8 mm
0.8mm pitch
Ball pad

2 - 4 mil max
2 - 6 mil max
High density
routing layer

79
Source: DDI Presentation
Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
 0.8 mm HDI Routing- TH & Buried
10 mil drill
Buried via 8 mil
20 mil pad
drill 16 mil land 0.8 mm
0.8mm pitch
Ball pad
No Via

2 - 6 mil max
No max
One track between
PTHs

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Source: DDI Presentation
Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
0.8 mm HDI Routing (2BU) & Buried10 mil drill
Buried via Ball pad 20 mil pad
10 mil drill 0.8 mm
0.8mm pitch
20 mil land

2 - 6 mil max
2 - 4 mil max
One track between
PTHs

81
Source: DDI Presentation
Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
0.8 mm HDI Routing (2BU) & Buried
10 mil drill
Buried via Plane
0.8 mm 20 mil pad
10 mil drill connection 0.8mm pitch
20 mil land

2 - 6 mil max
2 - 4 mil max
One track between
PTHs

Source: DDI Presentation

82
Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
0.8 mm HDI Routing (surface PWR & GND)
Signal Pad Ground Pad Power Pad

Layer 1

Layer 2

0.002" - 0.004"
Microvia layer 1:2

83 Source: DDI Presentation

Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
Using HDI For Power & Ground

84
Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
BGA Routing - Basics
Routing techniques for further layer reduction:
Channel routing technique:
Identify NC Pins that do not need a dog bone, share
power/gnd to additional pin fanouts, and use µ vias in
order to create additional routing channels
Neck down technique:
Use neck down and reduced clearance in order to get
two tracks between
Non functional pads removal:
Remove unused via pads on inner layers in order to
get more tracks between

85
Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
NVIP Example SMT pad=.014"
bl via =.005"
bl v pad =.013"
bu via =.010"
3- 160 I/O@0.8 mm pitch BGA bu v pad=.022"

back-to-back
layer 1

86
Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
 NVIP Example
SMT pad=.014"
3- 160 I/O@0.8 mm pitch BGA bl via =.005"
back-to-back bl v pad =.013"
bu via =.010"
bu v pad=.022"

layer 16

87
COPYRIGHT HHolden 2006 Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
 NVIP Example
3- 160 I/O@0.8 mm pitch BGA
showing the buried vias
layer 1

88
COPYRIGHT HHolden 2006 Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
 0.65 mm BGA
Design Guidelines

89
COPYRIGHT HHolden 2006 Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
 BGA Routing – Basics Design rules
 0.65mm BGA:
 Pad size ø 300µm 115µm 100µm 115µm

 Line.: 100µm Etchprofile 10µm Etchprofile10µm

Soldermask

377,5µm
300µm
320µm
Paddiameter Top
Paddiameter
Bottom

Soldermask Registration:
Pad +/- 57,5µm
Soldermask Registration :
Line
1/4 * (650 - 320 – 100 )µm
650 µm
= 57,5µm ( +/- )

90
Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
 BGA Routing – Basics Design Rules
 0.65mm BGA:
 Pad size ø 250µm 77,5µm 75µm 75µm 77,5µm
 Line.: 65-75µm
75µm
Etchprofile 10µm
Etchprofile10µm
Soldermask

82,5 µm

310,75µm 65µm 65µm

85µm
250µm
270µm
Paddiameter Top
Paddiameter
Bottom

82,5 µm

Pad Soldermask Registration:

+/- 41,25µm
Soldermask Registration :
Line
1/4 * (650 - 270 – 65 –85 – 65 )µm
= 41,25µm ( +/- )
650 µm

91
Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
Support for Fine-Pitch (0.65mm)
296 Pin, 0.65 mm pitch BGA
THRU-HOLE (it won't work)

1:Top 2:Gnd 3:SIG1

4:SIG2 5:PWR 6:BOT

TH Via dia: .004"
O/L Via pad: .017"
I/L Via pad: .017"
Pwr/Gnd opening: .021"
Traces: .003"
Spacing: .0035"

92
Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
 Support for Fine-Pitch (0.65mm)
296 Pin, 0.65 mm pitch BGA

Conventiona 2:Gnd
1:Top 3:SIG1
l Blind Vias
w/Thru holes

5:PWR 6:BOT
4:SIG2
IPC Type I stackup, 1 + N + 1 Via dia: .010" 3LBV dia: .012"
variable depth vias O/L Via pad: .018" 3LBV pad: .020"
I/L Via pad: .020" Traces: .004"
BV dia: .006" Spacing: .004"
BV pad: .014"

93
Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
 Support for Fine-Pitch (0.65mm)
Conventional Blind Vias w/Thru holes (Type I)
296 Pin, 0.65 mm pitch BGA

1:Top/GND 2:SIG1 3:SIG2

4:PWR 5:SIG3 6:BOT/GND

IPC Type I stackup, 1 + N + 1
variable depth vias Via dia: .010"
3LBV dia: .012"
O/L Via pad: .018"
3LBV pad: .020"
I/L Via pad: .020"
Traces: .004"
BV dia: .006"
Spacing: .004"
BV pad: .014"

94
Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
 Support for Fine-Pitch (0.65mm)
296 Pin, 0.65 mm pitch BGA

1:Top/GND 2:SIG1 3:SIG2

Conventiona
l Blind Vias
w/Stacked
Vias
4:PWR 5:SIG3 6:BOT/GND
Buried via
IPC Type II stackup, 1 + N + 1 w/ 3LBV dia: .012"
stacked vias
dia: .010"
I/L Via pad: .020" 3LBV pad: .020"
BV dia: .006" Traces: .004"
BV pad: .014" Spacing: .004"

95
Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
 0.50 mm BGA
Design Guidelines

96
Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
 BGA Routing – Basics Design rules
0.5mm BGA: 80 µm
Solder mask dam
Pad size ø 300 µm
Line.: No line Etchprofile 10µm Etchprofile10µm
Soldermask

300µm
320µm
Paddiameter Top
370µm Paddiameter
Bottom

Soldermask Registration:
Soldermask Registration : Pad +/- 50µm
1/4 * (500 - 320 – 80)µm
= 50µm ( +/- )
500 µm

97
Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
 BGA Routing – Basics Design rules
0.5mm BGA
Pad size ø 250 µm 77,5µm 75µm 77,5µm

Line.: 65-75µm
Soldermask
Etchprofile 10µm
Etchprofile10µm

65µm
250µm
347,5µm 270µm
Paddiameter Top
Paddiameter
Bottom

82,5µm

Soldermask Registration: +/-

Soldermask Registration :
Pad Line 41,25µm
1/4 * (500 - 270 - 65)µm
= 41,25µm ( +/- )
500µm

98
Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
 BGA Routing – Design rules
0.5 mm BGA
HDI blind vias: INSET MicroVias (NVIP) 0.0197"

.010" (250 µm) SMT land

.010” (250 µm) via pad

.004” (100 µm) Laser drill

.0039” (100 µm) pad-pad

space

.002" (50 µm) S/M Cir.

Surface Layers
99
Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
0.5 mm BGA Blind To Buried Via

100
Source: DDI Presentation
Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
BGA Routing – Basics Design rules
0.5 mm Pitch BGA
(0.0197")

101 Source: DDI Presentation

Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
BGA Routing – 0.5 mm Design rules

102
Source: DDI Presentation
Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT
103
Copyright ©1999-2006, Mentor Graphics.
HDI_Design_Rules_Structures_Part_1.PPT