Module-3:

CPU Organization
ODD 2025

Computer Organization and Architecture

(15B11CI313)
 General-purpose computer

An instruction code is a group of bits that instruct the

computer to perform a specific operation. It is usually
divided into parts.
Instructions are stored in one section of memory and
data in another.
The memory has 4096 words
4096 = 212, so it takes 12 bits to specify an Figure 5 General purpose computer [1]
Address to select a word in memory
Each word is 16 bits long
16-bit memory word, we have available four bits for the operation code specify
one out of 16 possible operations, and 12 bits to specify address of an operand.
Computers that have a single-processor register called accumulator and label it AC.
The operation is performed with the memory operand and the content of AC.
 PROCESSOR REGISTERS
The significance of a general purpose register is that it can be referred to in
instructions
e.g. load AC with the contents of a specific memory location; store the contents of AC into a
specified memory location

Often a processor will need a scratch register to store intermediate results or

other temporary data; Here, it is known as the Temporary Register (TR)

The Basic Computer uses a very simple model of input/output (I/O) operations
Input devices are considered to send 8 bits of character data to the processor
The processor can send 8 bits of character data to output devices

The Input Register (INPR) holds an 8 bit character gotten from an input device
The Output Register (OUTR) holds an 8 bit character to be send to an output
device
 BASIC COMPUTER REGISTERS
Registers in the Basic Computer

11 0
PC
Memory
11 0
4096 x 16
AR
15 0
IR CPU
15 0 15 0
TR DR
7 0 7 0 15 0
OUTR INPR AC

List of BC Registers
DR 16 Data Register Holds memory operand
AR 12 Address Register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction Register Holds instruction code
PC 12 Program Counter Holds address of instruction
TR 16 Temporary Register Holds temporary data
INPR 8 Input Register Holds input character
OUTR 8 Output Register Holds output character
Figure 7 Basic computer registers [1]
GENERAL REGISTER ORGANIZATION
Clock Input

R1
R2
R3
R4
R5
R6
R7
Load
(7 lines)
SELA { MUX MUX } SELB

3x8 A bus B bus

decoder

SELD
OPR ALU

Output
Figure 8. General Register Organization [1]
 INSTRUCTIONS

Program
A sequence of (machine) instructions
(Machine) Instruction
A group of bits that tell the computer to perform a specific operation (a sequence of
micro-operation)

The instructions of a program, along with any needed data are stored in
memory Instruction Fetch

The CPU reads the next instruction from memory

It is then placed in an Instruction Register (IR) Instruction Decode

Control circuitry in control unit then translates the instruction into the
sequence of microoperations necessary to implement it
 INSTRUCTION FORMAT
A computer instruction is often divided into two parts
An opcode (Operation Code) that specifies the operation for that instruction
An address that specifies the registers and/or locations in memory to use for that operation
In the Basic Computer, since the memory contains 4096 (= 212) words, we
needs 12 bit to specify which memory address this instruction will use

The most significant bit, i.e., bit #15 of the instruction specifies the addressing
mode (0: direct addressing, 1: indirect addressing)

Since the words in memory (and overall instructions that reside there) are 16
bits long, that leaves 16 - (12+1)= 3 bits for the instruction’s opcode

Figure 11. Instruction format [1]

 ADDRESSING MODES
The address field of an instruction can represent either
Direct address: the address in memory of the data to use (the address of the operand), or
Indirect address: the address in memory of the address in memory of the data to use

Figure 12. Addressing modes [1]

The indirect address instruction needs two references to memory to fetch an operand. The first
reference is needed to read the address of the operand; the second is for the operand itself.
Effective Address (EA)
The address, that can be used directly (without modification) to access an operand for a
computation-type instruction, Or, as the target address for a branch-type instruction
Basic Computer Instruction Format

Figure 13. Basic computer instructions [1]

BASIC COMPUTER INSTRUCTIONS

Figure 14. Basic computer instructions [1]

COMMON BUS SYSTEM

Figure 17. Common bus system [1]

 COMMON BUS SYSTEM

Three control lines, S2, S1, and S0 control which register the bus selects
as its input
S2 S1 S0 Register
0 0 0 x
0 0 1 AR
0 1 0 PC
0 1 1 DR
1 0 0 AC
1 0 1 IR
1 1 0 TR
1 1 1 Memory

Either one of the registers will have its load signal activated, or the
memory will have its read signal activated
Will determine where the data from the bus gets loaded
The 12-bit registers, AR and PC, have 0’s loaded onto the bus in the high
order 4 bit positions
When the 8-bit register OUTR is loaded from the bus, the data comes
from the low order 8 bits on the bus
 Fetch-Decode-Execute Cycle
During the fetch part, the CPU fetches the next instruction from the
address contained in the Program Counter and places the instruction
in the Instruction Register.
When a program starts, the program counter contains 0, so the
instruction at address 0 is fetched.

As soon as an instruction is fetched, the CPU adds 1 word to the

contents of the Program Counter, so that it will contain the address
of the next sequential instruction.
 Fetch-Decode-Execute Cycle
The decode unit within the CPU decrypts the instruction in the
Instruction Register and determines:
What operations need to be done, and
What type of operands will be used

During the execution part, the specified operation is performed

(add, compare, etc).

After execution of the instruction has been completed the cycle starts
all over again (unless the instruction terminates the program).
Fetch-Decode-Execute Diagram

CPU Main Memory

Fetch …
Program Counter (PC)
Get instruction and
3024
3023 increment PC 3020
3021
Instruction Register
3022
add r3, r1, r2
add r3, r1, r2 3023
Decode 3024
General Purpose Registers
Determine what the
3025
33 r1 instruction is (add)
3026
45 r2
Execute 3027
78 r3 In this case add r1 and
r2 and put result in r3. 3028
…
Fig. 19 Fetch-Decode-Execute Diagram
 FETCH and DECODE
T0: AR PC (S0S1S2=010, T0=1)
T1: IR  M [AR], PC  PC + 1 (S0S1S2=111, T1=1)
T2: D0, . . . , D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)

To provide the data path

for the transfer of PC to
AR, we must apply timing
signal T0 to achieve the
following connection:
1. Place the content of
PC onto the bus by
making the bus selection
inputs S2S1S0 equal to
010.

2. Transfer the content of

the bus to AR by
enabling the LD input of
AR . Fig. 20 Register transfer for fetch phase
 FETCH and DECODE

Timing signal T1 provide the following connections in the bus

system:
Enable the read input of memory.
Place the content of memory onto the bus by making S2 S1 S0 =
111.
Transfer the content of the bus to IR by enabling the LD input of IR
.
Increment PC by enabling the INR input of PC .
DETERMINING THE TYPE OF INSTRUCTION

Fig. 21 Register transfer for fetch phase

 DETERMINE THE TYPE OF INSTRUCTION

The three instruction types are subdivided into four separate

paths.
The selected operation is activated with the clock transition
associated with timing signal T3.

D7’ IT3: AR <-- M [AR]

D7’ I' T3: Nothing
D7 I' T3: Execute a register-reference instruction
D7IT3: Execute an input-output instruction
 REGISTER REFERENCE INSTRUCTIONS
Register Reference Instructions are identified when
- D7 = 1,(OPCODE=1 1 1 ) I = 0
- Register Ref. Instr. is specified in b0 ~ b11 of IR
- Execution starts with timing signal T3
r = D7 IT3 => Register Reference Instruction
Bi = IR(i) , i=0,1,2,...,11
r: SC  0
CLA rB11: AC  0
CLE rB10: E0
CMA rB9: AC  AC’
CME rB8: E  E’
CIR rB7: AC  shr AC, AC(15)  E, E  AC(0)
CIL rB6: AC  shl AC, AC(0)  E, E  AC(15)
INC rB5: AC  AC + 1
SPA rB4: if (AC(15) = 0) then (PC  PC+1)
SNA rB3: if (AC(15) = 1) then (PC  PC+1)
SZA rB2: if (AC = 0) then (PC  PC+1)
SZE rB1: if (E = 0) then (PC  PC+1)
 MEMORY REFERENCE INSTRUCTIONS

Fig. 22 Register transfer for fetch phase

- The effective address of the instruction is in AR and was placed there
during
timing signal T2 when I = 0, or during timing signal T3 when I = 1
- Memory cycle is assumed to be short enough to complete in a CPU cycle
- The
AND execution of MR instruction starts with T4
to AC
D0T4: DR  M[AR] Read operand
D0T5: AC  AC  DR, SC  0 AND with AC
ADD to AC
D1T4: DR  M[AR] Read operand
D1T5: AC  AC + DR, E  Cout, SC  0 Add to AC and store carry in E
 MEMORY REFERENCE INSTRUCTIONS

LDA: Load to AC
D2T4: DR  M[AR]
D2T5: AC  DR, SC  0
STA: Store AC
D3T4: M[AR]  AC, SC  0
BUN: Branch Unconditionally
D4T4: PC  AR, SC  0
BSA: Branch and Save Return Address
M[AR]  PC, PC  AR + 1
 MEMORY REFERENCE INSTRUCTIONS

BSA:
D5T4: M[AR]  PC, AR  AR + 1
D5T5: PC  AR, SC  0

ISZ: Increment and Skip-if-Zero

D6T4: DR  M[AR]
D6T5: DR  DR + 1
D6T4: M[AR]  DR, if (DR = 0) then (PC  PC + 1), SC  0
 FLOWCHART FOR MEMORY REFERENCE
INSTRUCTIONS

Fig. 23 Flowchart for memory reference

instructions
 Input-Output Instructions

Fig. 24 Input output instructions

Hardwired Control for the basic computer

Fig. 25 Hardwired control unit

 Reference
s
[Ref.1] John L. Hennessy and David A Patterson, Computer Architecture A
quantitative Approach, Morgan Kaufmann / Elsevier, Fourth Edition, 2007 .
[Ref.2] Mafla, E. Course Notes, CDA3101, @ URL
http://www.cise.ufl.edu/~emafla/
(as-of 11 Apr 2001)
[Ref.3] https://people.cs.clemson.edu/~mark/uprog.html
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Applications
with the 8085, Prentice Hall, Fifth Edition, 1996.
[Ref.5] William Stallings, Computer Organization and Architecture–Designing
for
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4, and Core2 with 64-bit Extensions : Architecture, Programming, and Interfacing.
Pearson Education India, Eigth Edition, 2019.
[Ref.7] Nicholas Carter, Schaum’s outline of Computer Architecture, Tata McGraw
 Reference
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[Ref.8] Patterson, D.A. and J.L. Hennesey. Computer Organization and Design: The
Hardware/Software Interface, Second Edition, San Francisco, CA: Morgan
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[Ref.9]http://cs.sru.edu/~mullins/cpsc100book/module03_internalHardware/modul
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York: Academic Press, 1976.