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Programmable array logic
Programmable logic devices (PLDs) like PLA, PAL, CPLD and FPGA allow implementing logic circuits using programmable switches. PLA and PAL have programmable AND planes and OR planes to implement sum-of-products logic. PALs are simpler than PLAs with fixed OR planes. CPLDs contain multiple PAL-like blocks with programmable interconnects. FPGAs provide programmable logic blocks and interconnects to implement larger circuits without AND/OR planes. All PLDs require programming using CAD tools to set the switches for the desired logic function.
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Overview of presentation focusing on Programmable Array Logic with presenters listed.
Discussion on Programmable Logic Devices (PLDs), their customization and main types: PLA, PAL, ROM, CPLD, FPGA.
Illustration of PLDs as black boxes with inputs as logic variables and outputs as logic functions.
Description of PLA usage for circuits in SOP form, with programmable connections in AND and OR planes.
Outline of PAL’s use in SOP circuits, highlighting programmable AND plane and fixed OR plane connections.
Discusses PLA limitations, including size, input/output constraints, and performance considerations.
A schematic example illustrating functions and connections in a PAL setup.
Comparison highlighting the limitations of PALs versus PLAs, including performance and complexity.
Definition and role of macrocells in PAL, including feedback and clock synchronization.
Detailed functionality of macrocells, including output functionality and design synchronization.
Explains multi-level design using PALs for logic functions through a detailed mathematical expression.
Overview of ROM with fixed AND plane and programmable OR plane for decoding logic combinations.
Methods to program SPLDs (PLAs, PALs, ROMs) with CAD tools and fuse map usage for programming.
Description of the SPLD programming unit for programming devices outside of the PCB.
Introduction to removable SPLD socket packages, specifically PLCC for ease of integration.
Details of ISP for non-removable SPLDs programming using a special cable and computer interface.
Overview of Complex Programmable Logic Devices (CPLDs), highlighting their structure and capabilities.
Illustration of CPLD structure including multiple PAL-like blocks and interconnection networks.
Detail on PAL-like blocks within CPLDs, including macrocells and fixed OR planes.
Information on programming methods for CPLDs, focusing on ISP and JTAG connections.
Description of FPGAs, highlighting their ability to handle larger circuits without AND/OR planes.
Diagrammatic representation of FPGA structure featuring I/O blocks and logic blocks.
Ending remarks and thank you note to the audience.
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Programmable array logic
- 1. Programmable Array Logic PresentationBy: Fareed Yousuf Jawwad Khatri Muhammad Afnan SMI University
- 2. PLDs ProgrammableLogic Devices (PLD) General purpose chip for implementing circuits Can be customized using programmable switches Main types of PLDs PLA PAL ROM CPLD FPGA Custom chips: standard cells, sea of gates
- 3. PLD asa Black Box Logic gates and programmable switches Inputs (logic variables) Outputs (logic functions)
- 4. Programmable LogicArray (PLA) Use to implement circuits in SOP form The connections in the AND plane are programmable The connections in the OR plane are programmable f1 AND plane OR plane Input buffers inverters and P1 Pk fm x1 x2 xn x1 x1 xn xn
- 5. Programmable ArrayLogic (PAL) Also used to implement circuits in SOP form The connections in the AND plane are programmable The connections in the OR plane are NOT programmable f1 AND plane OR plane Input buffers inverters and P1 Pk fm x1 x2 xn x1 x1 xn xn fixed connections
- 6. Limitations ofPLAs PLAs come in various sizes Typical size is 16 inputs, 32 product terms, 8 outputs Each AND gate has large fan-in this limits the number of inputs that can be provided in a PLA 16 inputs 316 = possible input combinations; only 32 permitted (since 32 AND gates) in a typical PLA 32 AND terms permitted large fan-in for OR gates as well This makes PLAs slower and slightly more expensive than some alternatives to be discussed shortly 8 outputs could have shared minterms, but not required
- 7. Example Schematicof a PAL f1 P1 P2 f2 x1 x2 x3 AND plane P3 P4 f1 = x1x2x3'+x1'x2x3 f2 = x1'x2'+x1x2x3
- 8. Comparing PALsand PLAs PALs have the same limitations as PLAs (small number of allowed AND terms) plus they have a fixed OR plane less flexibility than PLAs PALs are simpler to manufacture, cheaper, and faster (better performance) PALs also often have extra circuitry connected to the output of each OR gate The OR gate plus this circuitry is called a macrocell
- 9. Macrocell f1 back toAND plane D Q Clock Select Enable Flip-flop OR gate from PAL 0 1
- 10. Macrocell Functions Enable = 0 can be used to allow the output pin for f1 to be used as an additional input pin to the PAL Enable = 1, Select = 0 is normal for typical PAL operation Enable = Select = 1 allows the PAL to synchronize the output changes with a clock pulse The feedback to the AND plane provides for multi- level design f 1 back to AND plane D Q Clock Select Enable 0 1
- 11. Multi-Level Designwith PALs f = A'BC + A'B'C' + ABC' + AB'C = A'g + Ag' where g = BC + B'C' and C = h below D Q Clock Sel = 0 En = 0 0 1 D Q Clock Select 0 1 D Q Clock Sel = 0 En = 1 0 1 A B h g f
- 12. ROM AROM (Read Only Memory) has a fixed AND plane and a programmable OR plane Size of AND plane is 2n where n = number of input pins Has an AND gate for every possible minterm so that all input combinations access a different AND gate OR plane dictates function mapped by the ROM
- 13. Programming SPLDs PLAs, PALs, and ROMs are also called SPLDs – Simple Programmable Logic Devices SPLDs must be programmed so that the switches are in the correct places CAD tools are usually used to do this A fuse map is created by the CAD tool and then that map is downloaded to the device via a special programming unit There are two basic types of programming techniques Removable sockets on a PCB In system programming (ISP) on a PCB This approach is not very common for PLAs and PALs but it is quite common for more complex PLDs
- 14. An SPLDProgramming Unit The SPLD is removed from the PCB, placed into the unit and programmed there
- 15. Removable SPLDSocket Package PLCC (plastic-leaded chip carrier) Printed circuit board PLCC socket soldered to the PCB
- 16. In SystemProgramming (ISP) Used when the SPLD cannot be removed from the PCB A special cable and PCB connection are required to program the SPLD from an attached computer Very common approach to programming more complex PLDs like CPLDs, FPGAs, etc.
- 17. CPLD ComplexProgrammable Logic Devices (CPLD) SPLDs (PLA, PAL) are limited in size due to the small number of input and output pins and the limited number of product terms Combined number of inputs + outputs < 32 or so CPLDs contain multiple circuit blocks on a single chip Each block is like a PAL: PAL-like block Connections are provided between PAL-like blocks via an interconnection network that is programmable Each block is connected to an I/O block as well
- 18. Structure ofa CPLD PAL-like block I/Oblock PAL-like block I/Oblock PAL-like block I/Oblock PAL-like block I/Oblock Interconnection wires
- 19. Internal Structureof a PAL-like Block Includes macrocells Usually about 16 each Fixed OR planes OR gates have fan-in between 5-20 XOR gates provide negation ability XOR has a control input D Q D Q D Q PAL-like block PAL-like block
- 20. Programming aCPLD CPLDs have many pins – large ones have > 200 Removal of CPLD from a PCB is difficult without breaking the pins Use ISP (in system programming) to program the CPLD JTAG (Joint Test Action Group) port used to connect the CPLD to a computer
- 21. FPGA SPLDsand CPLDs are relatively small and useful for simple logic devices Up to about 20000 gates Field Programmable Gate Arrays (FPGA) can handle larger circuits No AND/OR planes Provide logic blocks, I/O blocks, and interconnection wires and switches Logic blocks provide functionality Interconnection switches allow logic blocks to be connected to each other and to the I/O pins
- 22. Structure ofan FPGA I/O block I/O block I/Oblock I/Oblock logic block interconnection switch
- 23.