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Risc cisc Difference
This document compares RISC and CISC architectures by examining the MIPS R2000 and Intel 80386 processors. It discusses the history of RISC and CISC, providing examples of each. Experiments using benchmarks show that while the 80386 executes fewer instructions on average than the R2000, the difference is small at around a 2x ratio. Both instruction sets are becoming more alike over time. In the end, performance depends more on how fast a chip executes rather than whether it is RISC or CISC.
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Risc cisc Difference
- 1. Advance Computer Architecture December8, 2013 Presented By: Zunera Altaf Ambreen Younas Sehrish Asif Wajeeha 1
- 2. COMPARISON BETWEEN RICS v/sCISC BY Yi Gao Shilang Tang Zhongli Ding 2
- 3. AGENDA 1 2 3 4 • Introduction • History •RISC v/s CISC • Experiments with MIPS 2000 and Intel 80386 • The Benchmarks • Benchmark Selection • Benchmark Compilation • Data Collection • Instruction Count • Instruction Format and Encoding • Addressing Modes • Data Traffic • Conclusion • Who Wins?
- 4. INTRODUCTION The debate betweenCISC & RISC has been going on for a long time and will likely continue. The difference between RISC and CISC can lays on many levels, lots of plausible arguments are put forward by both sides such as. Code density Transistor counts Memory bottlenecks Compiler Decode complexity etc. December 8, 2013 4
- 5. INTRODUCTION(CONT.) This paper intendsto compare these two different ideas in detail, their distinct characters, their possible specific application domains, their current scope and their future development to the CPU design. December 8, 2013 5
- 6. INTRODUCTION(CONT.) To Explain thedifference between them experiment mainly based on the MIPS R2000 and Intel 80386 instruction sets. MIPS R2000 is a typical product of pure RISC Intel 80386 is a typical kind of pure CISC chip December 8, 2013 6
- 7. HISTORY OF RISC& CISC The IBM 360 system, created in 1964, was probably the first modern processor system. Micro-coded control. Desire to reduce semantic gap. Execute fewer instructions and thus would have better performance. Provide hardware flexibility. Instructions with different sizes and execution cycles, which makes CISC instructions harder to pipeline. December 8, 2013 7
- 8. HISTORY (CONT.) In themiddle of 70's people began to doubt the design philosophy behind CISC with: Complex instructions sets. Decoding and execution of such instructions were complicated and timeconsuming. Overhead brought by them slowed down the execution of those more frequently used simple instructions. All these may finally decrease the performance December 8, 2013 8
- 9. HISTORY (CONT.) Basedon previous (slide) observation, RISC chips evolved around the mid 1970 as a reaction at CISC chips. In 70's, John Cocke at IBM's T.J Watson Research Center provided the fundamental concepts of RISC. December 8, 2013 9
- 10. HISTORY (CONT.) This chipcontained many traits a later RISC chip should have: Few instructions. Fix sized instructions in a fixed format. Execution on a single cycle of a processor. Load / Store architecture. Hard-wired control superscalar and speculation is possible easier. They realized that RISC promised higher performance, less cost and faster design time. December 8, 2013 10
- 11. HISTORY (CONT.) Thedesign philosophies behind RISC chip are "make common case faster“ and "simple is best“. In a CISC chip, many very complex instructions never or seldom used, but they make the control unit extremely complex and thus have a high control unit delay. As researchers continued into RISC during the 1970's and 1980's it became clear that the factors described resulted in a speed increase over CISC designs. December 8, 2013 11
- 12. HISTORY (CONT.) Withthe fleeting of time, the battle over RISC and CISC became blur, though pure RISC machine may outperform pure CISC machine, but both of each have some bad faces which interfere their further improvement of performance. In 90's, the trend is migrating toward each other, RISC machines may adopt some traits from CISC, while CISC may also do it vice versa. December 8, 2013 12
- 13. HISTORY (CONT.) An exampleis Intel microprocessors, though they use a CISC instruction set and are considered CISC chips, the internal architecture has gradually migrated to RISC. December 8, 2013 13
- 14.
- 15. COMPARISON CISC RISC • • • • • • • • Richer instruction set,some simple, some very complex. Instructions generally take more than 1 clock to execute. Instructions of a variable size. Instructions interface with memory in multiple mechanisms with complex addressing modes. No pipelining. Upward compatibility within a family. Microcode control. Work well with simpler compiler. • • • • • • Simple primitive instructions and addressing modes. Instructions execute in one clock cycle. Uniformed length instructions and fixed instruction format. Instructions interface with memory via fixed mechanisms. Pipelining. Instruction set is orthogonal (little overlapping of instruction functionality) • Hardwired control. • Complexity pushed to the compiler. December 8, 2013 15
- 16. Comparison (Cont.) Advance CISC •Segmented memory model • Few registers • Crappy floating point performance Advance RISC • Superscalar and out-of-order execution • Large number of registers • Fast floating point performancef December 8, 2013 16
- 17. Middle to 80’s Intel'sfaster CISC runs faster and Machines Still the old Non Intel's Machines with a Now, The differenceinstructionpointthey decent floating runset, but Seemed to have a clearly adopt between RISC CISC some upside, until the appearing performance. and Characteristics RISCone e.g. of i486, Pentium and now PII, PIII. is no longer one of clock execution instruction sets, butsuperscalar operations of and lots the whole chip architecture of registers. and system. RISC machines added more instructions to their architectures for new data types. December 8, 2013 17
- 18. CISC & RISCPROCESSORS December 8, 2013 18
- 19. CISC & RISC’SMODELS CISC • DEC VAX • Motolora 68K and 680x0 • Intel 80x86 Experiments with RISC • • • MIPS • • • • • HP PA-RISC IBM RT-PC IBM RS6000 2000 and Intel 80386 Intel's i860 and i960, MIPS R2000 (and so on), Motorola's 88K, Motolora/IBM's PowerPc Sun's SPARC 19 December 8, 2013
- 20. INTEL 80386 VSMIPS R2000 December 8, 2013 20
- 21. Comparison MIPS 2000 1. Anadvanced microprocessor optimized for multitasking operating systems 2. Designed for applications needing very high performance. 3. Its 32-bit registers and data paths support 32-bit addresses and data types 4. 32-bit architecture with 32-bit address space, the 80386 added new addressing modes and additional operations 80386 also added paging support in addition to segmented addressing. Like 80286, the 80386. 6. 80386 has 16 registers 8 of them can be general purpose registers and 8 additional floating point registers. Intel 80386 1. Design came from the Stanford MIPS project, which stood for Microprocessor without Interlocked Pipeline Stages, and was debatably the first commercial RISC processor. 2. It is a 32-bit processor with an off-chip split cache for instructions and data 3. 32 general purpose integer registers and 16 separate 64-bit floating point registers. The integer pipeline has a depth of 5 and the floating-point pipeline a maximal depth of 4. It has only 2 addressing mode, its opcode is 6 bits, which limits the totally number of instructions and it has one delay slot used for delayed branch. December 8, 2013 21
- 22. SUMMARY OF 80386AND MIPS R2000 ARCHITECTURES Components MIPS R2000 Intel 80386 Date announced 1986 1985 Instruction size(bits) 32 Variable Address space(size, model) 32 bits, flat 32 bits, segmented with paging support Data alignment Aligned No Data addressing modes 2 11 Protection Page Segmented Scheme Integer registers 31 GPR*32 bits (number, model, size) 8 GPR*32 bits, 6 segment registers*16 bits, 2 other * 16 bits Floating-point format IEEE 754 single, double, extended IEEE 754 single December 8, 2013 22
- 23. MIPS R2000 RISC December 8, 2013 23
- 24. INTEL 80386 CISC December8, 2013 24
- 25.
- 26. BENCHMARK SELECTION Weselect benchmarks used for comparison carefully; we try to select benchmarks that can cover as many faces as possible. The series of benchmarks we selected varies from real programs to some famous one we got from web, and they are all C programs. December 8, 2013 26
- 27. INTEGER BENCHMARK Test1 Is asuit of programs use for compiler optimization analysis. Standford Suite of benchmarks that are relatively short both in program size and execution time. Poly Very common and typical real-world integer program. Includes 7 small programs: • bubble sort, • towers of Hanoi, • the 8 queens problem, • quick sort, • integer matrix multiply, • Perm and Sieve. December 8, 2013 27
- 28. FLOATING-POINT BENCHMARKS: Whetstone Mix offloating-point and integer arithmetic Function calls Array indexing Conditional jumps Transcendental functions. Defeat many simple compiler optimizations. It makes little use of memory and benefits little from the addition of cache memory. Var Corresponding to poly, it is a very common real-world FP program. Lre This is a real-world computation intensive program. December 8, 2013 28
- 29. BENCHMARK COMPILATION For MIPSR2000 cc which comes with the SGI Unix OS along with an argument: cc –mips1*.c. For Intel 80386 VC’s debug to get 80386 instructions. December 8, 2013 29
- 30. DATA COLLECTION To MIPSR2000 • We used pixie and a pixie-statistical program to collect dynamic instruction counts. To 80386 • We used gcov and statistical programs to dynamically count all kinds of instructions and other data. December 8, 2013 30
- 31. RESULTS FROM BENCHMARKS December8, 2013 31
- 32.
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- 34.
- 35. INSTRUCTION COUNT Results: • Ratio1.0 means that MIPS R2000 executes fewer instructions then 80386. 35
- 36. INSTRUCTION FORMAT ANDCODING For MIPS R2000, every instruction is 32bits (4 bytes) long with a fixed 6 bits opcode. It has 4 categories of formats: 1. Register-Register 2. Register-immediate 3. Branch 4. Jump/call December 8, 2013 36
- 37. INSTRUCTION FORMAT ANDCODING Register-Register: Op(6) Rs1(5) Rs2(5) Rd(5) Const(5) Opx(6) Register-immediate: Op(6) Rs1(5) Rs2(5) Const(16) December 8, 2013 37
- 38. INSTRUCTION FORMAT ANDCODING Branch: Op(6) Rs1(5) Opx(5) Const(16) Jump/call: Op(6) Const(26) December 8, 2013 38
- 39. INSTRUCTION FORMAT OFTHE 80386 The instruction encoding in 80386 is complex, with many different instruction formats. Instruction may vary from one byte, where there are no operands, to up to 17 bytes long. Table 3.5a shows the instruction formats for 80386. December 8, 2013 39
- 40. INSTRUCTION FORMAT OFTHE 80386 December 8, 2013 40
- 41. ADDRESSING MODES MIPS R2000,it has only two kinds of addressing modes: Register indirect Immediate It accesses memory only through load/store instruction, to other instructions, the operands come from registers. December 8, 2013 41
- 42. ADDRESSING MODES To 80386,the operand types of 1st and 2nd operand can be like below: R, R R, Imm R, Mem Mem, R Mem, Imm December 8, 2013 42
- 43. IT SUPPORT 7DATA MEMORY ADDRESSING MODES: 80386 has 11 addressing modes in total, some are below: Absolute Register indirect Based Indexed Based indexed with displacement Based with scaled indexed and displacement December 8, 2013 43
- 44. DATA TRAFFIC December 8,2013 44
- 45. CONTINUE.. The debate betweenRISC and CISC will likely continue, even if the battle lines are now becoming fuzzy. This seems clear, no matter what your RISC or CISC persuasion. But the future might not bring victory to one of them, but makes both extinct.
- 46. CONCLUSIONS IC in 80386is less than MIPS R2000, but not very much (average ratio < 2) CISC has richer Instruction set, but in our case, the programs just use around 15% of all the instructions CISC has better code density, 80386’s average instruction length is less than MIPS R2000’s To 80386, the operand types can be “Memory”, while in MIPS R2000, only load/store will access memory, all operands are in registers. Cache and memory designer should be aware of this difference. 80386 has richer addressing modes, but in both integer and floating-point case, 3 addressing modes used for about 90%’s addressing, some addressing modes even never used December 8, 2013 46
- 47. WHO WINS? Thedifference between RISC and CISC chips is getting smaller and smaller. RISC and CISC architectures are becoming more and more alike. Many of today's RISC chips support just as many instructions as yesterday's CISC chips. Here maybe we can simply say that RISC and CISC are growing to each other in their architecture in the theoretical point of view.
- 48. CONTINUE.. In reality, whatcounts is how fast a chip can execute the instructions it is given and how well it runs existing software. Today, both RISC and CISC manufacturers are doing everything to get an edge on the competition. In 90's, most new generations of processors employ a mixed bag of architectural features, including multiple execution units, pipelining, caches, and floating-point integration, thus makes performance comparisons almost useless outside of a specific application. December 8, 2013
- 49. CONTINUE.. Finally, Theypoint out that the biggest threat for CISC and RISC might not be each other, but a new technology called EPIC. EPIC stands for Explicitly Parallel Instruction Computing. EPIC is a created by Intel and is in a way a combination of both CISC and RISC.
- 50. CONTINUE.. From ourlimited experience based on the results of our benchmarks, it appears that theoretically the pure RISC machine such as MIPS R2000 is a more promising style of computer design Compared to Intel 80386 CISC Chip at that era. With time fleeting, however, the bottom line between CISC and RISC becomes blur, in real world, people only care about how well a system can serve them.
- 51.
Editor's Notes
- #27 We select benchmarks used for comparison carefully; we try to select benchmarks that can coveras many faces as possible. The series of benchmarks we selected varies from real programs tosome famous one we got from web, and they are all C programs.
- #31 Pixie and gcov instrument programs tocollect enough information to determine how often each user-level instruction is executed, whileour own statistical programs produce summary data based on these counts.