MICROCONTROLLER 8051- Architecture & Pin Configuration

Microcontroller 8051
Architecture And Pin Configuration OF 8051
#Presented By AKHIL MADANKAR.#
A

General-purpose Microprocessors
 CPU
 No RAM
 No ROM
 No I/O ports
RAM
Address bus
Data bus
ROM Printer Disk Monitor Keyboard
Control bus
Microprocessor
CPU
Write
Read/

General-purpose Microcontroller
 CPU (microprocessor)
 RAM
 ROM
 I/O ports
 Timer
 ADC and other peripherals
Serial
COM
Port
TimerI/O
ROMRAMCPU
Microcontroller

Features Of 8051
128 bytes of RAM
4 K bytes of on-chip ROM
Two timers
One serial port
Four I/O ports, each 8 bits wide(i.e. 32 I/O pins.)
6 interrupt sources
Commercially available version of 8051 run on 12 MHz to 18 MHz

Architecture Of 8051
Interrupt
Control
Bus
Control
CPU
OSC I/O
Ports
Serial
Port
Etc.
Timer 0
Timer 1
On-chip
RAM
On-chip
ROM
for code
P3P0P1P2 TXD RXD
Interrupts

Functional Description Block
 Accumulator
- SFR
- It can be accessed through its SFR adder 0E0H.
 B Register
- Use as temporary register .
- store upper bit Result of MUL & DIV.
- access through SFR adder 0F0H.
 Stack Pointer
- Define anywhere on chip 128 byte RAM.
- It is Initialised to 07H address (after rest) .
 Data Pointer
- 16 bit register
-Access external memory up to 64KB.
Arch8051

 Program Status Word
- Reflect status ALU performing operation.
 Port 0 to 3
- Each latch and corresponding drivers of port 0 to 3 is allotted to the
corresponding on chip I/O port.
 Serial Data Buffer
- Two Independent Register : TX Buffer (8bit) & RX Buffer(8bit).
 Program Counter
- 16 bit wide
- Point to address of next instruction to be executed .
Arch8051

 Timing & Control Unit
- Deriver signal required for Internal operation of circuit .
- Control signal required for controlling External System Bus.
 Oscillator
- Generate basic timing control signal for operation of circuit using crystal oscillator.
 ALU
- Perform 8 bit operation.
- Through TMP1 and TMP2 (each 8 bit).
- Not access by User.
 SFR Register Bank
- lie in range of 80H to 0FFH .
- It can addressed using their respective address .
Arch8051

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P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
(RXD)P3.0
(TXD)P3.1
(T0)P3.4
(T1)P3.5
XTAL2
XTAL1
VSS
(INT0)P3.2
(INT1)P3.3
(RD)P3.7
(WR)P3.6
VCC
P0.0(AD0)
P0.1(AD1)
P0.2(AD2)
P0.3(AD3)
P0.4(AD4)
P0.5(AD5)
P0.6(AD6)
P0.7(AD7)
EA/VPP
PSEN
P2.7(A15)
P2.6(A14)
P2.5(A13)
P2.4(A12)
P2.3(A11)
P2.2(A10)
P2.1(A9)
P2.0(A8)
8051 ALE/PROG
Pin Configuration
OF 8051
 VCC & VSS
 RESET
 ALE/PROG
- It is used for demultiplexing
address and data .
- It is valid only for External
memory accesses.
 EA/VPP
- EA/VPP =0 : Execute program on
external memory.
- EA/VPP =1 : Execute program on
internal memory.
- Receives 21 v for programming
of the on chip EPROM.

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P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
(RXD)P3.0
(TXD)P3.1
(T0)P3.4
(T1)P3.5
XTAL2
XTAL1
VSS
(INT0)P3.2
(INT1)P3.3
(RD)P3.7
(WR)P3.6
VCC
P0.0(AD0)
P0.1(AD1)
P0.2(AD2)
P0.3(AD3)
P0.4(AD4)
P0.5(AD5)
P0.6(AD6)
P0.7(AD7)
EA/VPP
PSEN
P2.7(A15)
P2.6(A14)
P2.5(A13)
P2.4(A12)
P2.3(A11)
P2.2(A10)
P2.1(A9)
P2.0(A8)
8051 ALE/PROG
Pin Configuration
OF 8051
 PSEN
- Acts as a strobe to read the
external program memory.
- It is low during external program
memory accesses.
 Port 0 (P0.0-P0.7)
- 8 bit bidirectional bit addressable
I/O port.
- Allotted an address in SFR
address range.
- Act as Multiplexed A/D lines
during external memory access.
PIN8051

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P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
(RXD)P3.0
(TXD)P3.1
(T0)P3.4
(T1)P3.5
XTAL2
XTAL1
VSS
(INT0)P3.2
(INT1)P3.3
(RD)P3.7
(WR)P3.6
VCC
P0.0(AD0)
P0.1(AD1)
P0.2(AD2)
P0.3(AD3)
P0.4(AD4)
P0.5(AD5)
P0.6(AD6)
P0.7(AD7)
EA/VPP
PSEN
P2.7(A15)
P2.6(A14)
P2.5(A13)
P2.4(A12)
P2.3(A11)
P2.2(A10)
P2.1(A9)
P2.0(A8)
8051 ALE/PROG
Pin Configuration
OF 8051
 Port 1 (P1.0-P1.7)
port.
address range.
 Port 2 (P2.0-P2.7)
- During external memory, It emits
higher 8 bits of address when
ALE =1 & EA=0 .
- Also receives higher order
address bit during programming of
on chip EPROM.
PIN8051

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P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
(RXD)P3.0
(TXD)P3.1
(T0)P3.4
(T1)P3.5
XTAL2
XTAL1
VSS
(INT0)P3.2
(INT1)P3.3
(RD)P3.7
(WR)P3.6
VCC
P0.0(AD0)
P0.1(AD1)
P0.2(AD2)
P0.3(AD3)
P0.4(AD4)
P0.5(AD5)
P0.6(AD6)
P0.7(AD7)
EA/VPP
PSEN
P2.7(A15)
P2.6(A14)
P2.5(A13)
P2.4(A12)
P2.3(A11)
P2.2(A10)
P2.1(A9)
P2.0(A8)
8051 ALE/PROG
Pin Configuration
OF 8051
 Port 3 (P3.0-P3.7)
port.
address range.
 XTAL1 & XTAL2
- A Crystal is to be connected
externally between these two pins
to complete the feedback path to
start oscillations.
- Controller can be operated on
external clock .
PIN8051

References
1.
The 8051 Microcontroller and Embedded Systems: Using Assembly and C.
By Mazidi, Mazidi and McKinlay.
2.
Advanced Microprocessor And Peripherals .3E
By K M Bhurchuandi and A K Ray .
3.
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MICROCONTROLLER 8051- Architecture & Pin Configuration

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MICROCONTROLLER 8051- Architecture & Pin Configuration