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CA Assignment 2

This document describes a single-cycle machine data-path architecture. It explains that in a single-cycle design, all instructions complete in exactly one clock cycle, with the clock cycle length determined by the longest instruction path. It has features like executing only one instruction per cycle, requiring duplicate hardware, and a performance baseline. The document then provides details on implementing a single-cycle design, including assumptions, advantages like simplicity, and disadvantages like being limited by the longest instruction path. It lists arithmetic and logical instructions that were implemented in the single-cycle machine like ADD, MULT, OR, AND, XOR, LW, and SW.

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79 views4 pages

CA Assignment 2

This document describes a single-cycle machine data-path architecture. It explains that in a single-cycle design, all instructions complete in exactly one clock cycle, with the clock cycle length determined by the longest instruction path. It has features like executing only one instruction per cycle, requiring duplicate hardware, and a performance baseline. The document then provides details on implementing a single-cycle design, including assumptions, advantages like simplicity, and disadvantages like being limited by the longest instruction path. It lists arithmetic and logical instructions that were implemented in the single-cycle machine like ADD, MULT, OR, AND, XOR, LW, and SW.

Uploaded by

INAM
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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COMSATS INSTITUE OF INFORMATION TECHNOLOGY

COMPUTER ARCHITECTURE – ASSIGNMENT 2

COMPUTER ARCHITECTURE

ASSIGNMENT 2

Submitted By
Inaam Ullah Khan
FA19-BCS-061

Submitted To
Sir Muhammad Ali Faisal

Date
22-04-2021

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COMSATS INSTITUE OF INFORMATION TECHNOLOGY
COMPUTER ARCHITECTURE – ASSIGNMENT 2
QUESTION
Describe The “Single-Cycle” Machine Data-Path Architecture

Single Cycle:
Single-cycle means that all implemented instructions complete in
exactly one cycle (and exactly one instruction is worked on each cycle).
To achieve this, the cycle time (the inverse of the clock rate) is set long
enough that the slowest of the implemented instructions has enough
time to complete.
Single Cycle design is simple but it is inefficient. All instructions have
same clock cycle length, they all take the same amount of time
regardless of what they actually do. Clock cycle determined by longest
path that is Load uses IM, RF, ALU, DM, RF in sequence. But others may
be shorter R-type (arithmetic) use IM, RF, ALU, RF.

Single Data-path is equivalent to the original single-cycle data-path, the


data memory has only one Address input. The actual memory operation
can be determined from the Mem-Read and Mem-Write control
signals. There are separate memories for instructions and data. There
are 2 adders for PC-based computations and one ALU. The control
signals are the same.

Features of Single Cycle Machine Data-Path:


 Instructions are not subdivided.
 Clock cycles are long enough for the lowest instruction.
 There are only 1 instruction that can be executed at the same
time.
 There is 1 cycle per instruction, that is CPI = 1.
 Control unit generates signals for the entire instruction.
 There is duplicate hardware, because we can use a functional unit
for at most one subtask per instruction.
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COMSATS INSTITUE OF INFORMATION TECHNOLOGY
COMPUTER ARCHITECTURE – ASSIGNMENT 2
 Extra registers are not required.
 Performance is baseline.
Single-Cycle Implementation:
Assume each instruction is executed in 1 clock cycle. Each component
(memory, ALU, etc.) can be used only once. Reason for assuming
separate instruction and data memories
Advantage: Simpler to design.
Disadvantage: Speed of machine is determined by time for longest
path.
Memory access is much slower than register access, but most
instructions use only registers. Each instruction type can take different
number of clock cycles. Common elements for all instructions:
Instruction fetch, PC update Access 1 or 2 registers.
Following are the Arithmetic and Logical instructions that I
implemented:
 ADD

 MULT

 OR

 AND

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COMSATS INSTITUE OF INFORMATION TECHNOLOGY
COMPUTER ARCHITECTURE – ASSIGNMENT 2

 XOR

 LW

 SW

4|Page

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