ESc201 : Introduction to Electronics

Sequential Circuits

Vipul Arora
Dept. of Electrical Engineering
IIT Kanpur
April 10, 2023
1
 Digital Circuits

Combinational Circuits Sequential Circuits

X Z
CC
X

CC W
Y
Storage
elements

Output is determined by current Output is determined by the

values of inputs only. current and past values of
inputs/outputs.
 Sequential Circuits
• Time
• The current state depends on previous states
too
• … if circuit has memory

• E.g., Latch or Flip-flop: binary output

3
NOR SR Latch (Set-Reset Latch)

R 1
0 Q
0
Q = 1; Q = 0 Set State

1
Q = 0; Q = 1 Re set State
Q
S 0

S R Q Q State

1 0 1 0 SET
NOR SR Latch
Reset

R 0
Q
1 Q = 1; Q = 0 Set State

1 Q = 0; Q = 1 Re set State
0 0 Q
S

Set

S R Q Q State
1 0 1 0 SET

0 1 0 1 RESET
HOLD State

S R Q Q State
R 1 1
Q 1 0 1 0 SET
0
0 0 1 0 HOLD

0 1 0 1 RESET
0 Q 0 1 HOLD
S 0 0 0 0

S R Q Q State

1 0 1 0 SET

0 1 0 1 RESET
0 0 Q Q HOLD 1 bit memory?

1 1 0 0 INVALID
 INVALID state
• The two outputs do not follow 𝑄 and 𝑄ത
relationship
• Switching from 11 to 00 could lead to
unpredictable results due to even a slight de-
synchronization in the two inputs

7
 R 0 Q
1

Both the outputs are well defined and 0.

The first problem is that we do not get
0 complementary output.
1 Q
S

A more serious problem occurs when we switch the latch to the hold state by
changing RS from 11 → 00 . Suppose the inputs do not change
simultaneously and we get the situation 11 → 01* → 00

1 0 1 0
R 0 Q
R
Q
R 1 Q

0 0
S 1 Q
S 1 Q
S 0 Q
0
Q=1
 1 0 1 0
R 0 R R 1 Q
Q Q

0 0
1 Q 1 Q S
0 Q
S 0 S

Q=1

Suppose the inputs change as RS = 11 → 10* → 00

1 1 0 0
R 0 Q
R
Q
R 0 Q

1 1
S 1 Q
S 0 Q
S 0 Q
0
Q=0
So although output is well defined when we apply RS = 11, it becomes
unpredictable once we switch the latch to hold state by applying RS = 00. That
is why RS = 11 is not used as an input combination.
NAND Latch

S
S Q

Q
R
R

S R S R Q Q State

1 0 0 1 1 0 SET

0 1 1 0 0 1 RESET
0 0 1 1 Q Q HOLD
1 1 0 0 1 1 INVALID
RS NAND Latch with Enable

S 1
Q

EN Hold State
0

1 Q
R

Enable S R Q Q State
S
S
0 x x Q Q Hold
Q
1 1 0 1 0 Set
EN 0 1 0 1 Reset
1
1 Q 1 0 0 Q Q Hold
R
1 1 1 0 0 Invalid
R
D latch

1 1 1
S Q D S Q
EN 1 EN
0
R Q 0
R Q

Enable S R Q Q State
0 x x Q Q Hold D Q
1 1 0 1 0 Set

1 0 1 0 1 Reset EN Q
1 0 0 Q Q Hold

1 1 1 0 0 Invalid

If EN = 1 then Q = D otherwise the latch is in Hold state

Latch with clock 1
zn
• A clock toggles periodically
between 0 and 1 1
• Discretizing the time D Q yn
clk
• Edge triggered RS flip-flops
• Edge triggered D flip-flops
• Edge triggered JK flip-flops

clk

Circuits are designed with the idea there would be single change in output
or memory state in single clock cycle. 13
Positive Edge Triggered Latch or Flip-flop

• Time synchronization across a

D Q large system
• Give sufficient time for info to
clk
be read
• There are no commas in
signal, so discrete time helps
separate consecutive bits

Clock

D
Negative Edge Triggered Latch or Flip-flop

D Q

clk

Clock

D
Master-Slave D Flip-flop

D D D Q

master slave
EN EN Q
The result is
a negative
clk
edge
triggered D
Flip Flop
Clock

D Q

Master clk

Slave
Characteristic table

• Given a input and the present state of the flip-flop, what is the
next state of the flip-flop.
• 𝑄 𝑡 + 1 as a function of 𝑄 𝑡 and inputs

D Q
Inputs (D) Q(t+1)
clk 0 0
1 1

Characteristic equation: Q(t + 1) = D

JK Flip-flop
Inputs J K Q(t+1)
J Q 0 0 Q(t)
0 1 0
clk
1 0 1
K
1 1 Q(t)

Characteristic equation: Q(t + 1) = JQ (t ) + K Q(t )

JK flip flop is refinement of RS flip flop where

indeterminate state of RS flip flop is defined in JK Flip Flop
JK Flip-flop (characteristic equation)

Q(t) J K Q(t+1)
0 0 0 0
0 0 1 0 1 1
0 1 0 1
1 1
0 1 1 1
1 0 0 1
1 0 1 0
Q(t + 1) = JQ (t ) + K Q(t )
1 1 0 1
1 1 1 0
Toggle or T Flip-flop

T Q
Inputs (T) Q(t+1)
clk
0 Q(t)
1 Q(t)

Characteristic equation: Q(t + 1) = T  Q(t )

T Q(t) Q(t+1)
0 0 0
0 1 1
1 0 1
1 1 0
 Excitation Table
• What inputs are required to effect a
particular state change
• Given 𝑄 𝑡 and 𝑄 𝑡 + 1 , find inputs

21
Toggle or T Flip-flop
Inputs (T) Q(t+1)
T Q 0 Q(t)
clk 1 Q(t)

Characteristic equation: Q(t + 1) = T  Q(t )

Excitation Table

Excitation Table Inputs

Q T Q(t+1) Q(t) Q(t+1) T
0 0 0 0 0 0
0 1 1 0 1 1
1 0 1 1 0 1
1 1 0
1 1 0 22
JK Flip-flop excitation table
Inputs
J K Q(t+1) Q(t) Q(t+1) J K
J Q 0 0 Q(t) 0 0 0 X
clk 0 1 0
0 1 1 X
1 0 1
K 1 1 Q(t) 1 0 X 1
Characteristic Table 1 1 X 0

Excitation Table
Q J K Q(t+1)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0 23