CEA - Computer Engineering

COMPORGA – COMPUTER ORGANIZATION AND ARCHITECTURE

MODULE 4: CONTROL UNIT

TOPIC: Learning Objective
In this module, we focus our attention on the main
● To identify the different
component of any computer system, the central
components of control
processing unit (CPU). The primary function of the CPU is
to execute a set of instructions stored in the computer’s system
memory. A simple CPU consists of a set of registers, an
● To understand the function
arithmetic logic unit (ALU), and a control unit (CU)
of control system

MODULE STRUCTURE: ● To create microinstruction

according to the structure
I. Central Processing Unit
of the control unit
a. Register set
b. Arithmetic Logic Unit
c. Control Unit
Resources Needed
II. Datapath Organization ● Access to the Internet
III. Control Unit Implementation
● Computer or mobile
a. Hardwired
device
b. Microprogrammed

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COMPORGA – COMPUTER ORGANIZATION AND ARCHITECTURE

I. CENTRAL PROCESSING UNIT

- Main component of any computer system

- Primary function is to execute a set of
instructions stored in the computer’s memory
- The control unit is the entity responsible for
fetching the instruction to be executed from
the main memory and decoding and then
executing it.

Major components:
• Register set
• Arithmetic Logic Unit
• Control Unit

The image below shows different components that makes up the CPU

a. Register Set - used to hold the address of a specific instruction

- combination of general purpose and special purpose registers
- differs from one computer architecture to

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b. Arithmetic Logic Unit - provides the circuitry needed to perform the arithmetic,
logical and shift operations demanded the instruction set.

c. Control Unit - the entity responsible for fetching the instruction to be executed
from the main memory and decoding and then executing it.

The CPU fetches instructions from memory, reads and writes data from and to memory,
and transfers data from and to input/output devices. A typical and simple execution
cycle can be summarized as follows:

1. The next instruction to be executed, whose address is obtained from the PC, is
fetched from the memory and stored in the IR.
2. The instruction is decoded.
3. Operands are fetched from the memory and stored in CPU registers, if needed.
4. The instruction is executed. 5. Results are transferred from CPU registers to the
memory, if needed.

INTERRUPT - caused either by a special instruction in the instruction set or by an

exceptional condition in the processor itself.
- It is an input signal to the processor indicating an event that needs
immediate attention

Ex. I/O device request, arithmetic overflow, or a page fault

When an interrupt request is encountered, a transfer to an interrupt handling

routine takes place

Interrupt handling routines are programs that are invoked to collect the state of the
currently executing program, correct the cause of the interrupt, and restore the state
of the program.

If there is an interrupt request waiting, the following steps take place:

1. The contents of PC are loaded into MDR (to be saved).

2. The MAR is loaded with the address at which the PC contents are to be
saved.
3. The PC is loaded with the address of the first instruction of the interrupt
handling routine.
4. The contents of MDR (old value of the PC) are stored in memory

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COMPORGA – COMPUTER ORGANIZATION AND ARCHITECTURE

II. DATAPATH ORGANIZATION

Datapath - is a set of functional units that carry out data processing operations.
- contains the registers and the ALU
- capable of performing certain operations on data items.
- Internal and external data movements
- organized using:
• One-bus
• two-bus
• three-bus Organization
- Dedicated datapaths may also be used between components that
transfer data between themselves more frequently

DATAPATH ORGANIZATION

• One-Bus Organization
- the CPU registers and the ALU use a single bus to move outgoing and
incoming data
- simplest and least expensive, but it limits the amount of data transfer
that can be done in the same clock cycle, which will slow down the
overall performance

• Two-Bus Organization
- Using two buses is a faster solution than the one-bus organization
- Data can be transferred from two different registers to the input point of
the ALU at the same time

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In some cases, one of the buses may be dedicated for moving data into
registers (in-bus), while the other is dedicated for transferring data out of the
registers (out-bus).

In-bus

moving data
into registers

Out-bus

transferring
data out of the
registers

• Three-Bus Organization
- two buses may be used as source buses (out-bus), while the third is used
as destination (in-bus).
- Each of the two out-buses is connected to an ALU input point
- The output of the ALU is connected directly to the in-bus

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The more buses, the more data can be move within a single clock cycle.
However, increasing the number of buses will also increase the complexity of
the hardware.

CPU INSTRUCTION CYCLE

- The basic actions during fetching an instruction, executing an instruction, or
handling an interrupt are defined by a sequence of micro-operations.

Example 1: Execute Simple Arithmetic Operation

Micro-Operation: Add R1, R2, R0

1. The registers R0, R1 , R2 , are extracted from the IR.

2. The contents of R1 and R2 are passed to the ALU for addition.
3. The output of the ALU is transferred to R0.

Example 2: Execute Simple Arithmetic Operation

Micro-Operation: Add X, R0

1. The memory location X is extracted from IR and loaded into MAR.

2. As a result of memory read operation, the contents of X are loaded into
MDR.
3. The contents of MDR are added to the contents of R0.

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III. CONTROL UNIT IMPLEMENTATION

Control Unit - directs the system operations by sending control signals to the
datapath.
- signals control the flow of data within the CPU and between the
CPU and external units such as memory and I/O
- Clock signals are used in generating control signals.

Two different types of control units are

Hardwired - fixed logic circuits that correspond directly to the Boolean

expressions are used to generate the control signals

Ex. Assume that the instruction set of a machine has the three
instructions: Inst-x, Inst-y, and Inst-z; and A, B, C, D, E, F, G, and H
are control lines

Draw the logic circuits for control lines A, B, and C

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Microprogrammed - the control signals associated with operations are stored in

special memory units inaccessible by the programmer as control
words

- The idea of microprogrammed control units was introduced by

M. V. Wilkes in the early 1950s.

- Microprogramming was motivated by the desire to reduce the

complexities involved with hardwired control

- The idea of microprogrammed control is to store the control

signals associated with the implementation of a certain instruction
as a microprogram in a special memory called a control memory
(CM)

- control signals are represented using bits

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- Decoders will reduce the number of control lines that can be

activated simultaneously

Horizontal Versus Vertical Microinstructions

- Horizontal microinstruction, individual bits in horizontal microinstructions

correspond to individual control lines.

- Vertical microinstruction, control lines are coded into specific fields within
a microinstruction

- It should be noted that no decoding is needed in horizontal

microinstructions while decoding is necessary in the vertical case

Ex. Consider the three-bus datapath shown. In addition to the PC, IR,
MAR, and MDR, assume that there are 16 general-purpose registers
numbered R0 –R15. Also, assume that the ALU supports eight functions
(add, subtract, multiply, divide, AND, OR, shift left, and shift right).

Consider the add operation Add R1, R2, R0, which adds the contents of
source registers R1, R2 , and store the results in destination register R0 . In
this example, we will study the format of the microinstruction under
horizontal organization.

Destination
2
8 functions

16 Registers

Source 1
Source 2

Add R1, R2, R0

Horizontal Organization: there is a control bit for each control line

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ALU
Add sub mul div and or sleft sright none

Source 1
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 PC IR MAR MDR

Source 2
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15

Destination
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 PC IR MAR MDR

Microinstruction: Add R1, R2, R0

1000000000 01000000000000000000 0010000000000000 10000000000000000000

Vertical Organization: decoder will be needed. Control lines are assigned with a set of
control bits.

*ALU takes 4 bits since there are 9 instructions (8 functions + 1 transfer) it performs

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*Source1, Source2 and Destination takes 5 bits

ALU SOURCE 1 SOURCE 2

DESTINATION

Microinstruction: Add R1, R2, R0

0001 00001 00010 0000

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Task 4.1 CONTROL UNIT IMPLEMENTATION

1. Hardwired approach:
Suppose that the instruction set of a machine has three instructions: Inst-1,
Inst-2, and Inst-3; and A, B, C, D, E, F, G, and H are the control lines. The
following table shows the control lines that should be activated for the three
instructions at the three steps T0, T1, and T2. Draw the logic circuit for A, B, C,
D, E, F, G, and H control line.

2. Microprogramming approach
Write down the microprogram for instructions Inst-1 for horizontal and vertical
representation.

Example: microprogram for instructions Ins-2

Horizontal:
Steps Inst-control lines
T0 T1 T2 A B C D E F G H

Answer: Inst-3
T0 E,H 100 00001000 00000001
T1 D,A,C 010 00010000 10000000 00100000

Vertical:
Steps (3 inst – 2 bits) Inst-control lines (8 bits – 3 bits
00 T0 000 A
01 T1 001 B
10 T2 010 C
11 - 011 D
100 E
101 F
110 G
111 H
Answer: Inst-3
T0 E,H 00 100 111
T1 D,A,C 01 011 000 010

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