Introduction to IC Design &
Combinational Circuit
Lecturer: Tzu-Hsuan, Hung
System Integration and Silicon Implementation (Si2) Lab
Institute of Electronics
National Yang Ming Chiao Tung University, Hsinchu, Taiwan
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I ntegrated
C ircuit
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Performance Power Area
Higher battery life
Power Longer using time
Lab 8: low power design
Processing more tasks
Lower cost
Lab1
Area Performance Reach complicated goal
Lab4
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Outline
Section 1 Introduction to design flow
Section 2 Basic Description of Verilog
Section 3 Behavior Models of Combinational circuit
Section 4 Simulations
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Outline
Section 1 Introduction to design flow
Section 2 Basic Description of Verilog
Section 3 Behavior Models of Combinational circuit
Section 4 Simulations
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How Does Hardware Accelerate System
Profiling
Profiling is a form of dynamic program analysis that measures the
space/time complexity of a program to aid program optimization.
By doing profiling we can find the most time-consuming part of the
system
Designers can implement this part in hardware instead of software
(Source: APM Zone)
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How Does Hardware Accelerate System - Example
An algorithm contains steps:
(1) (2) (3) (4)
Mathematical Analysis: Profiling
(1) : O(C) Running 1000 times takes 100sec
(2) : O(n) (1) : 5s
(3) : O(n2) (2) : 10s
(4) : O(n) (3) : 70s
(4) : 15s
Make ASIC for (3), easily accelerated by 100x
Profiling with ASIC : Running 1000 times
(1) : 5s
(2) : 10s
(3) : 0.7s + 0.3s (communication time) takes 31s
(4) : 15s
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How Does Hardware Accelerate System
Application Specific IC (ASIC)
Specially designed IC are much faster than general purpose CPU.
we can design dedicated datapath and controller for the time-
consuming part which requires less time
Field-Programmable Gate Array(FPGA)
As implied by the name itself, the FPGA is field programmable.
FPGA working as a microprocessor can be reprogrammed to
function as the graphics card in the field, as opposed to in the
semiconductor foundries.
(Source: sigenics) (Source: Xilinx)
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FPGA Example
FPGA
No fabrication is needed
Limited routing resources
(Source: PDA, Prof. Chen)
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ASIC Example
Cell-based Design Flow
use pre-designed logic cells (known as standard cells) and
micro cells (e.g. microcontroller)
designers save time, money, and reduce risk
Full-Custom Design Flow
Design every thing by yourself
Not our focus
Cell-based Full-Custom
Pro. Design speed Large design
is fast freedom
Con. Less design Design speed
freedom is slow
(Source: TSRI)
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Standard Cell Example
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Full-Custom Example
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Cell-based Design Flow
Specification Development
System Architecture
System models
RTL code development
Functional Verification RTL
Synthesis
Synthesis
Timing Verificaiton
Physical Synthesis/Place and Route
Physical Design
Physical Verification
Prototype System Integration and
Build and Test Software Test
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Cell-based Design Flow - RTL to GATE
Specify
Design a input/output
SPEC.
Calculator
relationship
1: Adder Write Verilog
RTL Code 2: Divider
3: Subtracter HDL Code
Pre-sim Make sure your Use Cadence Tool
Adder is working Ncverilog, irun
nWave
Choose suitable Run synthesis by
Synthesis components from
Design Compiler
standard cell library
Gate Level
Optimize result
Netlist
And Generate
Gate level netlist
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Cell-based Design Flow GATE to LAYOUT
4ns 3ns
Input Output
Gate Level
Netlist AND OR
Check correctness
Gate-sim after adding timing
information
Gate Level
Netlist
Decide each
Floorplan Components position
(Source: Intel i7-5960X processor floorpla
Placement Place transistor in
Best position
Routing Connect ports from
Different modules
Layout Cadence innovus tool
(Source: PDA, Prof. Chen)
ICLAB NCTU Institute of Electronics Ref1: https://timsnote.wordpress.com/digital-ic-design/ic-compiler/floorplan/
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Layout
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Cell-based Design Flow LAYOUT to CHIP
Layout 4ns 3ns
Check correctness
Input 6ns Output
Post-sim after adding wiring
timing information AND Wiring OR
Check all functional Design rule check (DRC)
Verification work and no violation
of manufacturability Layout verse schematic(LVS)
Tape out Give all files to
the foundry
TSMC
Fabricate your
Fabrication design
Packing
& Testing
Test the IC is work
(Source: MTK)
CHIP
ICLAB NCTU Institute of Electronics Ref1: https://www.iue.tuwien.ac.at/phd/rovitto/node10.html
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Cell-based Design Flow Summary
RTL Design SPEC.
Plan the furniture
You want to own RTL Code
in your room
Pre-sim
Synthesis
Synthesis
Gate Level
Choose the suitable Netlist
Furniture based on
Datasheet Gate-sim
P&R
P&R Layout
Produce Floorplan
Post-sim
And layout of Verification
your room Tape out
Fabrication TSMC
Construction Fabrication
And
Get your new room
Packing & Testing
CHIP (Source: MTK)
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Cell-based Design Tools
System and behavioral Synthesis and Verification
description (math. or building
module ) Synopsys
C/C++ / python RTL Compiler, Design Compiler
Matlab PrimeTime,
Cadence
BuildGates Extreme
Hardware based description Verplex (Formal Verification)
language
System C
SystemVerilog Physical Design and post-layout
Verilog simulation
Innovus (SoC Encounter)
RTL simulation and debug IC compiler
NC-Verilog, irun Calibre
nLint, Verdi Nanosim, HSIM, UltraSim: a high-
performance transistor-level
FastSPICE circuit simulator
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Outline
Section 1 Introduction to design flow
Section 2 Basic Description of Verilog
Section 3 Behavior Models of Combinational circuit
Section 4 Simulations
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What is Verilog?
Hardware Description Language
Hardware Description Language
Hardware Description Language
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Hardware Description Language
Hardware Description Language
we plan to design
Verilog and VHDL are both widely using in the IC company
The difference between HDL and other programming
brain during designing the modules
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Verilog
Basic Language Rules
Data type
Port Declare and Connect
Number Representation
Operators
Conditional Description
Concatenation
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Module
All modules run concurrently
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Combinational Circuits
The output of combinational circuit depends on the
present input only.
Combinational circuit can be used to do mathematical
computation and circuit control.
Combinational circuit
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Behavioral Modeling (1/3)
Data Assignment
Continuous Assignment for wire assignment
Imply that whenever any change on the RHS of the assignment
occurs, it is evaluated and assigned to the LHS. => assign
LHS RHS
Cont. assign
Procedural Assignment for reg assignment
data types may occur within always,
initial, task and function. These expressions are controlled by
triggers which cause the assignment to evaluate.
LHS RHS
Proc. assign
trigger
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Behavioral Modeling (2/3)
Using always construct (Proc. assignment)
assignment should be applied in topological order
Simulation from top to down
always@(a,b,x,c,d) begin
x = a & b;
trigger b
y = x | c | d;
end
Using assign construct (Cont. assignments)
assign y = x | c | d ;
assign x = a & b ;
Which is better?
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Behavioral Modeling: Example (3/3)
Using blocking assignments in always construct
Sensitivity list changes value (trigger)
a x
b
c y
d
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Basic Language Rules
Terminate lines with semicolon ;
Identifiers
Verilog is a case sensitive language
C_out_bar and C_OUT_BAR: two different identifiers
Starts only with a letter or an _(underline), can be any sequence of
letters, digits, $, _ .
e.g. 12_reg illegal !!!!
Comments
single line : //
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Naming Conventions
Common
Lowercase letters for signal names
Uppercase letters for constants
Abbreviation
clk sub-string for clocks
rst sub-string for resets
Suffix
_n for active-low, _z for tri-state, _a for async ,
Ex: rst_n => reset circuit at active-low
State Machine
[name]_cs for current state, [name]_ns for next state
Identical(similar) names for connected signals and ports
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Data Type (1/5)
4-value logic system in Verilog: 0, 1, X, or Z
0,1: means low or high signal
X:
Z : high-impedance, the signal is neither 0 nor 1.
Avoid X and Z !!!
Floating
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Data Type (2/5)
Wire (default = Z (high impedance, floating net))
A wire cannot store value, often use in combination circuit
1. Represent port connection between devices
wire clk,A,B;
BBQ bbq1(.clk(clk),.meat(A),.vegetable(B))
BBQ bbq2(.clk(clk),.meat(A),.vegetable(B))
2. Can not be use in procedure assignment:
wire C;
always@(*) begin
C = a+b; // wrong, C should be reg data type (X)
end
3. Only use
wire C;
assign C = a+b; // correct (O)
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Data Type (3/5)
Registers (default = X (unknown, should be initialized) )
A reg is a simple Verilog, variable-type register
represent abstract data storage element
Hold their value until explicitly assigned in an initial or always block
1. Only use in procedure
2. Does not imply a physical register
EX1
reg C;
always@(*) begin
C = a+b; // (O) This reg does not imply a physical register
end
EX2
reg C;
Always@(posedge clk) begin
C <= a+b; // (O) This reg imply a physical register
end
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Data Type (4/5)
Wire Reg
1. Port connection(in/out) 1. Port output(register out)
2. Assign (cont. assignment) 2. Always block (Proc. assignment)
3. Can declared as vector 3. Can declared as vector
4. Often use in Comb. circuit 4. Often use in Sequ. circuit
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Data Type (5/5)
Vectors and Arrays : the wire and reg can be
represented as a vector
Vectors: single-element with multiple-bit
wire [7:0] vec; 8-bit
Arrays: multiple-element with multiple-bit
reg [7:0] mem [0:1023] Memories (1k - 1byte)
Memory
(Array) Vector
:
: For this reason, we do not
use array as memory,
Memory component will be
introduced later
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Port Declare and Connect (1/3)
Interface is defined by ports
Port inside module declaration
input : input port, only wire can be assigned
output : output port, wire/reg can be assigned
inout : bidirectional port, only wire can be assigned
Port connection outside module
input : wire or reg can be assigned to connect into the module
output : only wire can be assigned to connect out of the module
inout : register assignment is forbidden neither in module nor out of
module [Tri-state]
wire
wire inout
wire or reg wire wire or reg wire
output input output input
Module Module Module
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Port Declare and Connect (2/3)
Modules connected by port order (implicit)
Order must match correctly. Normally, it not a good idea to connect ports
implicitly. It could cause problem in debugging when any new port is
added or deleted.
e.g. : FA U01( A, B, CIN, SUM, COUT );
Order is vital!
Modules connect by name (explicit) Use this!!!
Use named mapping instead of positional mapping
name shall match correctly.
e.g. : FA U01 ( .a(A), .b(B), .cin(CIN), .sum(SUM), .cout(COUT) );
Name Mapping
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Port Declare and Connect : Example (3/3)
module MUX2_1(out,a,b,sel,clk,rst);
input sel,clk,rst; mux.v Wire for port
input a,b; module test; connection
output out; reg out; //incorrect define
Wire for input
wire c; reg a,b;
reg a,b; //incorrect define reg clk,sel,rst;
reg out;
// 1. connect port by ordering
//Continuous assignment MUX2_1 mux(out,a,b,sel,clk,rst);
assign c = (sel a:b;
// 2. connect port by name
//Procedural assignment, MUX2_1 mux(.clk(clk), .reset(rst),
//only reg data type can be assigned value .sel(sel), .a(a), .b(b), .out(out));
always@(posedge rst or posedge clk)
begin initial begin
else out <= c; end
end endmodule
endmodule sub module test module
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Number Representation (1/2)
Number Representation
Format: <size> <base><value>
Base format: b(binary), o(octal), d(decimal) or h(hexadecimal)
4-bit, 10, decimal
If <size> is smaller than <value>, left-most bits of <value>are
truncated
6-
If <size> is larger than <value>, then left-most bits are filled based
on the value of the left-most bit in <value>
zzzz zzzz zzzz; xx xxxx;
0000 0001;
6- -
Default size is 32-bits decimal number
e.g.
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Number Representation(2/2)
Number Representation
Signed Value (Verilog-2001)
By default the signal is unsigned
e.g. wire signed [7:0] a;
Negative : -
e.g. 3 illegal
A 3-bit signed value would be declared as wire signed [2:0] A
Decimal Value
3
2
1
0
-1
-2
-3
-4
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Operators (1/4)
Operators
Arithmetic Description
A = B + C;
A = B C;
A = B * C;
A = B / C;
A = B % C; (modulus)
Shift Operator (logical)
A = B >> 2; -bit
A = B << 2; -bit
Shift Operator (arithmetic)
A = B >>> 2; signed
A = B <<< 2;
e.g. wire signed [3:0] A,B;
positions and sign-filled.)
A = B >>>2;
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Operators (2/4)
Unsigned Operation
Signed Operation
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Operators (3/4)
Unsigned / Signed Mix Operation
If there are one unsigned operator, the operation will be regard as
unsigned
Example:
Goal: Number need to be in 0~6
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Operators (4/4)
Bitwise operators: perform bit-sliced operations on vectors
~(4 b0101) = {~0,~1,~0,~1} = 4 b1010
4 0101 & 4 0011 = 4 b0001
Logical operators: return one-bit (true/false) results
!(4 b0101) = ~1 = 1 b0
Reduction operators: act on each bit of a single input vector
&(4 0101) = 0 & 1 & 0 & 1 = b0
Comparison operators: perform a Boolean test on two arguments
Bitwise Logical Reduction Comparison
~a NOT !a NOT &a AND Relational
a<b
a&b AND a && b AND ~& NAND a>b
a <= b
| OR a >= b
a|b OR a || b OR
[in]equality
a^b XOR ~| NOR a == b returns x when x or z
a != b in bits. Else returns 0
a ~^ b XNOR ^ XOR or 1
case [in]equality
a === b returns 0 or 1 based
Note distinction between ~a and !a a !== b on bit by bit
comparison
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Conditional Description (1/2)
If-then-else often infers a cascaded encoder
inputs signals with different arrival time
Priority inferred
used in proc. assignment
case infers a single-level mux
case is better if priority encoding is not required
case is generally simulated faster than if-then-else
used in proc. assignment
conditional assignment (? :)
?: c = sel ? a : b;
used in cont. assignment
same as if-else statement
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Conditional Description: Example (2/2)
d 0
c 1 0
b 0
1 out
sel Sel=10
a 1 a 00
Sel=01 b 01
Sel=00 c 10
d 11
2
Sel
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Concatenation
Concatenation
b[3]
a[7]
{} assign a = {b, c}; b[0]
c[3]
a[0]
c[0]
{{}} assign a = {2{c}};
a = b << 1;
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Gate-Level Modeling (1/3)
Primitive logic gate
and nand
or nor
xor xnor
can use without instance name i.e. and( out, in1, in2 ) ;
can use with multiple inputs i.e. xor( out, in1, in2, in3 ) ;
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Gate-Level Modeling (2/3)
Primitive logic gate
buf, bufif0, bufif1
not, notif0, notif1
can use without instance name i.e. buf( out, in ) ;
can use with multiple outputs i.e. not( out1, out2 ,in) ;
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Behavioral Model v.s. Gate Level Model
Gate Level Model Behavioral Model
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Coding style
Data has to be described in one always block
Muti-driver (not synthesizable)
A
always@* begin
A=B+C;
end
always@* begin
A=B+D;
end B+C B+D
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Coding style
use initial block in your design for synthesis
initial begin
A=B;
B=C;
end Initial use for PATTERN only!!
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Coding style
Avoid combinational loop
May synthesis a Latch in your circuit !! (Latch is non-edge
triggered, avoid)
always@* begin always@* begin
A=B; always@* begin
case(Q)
B=A;
end A=B;
endcase
A=C;
end
end
always@* begin
always@* begin
case(Q)
A=B;
default: A=D;
A=C;
endcase
else A=D;
end
end
Figure. (a) D-latch (b) D flip-flop
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Outline
Section 1 Introduction to design flow
Section 2 Basic Description of Verilog
Section 3 Behavior Models of Combinational circuit
Section 4 Simulations
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Simulation Environment
TESTBED.v
DESIGN.v PATTERN.v
Port declaration
input
data type declaration
Applying simulation
output
Display results
Can use behavior-level
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Simulation Environment (cont.)
TESTBED.v Just like a breadboard
`timescale 1ns/10ps
PATTERN.v
module TESTBED;
wire out,a,b,sel,clk,reset;
MUX2_1 mux(.out(out),.a(a),.b(b),.sel(sel)); Putting devices on the board and
PATTERN pat(.sel(sel),.out(out),.a(a),.b(b)); connect them together!
enmodule
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Simulation Environment (cont.)
PATTERN.v # CYCLE sel=1;
for(i=0;i<=3;i=i+1) begin
#CYCLE {a,b}=i;
module PATTERN(sel,out,a,b); #CYCLE $display( "sel=%b, a=%b, b=%b,
out=%b" , sel, a, b, out);
input out; end
output a,b,sel;
# CYCLE sel=0;
reg a,b,sel,clk,reset; for(i=0;i<=3;i=i+1) begin
integer i; # CYCLE {a,b}=i;
parameter CYCLE=10; # CYCLE $display( "sel=%b, a=%b, b=%b,
out=%b" , sel, a, b, out);
always #(CYCLE/2) clk = ~clk; end
initial begin # CYCLE $finish;
a=0;b=0;sel=0;reset=0;clk=0; end
#3 reset = 1;
#10 reset = 0; endmodule
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Simulation Environment (cont.)
Simulation command input waveforms
Verilog compile Your
Verilog
irun TESTBED.v -define RTL debug Verilog Test pattern
design
Invoke nWave output test data
nWave &
Stop the simulation and continue the simulation
Ctrl+z Suspend the simulation at anytime you want.(not terminate yet!)
jobs Here you can see the jobs which are processing with a index on
the left [JOB_INDEX]
kill
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nWave
Overview Cursor Marker
Tool Bar
Position Position Delta Zoom Scale Ruler
Pull Down
Menu
Signal
Window
Value Window Full Scale Ruler Scroll Bar
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nWave (cont.)
Open fsdb file
Use File command
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nWave (cont.)
Get signal
Use Signal Get Signals... command
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nWave (cont.)
Choose value format
On the value window click Left Button
Default : Hexadecimal
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nWave (cont.)
Reload nWave
Update fsdb file in Debussy database
File Reload
Hot key L (shift + l)
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Authors
2004 Chia-Hao Lee (matchbox@si2lab.org)
2006revised Yi-Min Lin (ymlin@si2lab.org)
2008revised Chien-Ying Yu (cyyu@si2lab.org)
2008revised Chi-Heng Yang (kevin@oasis.ee.nctu.edu.tw)
2009revised Yung-Chih Chen (ycchen@oasis.ee.nctu.edu.tw)
2010revised Liang-Chi Chiu (oboe.ee98g@nctu.edu.tw)
2012revised Shyh-Jye Jou
2014revised Sung-Shine Lee (sungshil@si2lab.org)
2018revised Po-Yu Huang
2019revised Wei Chiang
2020revised Ya-Yun Hou / Lien-Feng Hsu
2021revised Lin-Hung Lai (h123572119@gmail.com)
2022revised Tzu_Hsuan Hung (davidhung.c@nycu.edu.tw)
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