Sequential Circuits

NCTU-EE IC LAB Spring-2022

Lecturer: Heng-Yu Liu

 Outline

Section 1 Sequential Circuits

Section 2 Finite State Machine
Section 3 Timing
Section 4 Synthesis and Design Compiler

ICLAB NCTU Institute of Electronics

2
 Outline

Section 1 Sequential Circuits

Introduction
Syntax
Reset
Coding Style
Generate & For Loop

ICLAB NCTU Institute of Electronics

3
 Motivation
Progress so far : Combinational circuit
Output is only a function of the current input values

ICLAB NCTU Institute of Electronics

4
 Motivation
What if you were given the following design
specification:

Button When the button is pushed: light

1)Turn on the light if it is off
2)Turn off the light if it is on

discussed before?

ICLAB NCTU Institute of Electronics

5
 What is Sequential Circuit ?
Sequential circuit
Output depends not only on the current input values, but
also on preceding input values
It remembers sort of the past history of the system

How?
Registers(Flip-Flops)

ICLAB NCTU Institute of Electronics

6
 Flip-Flop Operation

Latch: level sensitive

CLK=1 : Q follows D
CLK=0 : Q holds

ICLAB NCTU Institute of Electronics

7
 Flip-Flop Operation

D flip-flop: edge triggered

flip-
flop

Positive latch v.s. positive D flip-flop

Latch D flip-flop

CLK CLK

D D

Q Q

ICLAB NCTU Institute of Electronics 8

 Coding Styles (1/3)

Example

always @(*)
begin
if(sel == 1) f = a;
else f = b;
end

always @(*)
begin
if(sel == 1) f = a;
end

ICLAB NCTU Institute of Electronics

7
 Coding Styles (2/3)

Avoid latches in combinational circuit

Avoid incomplete if-then-else
Avoid incomplete case statements
X Xcase(mode)
if(!rst_n) out = 0;

endcase

O Ocase(mode)
if(!rst_n) out = 0;

else out = default_out; default:

out = default_out;
endcase

ICLAB NCTU Institute of Electronics

10
 Coding Styles (3/3)

Avoid combinational feedbacks

Lead to unpredictable oscillated output
NOT allowed
X X
assign a=a+1; assign out_value=out;
always @(*) begin
X always @(*) begin case(mode)
a = a+1;
end
default:
Xalways @(*) begin
out = out_value;
endcase
if(in_a) a = c;
end
else a = a;
end

ICLAB NCTU Institute of Electronics

11
 Flip-Flop Data Type

Flip-flop: data storage element with 4 states (0,1, X, Z)

0: logic low
1: logic high 1 0
X: unknown, may be a 0,1, Z, or
Z
in transition X
Z: high impedance, floating state

Operations on the 4 states

Example: AND, OR, NOT gate
AND 0 1 X Z OR 0 1 X Z NOT output
0 0 0 0 0 0 0 1 X X 0 1
1 0 1 X X 1 1 1 1 1 1 0
X 0 X X X X X 1 X X X X
Z 0 X X X Z X 1 X X Z X

ICLAB NCTU Institute of Electronics 12

 Concept of Sequential Circuit

Most computations are done by combinational circuit

Sequential elements are used for storage
top design

D Q
D Q
Comb.
D Q
Comb.
inputs

outputs
D Q

D Q
Comb.
D Q D Q
Comb.

13
 Combinational v.s. Sequential
Combinational Sequential
always@(*) always@(posedge clk)
begin begin
if(sel) out = a; if(sel) out <= a;
else out = b; else out <= b;
end end

(sequential waveform)

ICLAB
ICLABNCTU
NCTUInstitute
InstituteofofElectronics
Electronics
14
 Outline

Section 1 Sequential Circuits

Introduction
Syntax
Reset
Coding Style
Generate & For Loop

ICLAB NCTU Institute of Electronics

15
 Assignment in Sequential Circuit

Non-blocking assignment
Evaluations and assignments are executed at the same time
without regard to orders or dependence upon each other
Syntax : <variable> <= <expression>;

Example

always @(posedge clk)

begin
q1 <= in;
q2 <= q1;
out <= q2;
end

ICLAB NCTU Institute of Electronics

16
 Assignment in Sequential Circuit

Blocking assignment
Evaluations and assignments are immediate and in order
Syntax : <variable> = <expression>;

Example

always @(posedge clk)

begin
q1 = in;
q2 = q1;
out = q2;
end

ICLAB NCTU Institute of Electronics

17
 Coding Styles

<=

always @(posedge clk) begin

out <= out+1;
end

always @(*) begin

if(sel) out = a;
else out = b;
end

18
 Outline

Section 1 Sequential Circuits

Introduction
Syntax
Reset
Coding Style
Generate & For Loop

ICLAB NCTU Institute of Electronics

19
 Synchronous Reset (1/2)
Register with synchronous reset
Syntax: always@(posedge clk)

always @(posedge clk) begin

reset
if (reset) c <= 0; clk
else c <= a+1; a 1 2 3 4
end c 0 2 3 4 5

Advantages
Glitch filtering from reset combinational logic

Disadvantages
0
c
May need a pulse stretcher
a+1
Guarantee a reset pulse wide enough
Larger area reset
Increasing critical path clk

ICLAB NCTU Institute of Electronics

20
 Synchronous Reset (2/2)

Advantage: glitch filtering

Comb. Circuit
before reset

ICLAB NCTU Institute of Electronics

21
 Asynchronous Reset
Register with asynchronous reset
Syntax: always @(posedge clk or posedge reset)

always @(posedge clk or posedge reset) reset

begin
if (reset) c <= 0;
clk
else c <= a+1; a 1 2 3 4
end c 0 2 3 0 4 5

Advantages
Reset is independent of clock signal
Reset is immediate
Less area a+1 c

Disadvantages
Noisy reset line could cause unwanted reset clk
Metastability

reset

ICLAB NCTU Institute of Electronics

22
 Coding Styles

Reset all signals to avoid unknown propagation

Xalways @(posedge clk) begin
// if(!rst_n) week <= 0;
week <= week+1;
end
always @(posedge clk) begin
if(!rst_n) day <= 0;
else day <= week * 7;
end

Avoid conditional resets

Xalways @(posedge clk or posedge reset or posedge a) begin
if (reset || a) q <= 0;

end

ICLAB NCTU Institute of Electronics

23
 Outline

Section 1 Sequential Circuits

Introduction
Syntax
Reset
Coding Style
Non-synthesizable code

ICLAB NCTU Institute of Electronics

24
 Coding Styles (1/2)

Naming should be readable

Synthesizable codes
assign, always block, called sub-modules, if-then-else, cases,
parameters, operators

Data has to be described in one always block

Multiple source drive is not valid Xalways @(posedge clk) begin
out <= out+1;
end
always @(posedge clk) begin
out <= a;
end
-
blocking assignment
always @(posedge clk) begin
if(reset) out = 0;
X else out <= out+in;
end
25
 Coding Styles (2/2)

Do not put many variables in one always block

Except shift registers or registers with similar properties
bad suggested
always @(posedge CLK) begin always @(posedge CLK) begin
q2 <= in; q2 <= in;
if(sel==0) out <= q2; end
else if(sel==1) out <= q3; always @(posedge CLK) begin
else out <= out; if(sel==0) out <= q2;
end else if(sel==1) out <= q3;
else out <= out;
end

Use FSM (Finite State Machine)

ICLAB NCTU Institute of Electronics

26
 Outline

Section 1 Sequential Circuits

Introduction
Syntax
Reset
Coding Style
Generate & For loop

ICLAB NCTU Institute of Electronics

27
Generate

28
For Loop
For loop in Verilog
Duplicate same function
Very useful for doing reset and iterated operation
Unrolling

29
Generate
How to use for loop with generate?
For loop in generate : four always blocks
Regular for loop : one always block

30
 Generate

always block in for loop with

genvar

4 always block
instance

ICLAB NCTU Institute of Electronics 31

 Outline

Section 1 Sequential Circuits

Section 2 Finite State Machine
Section 3 Timing
Section 4 Synthesis and Design Compiler

ICLAB NCTU Institute of Electronics

32
 Finite State Machine

Example: Vending machine

Coke $25
Pepsi $25 IDLE
Sprite $25
coin inserted
abort
coin inserted
Item Waiting
dispensed abort Coins

selection button sufficient coins

pressed
Waiting
Selection

ICLAB NCTU Institute of Electronics

33
 Finite State Machine

Finite state machine

Powerful model for describing a sequential circuit
Divide a sequential circuit operation into finite number of states.
A state machine controller can output results depending on the
input signal, control signal and states.
As different input or control signal changes, the state machine will
take a proper state transition.

State diagram

ICLAB NCTU Institute of Electronics

34
 Mealy and Moore Machines

Mealy machine
The outputs depend on the current state and inputs

Moore machine
The outputs depend on the current state only

ICLAB NCTU Institute of Electronics

35
 FSM Coding Style

Separate current state, next state and output logic

always @(posedge clk or negedge rst_n) begin
Current if (!rst_n) current_state <= IDLE;
State end
else current_state <= next_state;
Use parameters for readability
always @(*) begin
if(!rst_n) next_state=IDLE;
else begin
case(current_state)
STATE_1: begin
if (in==in_1) next_state=STATE_2;
else next_state=current_state;
Next State end
STATE_2

default: next_state=current_state;
endcase
end
end
always@(posedge clk or negedge rst_n) begin
Output if (!rst_n) out <= 0;
else if (current_state==STATE_3) out <= output_value;
Logic else out <= out;
end

36
 Why FSM?

FSM can be referred to as the controller and status of

the whole module

FSM
inputs

D Q
D Q
Comb.
D Q
Comb.

outputs
D Q

D Q
Comb.
D Q D Q
Comb.

37
 Outline

Section 1 Sequential Circuits

Section 2 Finite State Machine
Section 3 Timing
Section 4 Synthesis and Design Compiler

ICLAB NCTU Institute of Electronics

38
 Timing Check (1/3)

Setup time check

The $setup system task determines whether a data signal remains
stable for a minimum specified time before a transition in an
enabling, such as a clock event.

in this red region

Hold time check
The $hold system task determines whether a data signal remains
stable for a minimum specified time after a transition in an
enabling signal, such as a clock event.

in this red region

ICLAB NCTU Institute of Electronics

39
 Timing Check (2/3)

Metastability
 Timing Check (3/3)

Timing report: setup time

Timing report: hold time Slacks should be MET!

(non-negative)

ICLAB NCTU Institute of Electronics

41
 Outline

Section 1 Sequential Circuits

Section 2 Finite State Machine
Section 3 Timing
Section 4 Synthesis and Design Compiler

ICLAB NCTU Institute of Electronics

42
Recall: Design Flow

ICLAB NCTU Institute of Electronics

43
 Logic Synthesis

Logic synthesis
A process by which behavioral model of a circuit is turned into an
implementation in terms of logic gates
Synthesis = Translation+Mapping+Optimization
assign avg=sum/total;
always_ff @(posedge clk) Translat
begin e
sum=sum+score*weight;
end

HDL Source Map+Optimize

gate
count

Large

Small
Short Long latency
Target
Technology 44
 Design Compiler

Design compiler
A tool by Synopsys, Inc. that synthesizes your HDL designs (Verilog) into
optimized technology-dependent, gate-level designs.
It can optimize both combinational and sequential designs for speed, area,
and power. Libraries
Behavioral level Clock period
Input/output delay
RTL Code Design Constraints
Max area
Libraries
design.sv syn.tcl or *.sdc Optimization

Design Compiler Log File

syn.log

Gate level
Netlist File Standard Delay File Report Files
design_SYN.v design_SYN.sdf design.timing
design.area
Wrapper design.power
design_Wrapper.sv

45