Introduction to Macros and SRAM

NYCU-EE IC LAB Spring-2022

Lecturer: Yu-Wei Lu
 Outline

Section 1 Macro
(Intellectual property, IP)

Section 2 Hard IP: Memory

Behavior
Usage

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 Outline

Section 1 Macro
(Intellectual property, IP)

Section 2 Hard IP: Memory

Behavior
Usage

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 Introduction to Intellectual Property
Intellectual Property (IP) core
What: IP is a design of a logic function that specifies how the elements are interconnected
// e.g. square root
Why: A designer can develop more quickly by applying IPs
How: IPs may be licensed to another party
Soft macro(IP): Synthesizable RTL
Portable and Editable

Unpredictable in terms of performance, timing, area, or power

IP protection risks
Firm macro(IP): Netlist format
Performance optimization under a specific fabrication technology

Need not synthesizing (sometimes time wasting)

Hard macro(IP): Hardware (LEF, GDS2 file format)
Specifies the physical pathways and wiring ( proved under specific tech.)

Moving, rotating, flipping freedom but can't touch the interior (APR)

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Imagine that your design is for cellphone screen processing
Assume the resolution is 1920*1080, 24 bits per pixel
50M registers!!

Cellphone becomes large and power-consuming!

size power

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 Outline

Section 1 Macro
(Intellectual property, IP)

Section 2 Hard IP: Memory

Behavior
Usage

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Memory Hierarchy

Register

SRAM
On chip
Off chip
DRAM

Disk

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AMD Ryzen ZEN3

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 Memory
SRAM 6T SRAM
Read and Write Data only
Memory has less area than register
Memory is slower than register
Only one address can be accessed in the same
time (single port SRAM vs. dual port )

Single port SRAM I/O Description

Memory

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 SRAM Logic Table

OEN is a tri-state
buffer

Considering CLK Out enable Out disable

skew, Enable Chip enable Chip disable
Chip at least one Read Write

cycle before use

High-Z

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 Signal example

Write data 1 Write data 2 Read data

In address 1 In address 2 from address 1

Write finish Write finish Read finish

Q changed Q changed Q changed

WEN (write enable negative):

0 -> write
1 -> read

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Appendix-Write and read in order

Write Read

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Appendix-Write and read in order
A D A D A D A D
0 X 0 8 0 8 0 8
1 X 1 X 1 1 1 1
2 X 2 X 2 X 2 d
3 X 3 X Write
3 X 3 X Read

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 Design Tips
To avoid critical path causing timing violation
Add registers after the hard macro
Use enable signal to control output register to avoid reading unknown value
If a memory macro is used in your design, the timescale should
be set according to the timescale specified by memory file
Be aware of features and characteristics of hard macro before you
use it in your design

[ Behavior Simulation ]

comb Memory Reg comb

Only do when it is critical path

[ Gate-level Simulation ]

comb Memory comb

No need reg when it is not critical path

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 Memory generation example

Example :
Number of Words : 600
Number of Bits : 8

1. How many bits of input pins are needed?

2. How many bits of address are needed?

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 Memory generation example

Example :
Number of Words : 600
Number of Bits : 8

1. How many bits of input pins are needed?

2. How many bits of address are needed?

Answer :
D [7:0]
Q [7:0]
A [9:0]

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 Memory Compiler
NYCU-EE IC LAB Spring-2022

Lecturer: Yu-Wei Lu
 Outline

Section 1 GUI

Section 2 Script

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 Memory Compiler GUI steps

Step 1. Execute Xlaunch

https://sourceforge.net/projects/xming/

Step 2. Check No Access Control

Step 3. Press Next or Yes for all other pages

2.

1.

ICLAB NCTU Institute of Electronics 19

 Memory Compiler GUI steps
Step 4. Log in linux01.ee.nctu.edu.tw

Step 5. Connect to ee08

Using ssh to connect the server, which is
%ssh mem@ee08.ee.nctu.edu.tw pw: mem

in your account in other server

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 Memory Compiler GUI steps
Step 6: create your own directory
$ mkdir your_own_name (ex: iclabxxx)
$ cd your_own_name (ex: iclabxxx)

Step 7. run the following commands

$ setenv DISPLAY 140.113.x.x:0
$ /RAID2/EDA/memory/CBDK018_UMC_Artisan/orig_lib/aci/ra1sh_1/bin/ra1sh

IP must be 140.113.x.x
Press Y to allow requested access to the X server

ICLAB NCTU Institute of Electronics 21

 Memory Compiler Interface

(1)

(2)

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 Memory Compiler Parameter

Instance Name : memory name

Number of Words : number of entry for the designed memory
Number of Bits : number of bits for every entry
Frequency <MHz> : memory working frequency
Ring Width : power line width
Multiplexer Width : 4-to-1, 8-to-1, 16-to-1 multiplexer
Top Metal Layer : the highest level of metal can be used in memory

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 Memory Compiler

Memory Architectures

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 Memory Compiler

Example :
32 words, 2bit , Multiplexer Width = 8

64 words, 2bit , Multiplexer Width = 16

Hint: change multiplexer width to make footprint close to square.

(

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 Memory Compiler

Spec. PostScript Datasheet : data sheet (*.ps) (use ps2pdf for .pdf)
ASCII datatable : parameter table (*.dat)
For Verilog model : behavior model be synthesized)
designer
Synopsys model : library for synthesis & APR (*.lib)
For LVS Netlist : used for LVS
APR
GDSII Layout : layout file

(2)

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 Outline

Section 1 GUI

Section 2 Script

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 SRAM generation in this course
Step 1. Log in linux??.ee.nctu.edu.tw

Step 2. Connect to ee08

Using ssh to connect the server, which is
%ssh mem@ee08.ee.nctu.edu.tw pw: mem

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 SRAM generation in this course
Step 3. Copy the directory /template and name on your own
% cp -r template your_own_name (ex: iclabxxx)

Step 4. Generate the memory you need in your directory

% cd your_own_name (ex:iclabxxx)
% ./01_mem_gen.sh RAISH 256 33 16 200

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 SRAM generation in this course
Step 5. Copy the directory back to your account
$scp -r <your_mem_dir> <your_account>@linux01.ee.nctu.edu.tw:.

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 SRAM generation in this course

Step 6. Generate db file

Step 7. Match the syntax of v file

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 Use library compiler to generate
.db files from .lib files
Step 6. Generate (*.db) from (*.lib) for (xx.tcl) usage

Invoke Synopsys
% lc_shell

Once inside lc_shell, execute the following Synopsys commands

lc_shell> read_lib xxx.lib
lc_shell> write_lib -format db USERLIB -output xxx.db
Note: Name of (*.lib) and (*.db) must be the same.

Exit lc_shell
lc_shell> exit

After generating the Synopsys model (*.db), one can generate SDF

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 Match the syntax of *.v file to SDF
Step 7. Match the syntax

Specify the setup time and hold time by replacing

$setuphold(posedge CLK &&& re_data_flag,D[9], 1.000, 0.500, NOT_D9);
to
$setuphold(posedge CLK &&& re_data_flag,posedge D[9], 1.000, 0.500, NOT_D9);
$setuphold(posedge CLK &&& re_data_flag,negedge D[9], 1.000, 0.500, NOT_D9);

Specify the delay of io paths by replacing

(CLK => Q[0])=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);
to
(posedge CLK => (Q[0]:1'bx))=(1.000, 1.000, 0.500, 1.000, 0.500, 1.000);

Note
Input part includes CEN, WEN, A, and D
Output part includes CLK to Q, and OEN to Q

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Step6, 7 command with a single command

Step 6, 7 can be done with a single command.

Take care not to perform the same action twice.

(ex: manually changed an run the command again)

If you do wrong, you should redo from generating the memory.

Command: ./02_lib_gen_syntax_match.sh

With this command, the db file will be generated and .v file

will be changed automatically

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 Move files
Step 8. After you get .db file and .v file, put them to Exercise/04_MEM folder.

Step 9. Edit the file_list.f in /01_RTL/ folder.

For example

Then you can use them to run behavior simulation and synthesis.

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 Remind!

When using IP, information in lib file belong to certain module

name, so modifying module name in v file is forbidden.

can not modify

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 JasperGold Superlint
NYCU-EE IC LAB Spring-2022

Lecturer: Yu-Wei Lu
 Outline

Overview

Choose Configure Checks

Import Design File

Setup the Clock and Reset

Extract and Prove Superlint Checks

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 Overview
Superlint combines traditional RTL linting and formal analysis,
deriving rich property-based functional checks from the RTL
automatically.

Superlint includes comprehensive lint and DFT checks.

Two modes of superlint

Command line mode (batch mode)
Graphic User Interface(GUI) mode: user-friendly!!

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 Overview (cont.)
Invoke JasperGold Superlint:
By command % jg superlint &

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 Choose Configure Checks
Configure Checks to Run
Using the Application -> Configure Superlint Checks
Or press the button

Choose the configuration, then press OK

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 Import Design File

Analyze the Design

Using the Design -> Analyze RTL
Or press the button

Choose language
Choose the design
(Import other (.v) files used in your design e.g. RA1SH.v)

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If using DesignWare IP
bbox_m XXXX

Elaborate

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 Setup the clock and Reset

Setup the Clock

press the button

Right click the clock signal

and choose declare clock

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 Setup the clock and Reset (cont.)

Setup the Reset

press the button

Type in the reset signal

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 Extract and Prove Superlint Checks

Press the Button

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 Extract and Prove Superlint Checks

Then you can see the violation messages

Line corresponding to the

violation is highlighted in
Violation messages view the source code

Proof summary

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Extract and Prove Superlint Checks

Check the violation description

Double click the violation

message to view the
information

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