Programmable Interval Timer (8254)

Md. Momenul Haque

Lecturer
Dept. of CSE, RMU
 8254 Programmable Interval Timer
 The 8254 is a programmable interval timer/counter
designed for use with Intel microcomputer systems.
 It is a general purpose, multi-timing element that can
be treated as an array of I/O ports in the system
software.
 The 8254 solves one of the most common problems
in any microcomputer system, the generation of accurate
time delays under software control.
 Instead of setting up timing loops in software, the
programmer configures the 8254 to match his
requirements and programs one of the counters for the
desired delay.
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 8254 Programmable Interval Timer
 After the desired delay, the 8254 will interrupt the
CPU.
 Software overhead is minimal and variable length delays
can easily be accommodated.

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Programmable counter/ Interval timer
 Required to generate:
 accurate time delay,
 event counting,
 rate generation,
 complex wave form generation,
 complex motor control,
 etc. under software control.
 Also used in personal computer to generate:
 18.2 timer interrupts per seconds,
 refresh RAM at regular intervals,
 provides timer signals to other devices
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 Internal Block Diagram (8254)
 Contains:
 data bus buffer
 Is a bidirectional, 8-bit buffer
 Read/ write logic
 Accepts input from the system bus and
generates control signal for the other
functional blocks
 A control word register and Three 16
bit counters
 Each counter is individually
programmed to operate in different
modes and by writing separate control
into the control word register.
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 Internal Block Diagram (Counter)

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 Internal Block Diagram (Counter)
 The Counters are fully independent. Each Counter
may operate in a different Mode.
 The Control Word Register is shown in the figure; it
is not part of the Counter itself, but its contents determine
how the Counter operates.
 The status register, shown in Figure contains the current
contents of the Control Word Register and status of the
output and null count flag.
 The actual counter is labelled CE (for ‘‘Counting Element’’).
It is a 16-bit presettable synchronous down counter.
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 Internal Block Diagram (Counter)
 OLM and OLL are two 8-bit latches. OL stands for ‘‘Output
Latch’’. the subscripts M and L stand for ‘‘Most significant
byte’’ and ‘‘Least significant byte’’.
 Similarly, there are two 8-bit registers called CR and CR (for
M L

‘‘Count Register’’).
 The Control Logic is also shown in the diagram.
CLK n, GATE n, and OUT n are all connected to the
outside world through the Control Logic.

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Pins and Signals(8254)

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 Pins and Signals(8254)

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 Interfacing with the system bus(8254)

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 Operational Description

 After power-up, the state of the 8254 is undefined. The Mode,

count value, and output of all Counters are undefined.
 How each Counter operates is determined when it is
programmed. Each Counter must be programmed before it
can be used.
 Counters are programmed by writing a Control Word
and then an initial count.

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 Operational Description
 The Control Words are written into the Control Word
Register, which is selected when A1,A0 =11. The Control
Word itself specifies which Counter is being programmed.

 By contrast, initial counts are written into the Counters, not

the Control Word Register. The A1,A0 inputs are used to select
the Counter to be written into. The format of the initial count
is determined by the Control Word used.

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 Control Word Register (8254)

 Is determined to select and program a counter of 8254

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 Write Operations
• The programming procedure for the 8254 is very flexible.
Only two conventions need to be remembered:
1) For each Counter, the Control Word must be written
before the initial count is written.
2) The initial count must follow the count format specified
in the Control Word (least significant byte only, most
significant byte only, or least significant byte and then most
significant byte).

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 Read Operations
 There are three possible methods for reading the counters:
simple read operation, the Counter Latch Command, and the
Read-Back Command.
 The first method is to perform a simple read operation. To read
the Counter, which is selected with the A1, A0 inputs, the CLK
input of the selected Counter must be inhibited by
using either the GATE input or external logic. Otherwise, the
count may be in the process of changing when it is read, giving
an undefined result.

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 Counter Latch Command (8254)
 Like a Control Word, this
command is written
to the Control Word
Register, which is selected
when A1,A0 = 11. Also
like a Control Word, the
SC0, SC1 bits select one of
the three Counters, but
two other bits, D5 and D4,
distinguish this command
from a Control Word.

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 Counter Latch Command (8254)
 The selected Counter’s output latch (OL) latches the count
at the time the Counter Latch Command is received.
 This count is held in the latch until it is read by the CPU (or
until the Counter is reprogrammed).
 The count is then unlatched automatically and the OL
returns to ‘‘following’’ the counting element (CE).
 Multiple counter latch commands can be used to latch more
than one counter.
 Counter latch commands do not affect the programmed
mode of operation of the counter.

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 Read back command (8254)
 It permits the programmer to
check the

.
 The command is written into
the Control Word Register and
has the format shown in Figure
. The command applies to the
counters selected by setting
their corresponding bits D3,
D2, D1 = 1.

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 Read back command (8254)
 The read-back command may be used to latch multiple
counter output latches (OL) by setting the COUNT bit D5
= 0 and selecting the desired counter(s).
 Each counter’s latched count is held until it is read (or the
counter is reprogrammed).
 The counter is automatically unlatched when read, but
other counters remain latched until they are read.
 If multiple count read-back commands are issued to the
same counter without reading the count, all but the first are
ignored; i.e., the count which will be read is the count at
the time the first read-back command was issued.

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 Read back command (8254)
 The read-back command may be used to latch status information by
setting the STATUS bit D4 = 0 and selecting the desired counter(s).
 Status must be latched to be read. Status of a counter is accessed by
a read from the counter.

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 Read back command (8254)
 NULL COUNT bit D6 indicates when the last count
written to the counter register (CR) has been loaded
into the counting element (CE).
 Until the count is loaded into the counting element (CE), it can’t be
read from the counter.

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 Read back command (8254)

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 Mode Definitions

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 Modes of Operation:
Mode-0: interrupt on terminal count
 Mode 0 is typically used for event counting.
 After the Control Word is written, OUT is initially low, and will
remain low until the Counter reaches zero. OUT then
goes high and remains high until a new count or a new Mode 0
Control Word is written into the Counter.
 GATE =1 enables counting; GATE = 0 disables counting. GATE
has no effect on OUT.
 After the Control Word and initial count are written to a Counter,
the initial count will be loaded on the next CLK pulse. This CLK
pulse does not decrement the count, so for an initial count of N,
OUT does not go high until N +1 CLK pulses after the initial
count is written.

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 Modes of Operation:
Mode-0: interrupt on terminal count

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 Modes of Operation:
Mode-1: Hardware retrigger able one-shot
 A trigger signal in GATE activates the counting.
 OUT will be initially high. OUT will go low on the CLK
pulse following a trigger and will remain low until the
Counter reaches zero.
 If GATE is triggered again in between counting, then the
counter reloaded and starts counting from the beginning.
Thus called retrigger able.
 If a new count is written while output is low, then the
current one-shot has no affect unless the counter is
retriggered.
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 Modes of Operation:
Mode-1: Hardware retrigger able one-shot

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 Mode-1: Hardware retrigger able one-
shot

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 Modes of Operation:
Mode-2: Rate generator
 In this mode the counter acts as a divide by N counter
 The GATE has to be kept high.
 The counting starts after loading the count value.

 The output remains high for N-1 clock cycles and then goes low for
one clock cycle.
 The process is repeated until the GATE goes low and starts from the
beginning when GATE goes high again.
 If a new count is loaded in between counting, then the new value take
affect from the subsequence of counting.

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 Mode-2: Rate generator

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 Mode-2: Rate generator

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 Mode-2: Rate generator

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 Mode 3 : Square Wave Mode.
 Low N/2 high N/2 ((N+1)/2 if N odd)
 Mode 3 is similar to Mode 2 except for the duty cycle
of OUT. OUT will initially be high. When half the
initial count has expired, OUT goes low for the
remainder of the count. Mode 3 is periodic; the
sequence above is repeated indefinitely. An initial
count of N results in a square wave with a period of N
CLK cycles.

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 Mode 3 : Square Wave Mode.

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 Mode 3 : Square Wave Mode.

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 Mode 3 : Square Wave Mode.

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 Mode 4 : Software Triggered Strobe
 Starts upon loading the count
 OUT will be initially high. When the initial count
expires, OUT will go low for one CLK pulse and then
go high again. The counting sequence is ``triggered'’
by writing the initial count.

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 Mode 4 : Software Triggered Strobe

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 Mode 4 : Software Triggered Strobe

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 Mode 4 : Software Triggered Strobe

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 Mode 5 : Hardware Triggered Strobe
 0 to 1 pulse on GATE
 OUT will initially be high. Counting is triggered by a
rising edge of GATE. When the initial count has
expired, OUT will go low for one CLK pulse and then
go high again.

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 Mode 5 : Hardware Triggered Strobe

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 Mode 5 : Hardware Triggered Strobe

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 Mode 5 : Hardware Triggered Strobe

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 Thank You

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