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and Electronics Eng. Dept.
of Computer & Computer Eng. Dept.
Engineering

EXPERIMENT 9

COUNTERS

EQUIPMENT:

1- Y-0016 main unit.

2- Integrated Circuit Board: Y-0016 main unit, Y-0016-004D

3. Connection wires.

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PRELIMINARY WORK:

1. Read all explanations about this experiment given in the lab manual.

2. Have a look at your course notes and related books about the topics covered in this experiment.

3. By means of a digital simulation software test and verify the operation of the logic circuits shown in
the following table.
1 Fig. 8.5.(a). The 4 bit asynchronous binary up counter circuit.
2 Fig. 8.6.(a). MOD10 asynchronous up counter circuit.
3 Fig. 8.7.(a). The 4 bit asynchronous binary down counter circuit.

4. In the above table there are 9 figures numbered as Fig. 8.XX.(a) referring to the schematic diagrams
of experiments to be done. As preliminary work you are obliged to draw by hand using pencils an
application circuit provided in Fig. 8.XX.(b) for each schematic diagram given in Fig. 8.XX.(a). It is
recommended that you use red colour for Vcc, black colour for GND and other colours for other
connections.

5. Design MOD8 and MOD12 counters by using the 74LS93 counter ICs.

6. There are some questions to be answered in the report form for this experiment. Have a look at these
questions and try to answer them before coming for the experiment. The quiz you will take before the
experiment may contain some of these questions.

NOTE: You are obliged to have a copy of the page number 8_1 from “the experiment report
form 8” when you start doing this experiment.

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COUNTERS

OBJECTIVES:
1- Investigating the binary counters,
2- Observing their operation principles,
3- Getting to know the binary counter ICs 74LS93 and 4024.

PRELIMINARY INFORMATION:

In digital logic and computing, a counter is a device which stores (and sometimes displays) the number
of times a particular event or process has occurred, often in relationship to a clock signal. Counters are
the logic circuits that take specific state with the clock ticks applied to their inputs. They are widely
used in the digital electronics area. Some of those application areas are, Digital Clocks, Frequency
Counters, Decoders, Digital Alarms, Traffic Lights etc.

The base of the counters are logic circuits and the flip-flops. Generally counters are obtained with
cascade connection of flip-flops in a specific rule. With each clock tick the counter changes its state. A
counter composed of n flip-flops with no feedback may have 2n different states depending on the
number of clock ticks. For example, if 4 flip-flops are used in the counter structure, there will totally
be 24=16 different states. So, the counter can count from 0 to 15.

The total number of counts or stable states a counter can indicate is called MODULUS (MOD). For
instance, the modulus of a four-stage counter would be 1610, since it is capable of indicating 00002 to
11112. The term modulo is used to describe the count capability of counters; that is, modulo-16
(MOD16) for a four-stage binary counter, modulo-10 (MOD10) for a decade counter, modulo-8
(MOD8) for a three-stage binary counter, and so forth. Counters can be up counters, whose count
value increments, and down counters, whose count value decrements, A counter is usually considered
in conjunction with a finite-state machine (FSM). Fig. 8.1 shows an FSM for a 3 bit binary up counter.
In this figure each state (circle) represents a different count value. The counter will move from one
state to the next one with a clock signal. When the count value is 111 the counter is in its largest value
and with the next clock signal it moves from the value of 111 to the initial value, namely 000.
Counters can be divided into two groups: 1. asynchronous (ripple) counters, 2. synchronous counters.

Fig. 8.1. An FSM for a 3-bit binary up counter.

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ASYNCHRONOUS (RIPPLE) COUNTERS

OBJECTIVES:
1- Observing the operation principles of asynchronous counters,
2- Analyzing up and down counting,
3- Defining the counting limits.

PRELIMINARY INFORMATION:

Asynchronous counters are counters that are configured such that all flip-flops are not triggered
simultaneously by a common clock. Since each flip-flop in the counter is triggered by the flip-flop in
series before it, these counters are also referred to as ripple counters. There are many types of
asynchronous counters. An UP counter counts in an ascending sequence while a DOWN counter
counts in a descending sequence. A counter can also count UP and DOWN on command; such a
counter is known as an UP/DOWN counter.

Asynchronous counters are limited in speed since all the flip-flops are not synchronized by the same
clock. Therefore the propagation delay in each flip-flop often affects the counting sequence at very
high operation frequencies. The flip-flops used in asynchronous counters are usually “T” flip-flops or
JK or D type flip-flops that have been configured as T flip-flops.

Counter decoding is a technique that is used with asynchronous counters to stop or recycle the
counting sequence at a particular count. This involves a circuit known as a count decoder that monitors
the output of the counter for a particular count and resets the counter when that count is detected.

Asynchronous counters can be constructed from discrete flip-flops or are readily available in the form
of ICs. The IC implementations are designed so that the counters can be configured for a wide variety
of applications ranging from simple counting to frequency division.

The flip-flop output in an asynchronous counter is used to trigger the next flip-flop. In other words, all
the flip-flops except for the first one are triggered with the state transition of the previous flip-flops.
However, in synchronous counters the input ticks are applied to all the Clk inputs of the flip-flops at
the same time. The fact that a flip-flop changes state depends on the states of other flip-flops. All flip-
flops work in toggle mode in an asynchronous counter.

A 4-bit asynchronous binary up counter is shown in Fig. 8.2. It can be seen that this asynchronous
counter is composed of four JK flip-flops. All JK flip-flops are working in toggle mode. When J and K
inputs are 1, with each clock signal the output is toggled. The flip-flop storing the Least Significant Bit
(LSB) gets the Clk pulses. The flip-flops are falling edge triggered type, so the flip-flops change their
states with high to low transition () of the signal in their Clk input.

Fig. 8.2. 4-bit asynchronous binary up counter.

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Fig. 8.3. Sample timing diagram for a 4-bit asynchronous binary up counter.

Sample timing diagram for this counter is provided in Fig. 8.3. Observe the waveforms in Fig. 8.3 to
fully understand the operating principle of the 4-bit asynchronous binary up counter. Initially, all flip-
flop outputs are zero (0):

Q1=0 , Q2=0 , Q3=0 , Q4=0

When the Clk pulse 0 falls from “1” to “0”, the FF1 is triggered and its output becomes “1”. The Q
outputs of the other flip-flops are all at level “0” because suitable clock pulses haven't yet been applied
to their Clk inputs. So after the Clk pulse 0, flip-flop outputs are as follows:

Q1=1, Q2=0, Q3=0, Q4=0

When the 1st Clk pulse falls from “1” to “0”, the FF1 is triggered again and its output Q1 falls from
“1” to “0”. As the Q1 output is connected to the Clk input of the FF2, that input will see a high to low
transition which triggers the FF2 and makes the Q2 output “1”. (Q1 output is the triggering input of
FF2). So, with the 1st clock pulse the output of the FF1 becomes “0” and the output of the FF2
becomes “1”. Finally, after the 1st Clk pulse, flip-flop outputs are as follows:

Q1=0, Q2=1, Q3=0, Q4=0

With the 2nd clock pulse, the FF1 is once again triggered and has Q1 output as “1”. The other flip-flops
conserve their states. So after the 2nd Clk pulse, flip-flop outputs are as follows:

Q1=1, Q2=1, Q3=0, Q4=0

With the 3rd clock pulse the FF1 is again triggered and its Q1 output falls from “1” to “0”. Therefore
this negative transition (falling edge) will trigger the FF2 and its Q2 output will also fall from “1” to
“0”. With this negative transition the FF3 is also triggered and its Q3 output rises to “1”. So after the
3rd Clk pulse, flip-flop outputs are as follows:

Q1=0, Q2=0, Q3=1, Q4=0

And the rest of the counting operation is performed similarly.

With the 15th clock pulse all the flip-flops are reseted (cleared).
Q1=0, Q2=0, Q3=0, Q=0

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When the waveforms of Fig. 8.3 are examined it can be seen that the signal frequency of the output of
FF1 is 1/2, FF2 is 1/4, FF3 is 1/8 and FF4 is 1/16 of the input clock pulse. Consequently, the counters
can be used as frequency dividers.

In the asynchronous binary down counters, with each clock pulse the count value is decremented by 1.
For example, if a 4-bit binary down counter starts counting from 15, then it falls to 14, 13, 12, ..., 1, 0
with each clock pulse and then turns back to 15. In the circuit of Fig. 8.2, if we connect the Clk inputs
of the flip-flops (except for the first one) from the previous flip-flop's Q’ output and read the counting
value from the Q outputs the counter becomes a 4-bit binary down counter.

Modulus Counters with Asynchronous Recycling

Counters can be designed to have a number of states in their sequence that is less than the maximum of
2n. This type of sequence is called a truncated sequence. To obtain such a counter, one of the methods
that can be used is “recycling with respect to the modulus” technique. One common modulus for
counters with truncated sequences is ten (called MOD10). Counters with ten states in their sequence
are called decade counters. A decade counter with a count sequence of zero (0000) through nine
(1001) is a BCD decade counter because its ten-state sequence produces the BCD code. This type of
counter is useful in display applications in which BCD is required for conversion to a decimal readout.
To obtain a truncated sequence, it is necessary to force the counter to recycle before going through all
of its possible states. For example, the BCD decade counter must recycle back to the 000 state after the
1001 state. A decade counter requires four flip-flops (three flip-flops are insufficient because 23=8).
One way to make a BCD counter from a 4-bit asynchronous up counter is to modify its sequence as
shown in Fig. 8.4, which shows a Mod10 (decade or BCD) asynchronous up counter circuit obtained
by JK flip-flops. To force this counter to recycle after the count of nine (1001) is to decode count ten
with a NAND gate and connect the output of the NAND gate to the clear (R) inputs of the flip-flops, as
shown in Figure 8.4. Notice in Fig. 8.4 that only Q4 and Q2 are connected to the NAND gate inputs.
This arrangement is an example of partial decoding, in which the two unique states (Q4 = 1 and Q2 =
1) are sufficient to decode the count of ten because none of the other states (zero through nine) has
both Q4 and Q2 HIGH at the same time. When the counter goes into count ten (1010), the output of
the decoding gate goes LOW (both inputs are HIGH) and asynchronously resets all the flip-flops. Then
the count sequences start from the 0000 state with the next clock signal.

Fig. 8.4. MOD10 (decade or BCD) asynchronous up counter circuit.

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EXPERIMENT NO: 8.1

EXPERIMENT NAME: EXAMINATION OF 4 BIT ASYNCHRONOUS BINARY UP
COUNTER
Equipment:
1. Y-0016 main unit.
2. Integrated Circuits (ICs):
74LS76 Dual master-slave J-K flip-flops 2 ICs
3. Connection wires.

Fig. 8.5.(a). The 4 bit asynchronous binary up counter circuit (count_4bit_as_u).

Note1: Do not forget to connect the Vcc pins to +5 V and the GND pins to ground (GND) connection.
Note2: Make use of the ON/ON SWITCH as an SPDT switch.
Fig. 8.5.(b). The 4 bit asynchronous binary up counter – application circuit.

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Procedure:
1. Construct the circuit [as given in Fig. 8.5.(a) and] as drawn by you in Fig. 8.5.(b) and apply the
power. In the beginning of the experiment, position the SPDT switch such that it connects the clock
input of the counter from the PULSE output signal.

2. Set the inputs A and B as follows: A=0, B=1 (this means that all preset inputs of flip-flops are
active). Observe the outputs QD(MSB), QC, QB and QA(LSB) and the value shown in the
“HEXADECIMAL DECODER”. Note down your observations here. What does this process mean?

3. Set the inputs A and B as follows: A=1, B=0 (this means that all clear inputs of flip-flops are
active). Observe the outputs QD(MSB), QC, QB and QA(LSB) and the value shown in the
“HEXADECIMAL DECODER”. Note down your observations here. What does this process mean?

4. Set the inputs A and B as follows: A=1, B=1 (this means that clear and preset inputs of flip-flops are
inactive). By pressing the PULSE button generate clock signals and observe the outputs QD(MSB),
QC, QB and QA(LSB) and the value shown in the “HEXADECIMAL DECODER”. Note down your
observations in Table 8.1.
OUTPUTS HEX DECIMAL
PULSE
QD QC QB QA VALUE VALUE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Table 8.1.

7. Set the inputs A and B as follows: A=1, B=1. Position the SPDT switch such that it connects the
clock input of the counter from the TTL oscillator. Change the oscillator frequencies starting from 1
Hz., 10 Hz., 100 Hz., etc. and observe the operation of the counter. After which frequencies you
cannot observe the changing of count values by your eyes? Explain why?

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EXPERIMENT NO: 8.2

EXPERIMENT NAME: EXAMINATION OF MOD10 ASYNCHRONOUS UP COUNTER

Equipment:

1. Y-0016 main unit.

2. Integrated Circuits (ICs):

74LS00 Quad 2-input NAND gates 1 IC
74LS76 Dual master-slave J-K flip-flops 2 ICs

3. Connection wires.

Fig. 8.6.(a). MOD10 asynchronous up counter circuit (count_4bit_as_u_md10).

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Note1: Do not forget to connect the Vcc pins to +5 V and the GND pins to ground (GND) connection.
Note2: Make use of the ON/ON SWITCH as an SPDT switch.
Fig. 8.6.(b). MOD10 asynchronous up counter – application circuit.

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Procedure:

1. Construct the circuit [as given in Fig. 8.6.(a) and] as drawn by you in Fig. 8.6.(b) and apply the
power. In the beginning of the experiment, position the SPDT switch such that it connects the clock
input of the counter from the PULSE output signal.

2. Set the input A to the logic 1 state (this means that all preset inputs of flip-flops are inactive).

3. In order to produce a clock signal to be applied to the counter press the PULSE button. After
applying a clock signal observe the output of the counter and note down the output in Table 8.2.
Successively press the PULSE button until all flip-flop outputs are zero.

4. Describe the operation of this counter here.

OUTPUTS DECIMAL
PULSE
QD QC QB QA VALUE
CLEAR
1
2
3
4
5
6
7
8
9
10
11
12
Table 8.2.

5. Keep the input A at the logic 1 state (this means that all preset inputs of flip-flops are inactive).
Position the SPDT switch such that it connects the clock input of the counter from the TTL oscillator.
Change the oscillator frequencies starting from 1 Hz., 10 Hz., 100 Hz., etc. and observe the operation
of the counter.

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EXPERIMENT NO: 8.3

EXPERIMENT NAME: EXAMINATION OF 4 BIT ASYNCHRONOUS BINARY DOWN
COUNTER
Equipment:
1. Y-0016 main unit.
2. Integrated Circuits (ICs):
74LS76 Dual master-slave J-K flip-flops 2 ICs
3. Connection wires.

Fig. 8.7.(a). The 4 bit asynchronous binary down counter circuit (count_4bit_as_d).

Note1: Do not forget to connect the Vcc pins to +5 V and the GND pins to ground (GND) connection.
Note2: Make use of the ON/ON SWITCH as an SPDT switch.
Fig. 8.7.(b). The 4 bit asynchronous binary down counter – application circuit.

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Procedure:
1. Construct the circuit [as given in Fig. 8.7.(a) and] as drawn by you in Fig. 8.7.(b) and apply the
power. In the beginning of the experiment, position the SPDT switch such that it connects the clock
input of the counter from the PULSE output signal.

2. Set the inputs A and B as follows: A=1, B=0 (this means that all clear inputs of flip-flops are
active). Observe the outputs QD(MSB), QC, QB and QA(LSB) and the value shown in the
“HEXADECIMAL DECODER”. Note down your observations here. What does this process mean?

3. Set the inputs A and B as follows: A=0, B=1 (this means that all preset inputs of flip-flops are
active). Observe the outputs QD(MSB), QC, QB and QA(LSB) and the value shown in the
“HEXADECIMAL DECODER”. Note down your observations here. What does this process mean?

4. Set the inputs A and B as follows: A=1, B=1 (this means that clear and preset inputs of flip-flops are
inactive). By pressing the PULSE button generate clock signals and observe the outputs QD(MSB),
QC, QB and QA(LSB) and the value shown in the “HEXADECIMAL DECODER”. Note down your
observations in Table 8.3.

OUTPUTS HEX DECIMAL

PULSE
QD QC QB QA VALUE VALUE
PRESET
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Table 8.3

5. Set the inputs A and B as follows: A=1, B=1. Position the SPDT switch such that it connects the
clock input of the counter from the TTL oscillator. Change the oscillator frequencies starting from 1
Hz., 10 Hz., 100 Hz., etc. and observe the operation of the counter.

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74LS93 4 BIT ASYNCHRONOUS BINARY UP COUNTER

PRELIMINARY INFORMATION:
The 74LS93 is an example of a specific TTL IC asynchronous up counter. Fig. 8.8 shows the
schematic symbol, the logic diagram, the reset/count truth table and the count sequence of the 74LS93
4 bit asynchronous up counter IC. As the logic diagram in Fig. 8.8 shows, this device actually consists
of a single flip-flop and a 3-bit asynchronous counter. This arrangement is for flexibility. It can be
used as a divide-by-2 device if only the single flip-flop is used, or it can be used as a MOD8 counter if
only 3-bit counter is used. This device also provides gated reset inputs, MR1 and MR2. When both of
these inputs are HIGH, the counter is reset to 0000 state. The 74LS93 can be used as a 4-bit MOD16
counter (counts 0 through 15). It can also be configured as a decade counter (counts 0 through 9) with
asynchronous recycling by using the gated reset inputs MR1 and MR2.

Schematic Symbol

Logic Diagram

NC: Not Connected

Fig. 8.8. The schematic symbol, the logic diagram, the reset/count truth table and the count sequence
of the 74LS93 4 bit asynchronous up counter IC.

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EXPERIMENT NO: 8.4

EXPERIMENT NAME: EXAMINATION OF THE 74LS93 4 BIT ASYNCHRONOUS UP
COUNTER
Equipment:
1. Y-0016 main unit.
2. Integrated Circuit (IC):
74LS93 4 bit binary counter 1 IC
3. Connection wires.

Fig. 8.9.(a). The 74LS93 4 bit asynchronous up counter circuit (74LS93).

Note1: Do not forget to connect the Vcc pin to +5 V and the GND pin to ground (GND) connection.
Note2: Make use of the ON/ON SWITCH as an SPDT switch.
Fig. 8.9.(b). 74LS93 4 bit asynchronous up counter – application circuit.

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Procedure:
1. Construct the circuit [as given in Fig. 8.9.(a) and] as drawn by you in Fig. 8.9.(b) and apply the
power. In the beginning of the experiment, position the SPDT switch such that it connects the clock
input of the counter from the PULSE output signal.

2. Set the input A to the logic 1 state (this means that all clear inputs of flip-flops are active).
Successively press the PULSE button a few times. Then observe the output of the counter and note
down the output value here. What does this process mean?

3. Set the input A to the logic 0 state (this means that clear inputs of flip-flops are inactive). By
pressing the PULSE button generate clock signals and observe the outputs Q3(MSB), Q2, Q1 and
Q0(LSB) and the value shown in the “HEXADECIMAL DECODER”. Note down your observations
in Table 8.4.

OUTPUTS HEX DECIMAL

PULSE A
Q3 Q2 Q1 Q0 VALUE VALUE
1 0
2 0
3 0
4 0
5 0
6 0
7 0
8 0
9 0
10 0
11 0
12 0
13 0
14 0
15 0
16 0
17 0
18 0
Table 8.4.

4. Keep the input A at the logic 0 state (this means that clear inputs of flip-flops are inactive). Position
the SPDT switch such that it connects the clock input of the counter from the TTL oscillator. Change
the oscillator frequencies starting from 1 Hz., 10 Hz., 100 Hz., etc. and observe the operation of the
counter.

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EXPERIMENT NO: 8.5

EXPERIMENT NAME: EXAMINATION OF THE 74LS93 USED AS A BCD COUNTER
Equipment:
1. Y-0016 main unit.
2. Integrated Circuit (IC):
74LS93 4 bit binary counter 1 IC
3. Connection wires.

Fig. 8.10.(a). Configuration of the 74LS93 as a decade counter (74LS93).

Note1: Do not forget to connect the Vcc pin to +5 V and the GND pin to ground (GND) connection.
Note2: Make use of the ON/ON SWITCH as an SPDT switch.
Fig. 8.10.(b). Configuration of the 74LS93 as a decade counter – application circuit.

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Procedure:

1. Construct the circuit [as given in Fig. 8.10.(a) and] as drawn by you in Fig. 8.10.(b) and apply the
power. In the beginning of the experiment, position the SPDT switch such that it connects the clock
input of the counter from the PULSE output signal.

2. By pressing the PULSE button generate clock signals and observe the outputs Q3(MSB), Q2, Q1
and Q0(LSB) and the value shown in the “HEXADECIMAL DECODER”. Note down your
observations in Table 8.5.

DECIMAL
PULSE Q3 Q2 Q1 Q0
VALUE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Table 8.5.

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3. In the circuit shown below, design and implement a MOD8 counter. Then construct the circuit and
apply the power.

4. In the circuit shown below, design and implement a MOD12 counter. Then construct the circuit and
apply the power.

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4024 7 BIT ASYNCHRONOUS BINARY UP COUNTER

PRELIMINARY INFORMATION:

The 4024 is a 7 bit asynchronous binary up counter CMOS IC. Fig. 8.11 shows the schematic symbol
and the function table of the 4024 7 bit asynchronous up counter IC. The 4024 has an active HIGH
asynchronous master reset input (MR), a clock input (CP’) and seven fully buffered parallel outputs
(Q6, Q5, …, Q0). The counter advances (counts 0000000 through 1111111) on the HIGH to LOW
transition () of CP’. A HIGH on MR clears all counter stages and forces all outputs LOW,
independent of CP’. Each counter stage is a static toggle flip-flop.

Schematic Symbol

NC: Not Connected

Fig. 8.11. The schematic symbol and the function table of the 4024 7 bit asynchronous up counter IC.

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EXPERIMENT NO: 8.6

EXPERIMENT NAME: EXAMINATION OF 4024 7 4 BIT ASYNCHRONOUS UP COUNTER
Equipment:
1. Y-0016 main unit.
2. Integrated Circuit (IC):
4024 7 bit binary counter 1 IC
3. Connection wires.

Fig. 8.12.(a). The 4024 7 bit asynchronous up counter circuit (4024).

Note1: Do not forget to connect the VDD pin to +5 V and the VSS pin to ground (GND) connection
Note2: Make use of the ON/ON SWITCH as an SPDT switch.
Fig. 8.12.(b). The 4024 7 bit asynchronous up counter – application circuit.

DIGITAL DESIGN LABORATORY MANUAL – Experiment 8 Page 8_21

240
Prof. Dr. Murat UZAM 2015
 Faculty of Engineering and Architecture
ElectricalDeparment
and Electronics Eng. Dept.
of Computer & Computer Eng. Dept.
Engineering

Procedure:
1. Construct the circuit [as given in Fig. 8.12.(a) and] as drawn by you in Fig. 8.12.(b) and apply the
power. In the beginning of the experiment, position the SPDT switch such that it connects the clock
input of the counter from the PULSE output signal.

2. Set the input A to the logic 1 state (this means that all clear inputs of flip-flops are active).
Successively press the PULSE button a few times. Then observe the outputs of the counter, i.e.
Q6(MSB), Q5, Q4, Q3, Q2, Q1 and Q0(LSB), and note down the output value here. What does this
process mean?

3. Set the input A to the logic 0 state. By pressing the PULSE button generate clock signals and
observe the counter outputs Q6(MSB), Q5, Q4, Q3, Q2, Q1 and Q0(LSB). Note down your
observations in Table 8.6. What does this process mean?

4. Keep the input A at the logic 0 state. Position the SPDT switch such that it connects the clock input
of the counter from the TTL oscillator. Change the oscillator frequencies starting from 1 Hz., 10 Hz.,
100 Hz., etc. and observe the operation of the counter. Discuss the results obtained in this step.

5. Keep the input A at the logic 0 state. Position the SPDT switch such that it connects the clock input
of the counter from the TTL oscillator. Remove the logic switch A from the MR input. Then
sequentially connect the outputs from Q1 to Q6 to the MR input and observe the count values for each
connection. For each connection chose an appropriate clock signal from the TTL oscillator. Note down
the different count sequences here. Discuss the results obtained in this step.
When Q1 is connected to MR the counter counts ……..
When Q2 is connected to MR the counter counts ……..
When Q3 is connected to MR the counter counts ……..
When Q4 is connected to MR the counter counts ……..
When Q5 is connected to MR the counter counts ……..
When Q6 is connected to MR the counter counts ……..

6. Connect the logic switch A to the MR input and set the input A to the logic 0 state. Remove the CP
input from the SPDT switch. Then connect the CP input to one of the unused “TTL BINARY
SWITCH”es (i.e., B, C, …, or L). This means that the clock input of the counter will be provided from
one of the TTL binary switches rather than TTL PULSE input or TTL OSCILLATOR. Then, toggle
the binary switch used as the clock input from the ON state to the OFF state only once and observe the
output of the counter, i.e. Q6(MSB), Q5, Q4, Q3, Q2, Q1 and Q0(LSB). Does the counter increment
only one count value? If not explain what this means.

DIGITAL DESIGN LABORATORY MANUAL – Experiment 8 Page 8_22

241
Prof. Dr. Murat UZAM 2015
 Faculty of Engineering and Architecture
ElectricalDeparment
and Electronics Eng. Dept.
of Computer & Computer Eng. Dept.
Engineering

INPUTS OUTPUTS
PULSE A Q6 Q5 Q4 Q3 Q2 Q1 Q0 DECIMAL
0 0 0 0 0 0 0 0 0 0
1 0
2 0
3 0
4 0
5 0
6 0
7 0
8 0
9 0
10 0
11 0
12 0
13 0
14 0
15 0
20 0
25 0
30 0
35 0
40 0
45 0
50 0
55 0
60 0
65 0
70 0
75 0
80 0
85 0
90 0
95 0
100 0
105 0
110 0
115 0
120 0
128 0
Table 8.6.

DIGITAL DESIGN LABORATORY MANUAL – Experiment 8 Page 8_23

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Prof. Dr. Murat UZAM 2015