Computer Architecture
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Epshita MoitraChapter - 1.a.
(Computer Organization)
Computer Types
In computer architecture, various types of computers are designed and
classifiedbasedontheirprocessingpower,size,andusage.Here'sanoverview
of the main types:
. Microcomputers (Personal Computers)
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These are the most common type of computers, used by individuals and
businesses for general tasks such as wordprocessing,internetbrowsing,and
gaming.
● Desktop Computers: Designed for regular use at a single location.
● Laptops: Portable computers with an integrated screen and keyboard.
● Tablets:Portable,touchscreendevicesoftenusedformediaconsumption
and light productivity tasks.
. Minicomputers
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Minicomputers, also known as mid-range computers, are more powerfulthan
microcomputers but less powerful than mainframes. They are used in
situationsthatrequiremoreprocessingpowerthanpersonalcomputersbutdo
not necessitate the power of a mainframe. Typical uses include scientific
calculations, engineering simulations, and managing small to medium-sized
business operations.
. Mainframe Computers
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Mainframes are large, powerful systems used primarily bylargeorganizations
for bulk data processing, such as census data, transaction processing, and
enterprise resource planning. They are known for their high reliability,
scalability, and ability to handle thousands of simultaneous users and
applications.
. Supercomputers
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These are the most powerful computers in terms of processing capability.
Supercomputers are used for highly complex simulations and calculations,
suchasclimatemodeling,quantummechanicssimulations,andcryptanalysis.
They consist of thousands of processors working in parallel.
. Workstations
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Workstations are high-performance computers intended for technical or
scientific applications. They are used for tasks requiring significant
computational power, such as 3D rendering, engineering simulations, and
complex data analysis.
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. Servers
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Servers are computers designed to manage network resources and provide
services to other computers (clients) over a network. They come in various
forms:
● Web Servers: Serve web pages to users.
● File Servers: Store and manage files.
● Database Servers: Manage databases.
● Application Servers: Run applications and provide services to end-users.
. Embedded Systems
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Embeddedsystemsarespecializedcomputingsystemsthatarepartofalarger
device.Theyperformdedicatedfunctionswithinthedevice,suchascontrolling
automotive systems, household appliances, and industrial machines.
. Microcontrollers
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Microcontrollers are compact integrated circuits designed to govern specific
operations in embedded systems. They contain a processor, memory, and
input/outputperipheralsonasinglechipandareusedinapplicationssuchas
controlling home appliances, medical devices, and remote controls.
. Quantum Computers
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Quantum computers use quantum-mechanical phenomena, such as
superposition and entanglement, to perform computations. They have the
potential to solve certain problems much faster than classical computers.
Quantum computers are still largely experimental but hold promise for
breakthroughs in fields like cryptography and complex system modeling.
0. Edge and Fog Computing Devices
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These are part of a newer paradigm where computing resources are
decentralized.Edgecomputinginvolvesprocessingdatanearthesourceofdata
generation (e.g., IoT devices), while fog computing extends cloud computing
capabilities to the edge of the network.
Structure with basic computer components
basic computer structure consists of several key components that work
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together to perform computations and process data. Here are the main
components typically found in a computer system:
. Central Processing Unit (CPU)
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The CPU is the brain of the computer, responsible for executing instructions
and processing data. It consists of two main parts:
● Arithmetic Logic Unit (ALU): Performs arithmetic and logical operations.
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● C ontrol Unit (CU): Directs the operation of the processor by fetching
instructions from memory, decoding them, and executing them.
. Memory
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Memory stores data and instructions that the CPU needs to execute tasks.
There are different types of memory:
● PrimaryMemory(RAM):RandomAccessMemoryisvolatilememoryused
for temporarily storing data and instructions that the CPU is currently
processing.
● CacheMemory:Asmaller,fastertypeofvolatilememorylocatedinsideor
very close to the CPU to speed up access to frequently used data.
● Read-Only Memory (ROM): Non-volatile memory that stores critical
bootstrapping instructions required when the computer is powered on.
. Storage
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Storage provides long-term data retention. Unlike RAM, it retains data even
when the computer is turned off. Types include:
● Hard Disk Drives (HDD): Traditional magnetic storage devices with
spinning disks.
● Solid State Drives (SSD): Faster, flash-based storage devices with no
moving parts.
. Input Devices
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Input devices allow users to interact with the computer and input data.
Common input devices include:
● Keyboard: For typing text and commands.
● Mouse: For pointing, clicking, and dragging objects on the screen.
● Scanner: For digitizing physical documents and images.
. Output Devices
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Output devices present data from the computer to the user. Common output
devices include:
● Monitor: Displays visual output from the computer.
● Printer: Produces hard copies of digital documents.
● Speakers: Output sound.
. Motherboard
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ThemotherboardisthemaincircuitboardthathousestheCPU,memory,and
othercriticalcomponents.Itprovidesconnectorsforadditionalperipheralsand
expansion cards.
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. Power Supply Unit (PSU)
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The power supply unit converts electrical power from an outlet into usable
power for the internal components of the computer. It providesthenecessary
voltages and currents to different parts of the computer.
. Graphics Processing Unit (GPU)
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A specialized processor designed to accelerate the rendering of images and
videos. It is crucial for gaming, video editing, and applications requiring
complex graphical computations.
. Network Interface Card (NIC)
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A hardware component that connects a computer to a network. It can be
integrated into the motherboard or added as an expansion card.
0. Cooling System
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Components like fans, heat sinks, and sometimes liquid cooling systemsthat
help dissipate heat generated by the CPU, GPU, and other components to
prevent overheating.
1. Expansion Slots and Cards
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Slots on the motherboard where additional cards can be inserted to add
functionality to the computer. Common types include:
● PCI (Peripheral Component Interconnect): For connecting hardware like
sound cards, network cards, etc.
● PCIe (PCI Express): A faster version of PCI used for high-speed
components like graphics cards.
iagram of Basic Computer Components
D
Here’s a simple diagram illustrating the structure of a basic computer
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Description
● Input Devices (keyboard, mouse) send data to the motherboard.
● Motherboard hosts the CPU and RAM.
● CPU processes data and instructions from RAM and storage.
● RAM provides temporary storage for data and instructions.
● Storage (HDD/SSD) holds data permanently.
● GPU handles graphics processing tasks.
● NIC manages network connections.
● Output Devices (monitor, printer) receive processed data from the
motherboard.
Function in brief with instruction fetch and execute
he basic function of a computer is to execute programs, which involves
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performing a sequence of instructions stored in memory. This processcanbe
broken down into two main phases: instruction fetch and instruction
execution. Here’s a brief overview of these phases:
. Instruction Fetch
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The instruction fetch phase involves retrieving aninstructionfrommemoryto
be executed. This phase includes the following steps:
1. Program Counter (PC) Points to the Instruction: The Program Counter
holds the address of the next instruction to be executed.
2. Fetch the Instruction: The instruction at the memory address specified
by the PC is fetched and placed into the Instruction Register (IR).
3. Increment the Program Counter: The PC is incremented to point to the
address of the next instruction in the sequence.
. Instruction Execute
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The instruction execution phase involves decoding and carrying out the
instruction fetched during the fetch phase. This phase includes the following
steps:
1. Decode the Instruction: The Control Unit decodestheinstructioninthe
Instruction Register to determine what actions are required.
2. Fetch Operands: If the instruction requires data operands (e.g., adding
two numbers), these are fetched from the appropriate registers or
memory locations.
3. Execute the Instruction: The ALU or other appropriate units within the
CPU perform the required operation (e.g., arithmetic operation, logical
operation, data transfer).
4. Store the Result: The result of the operation is stored in the specified
register or memory location.
5. UpdatetheProgramCounter:ThePCmaybeupdatedbasedonthetype
of instruction executed (e.g., jumps, branches).
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asic Computer Function: Fetch-Execute Cycle
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The fetch-execute cycle is a continuous process thatformsthecoreoperation
of a CPU. Here’s a step-by-step description of the cycle:
1. Fetch Phase:
● The CPU fetches the next instruction from the memory address
stored in the Program Counter (PC).
● The instruction is placed into the Instruction Register (IR).
● The Program Counter is incremented to the address of the next
instruction.
2. Decode Phase:
● The Control Unit decodes the instruction in the Instruction
Register to determine the operation and the operands involved.
3. Execute Phase:
● Basedonthedecodedinstruction,theCPUperformsthenecessary
operation. This might involve:
● Arithmetic operations (addition, subtraction)
● Logical operations (AND, OR)
● Data transfer (loading data from memory to a register,
storing data from a register to memory)
● Control operations (jump, branch)
● The results are stored in the appropriate location (register or
memory).
4. Repeat:
● The cycle repeats, beginning again with the fetch phase for the
next instruction.
Diagram of the Fetch-Execute Cycle
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Explanation:
● Fetch Phase:
● The Program Counter (PC) holds the address of the next
instruction.
● TheaddressissenttotheMemoryAddressRegister(MAR),andthe
instruction at that address is loaded into the InstructionRegister
(IR).
● The PC is incremented to prepare for the next instruction.
● Decode Phase:
● The Control Unit decodes the instruction in the IR tounderstand
the required operation.
● If necessary, operands are fetched from registers or memory.
● Execute Phase:
● The ALU or other CPU components perform the operation.
● The result is stored in the appropriate location (register or
memory).
● The PC is updated if the instruction involves branching or
jumping.
his fetch-execute cycle continues until the program ends, with the CPU
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repeatedly fetching, decoding, and executing instructions.
Interrupts and I/O communication
I nterrupts
Interrupts are signals that temporarily halt the CPU's current operations to
attend to a higher-priority task. They are crucial for handling asynchronous
events efficiently. Here's how interrupts work:
Types of Interrupts
1. Hardware Interrupts: Triggered by hardware devices (e.g., keyboard,
mouse, network cards) to signal that they need CPU attention.
2. Software Interrupts: Generated by software instructions to request a
system service or to switch tasks.
3. Exceptions (Traps): Triggered by the CPU itself when it detectsanerror
or specific condition (e.g., divide by zero, invalid opcode).
Interrupt Handling Process
1. Interrupt Signal: An interrupt signal is sent to the CPU.
2. InterruptAcknowledgment:TheCPUfinishesthecurrentinstructionand
acknowledges the interrupt.
3. Save State: The CPU saves the current state (e.g., program counter,
registers) so it can resume later.
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4. Interrupt Vector Table: The CPU uses the interrupt vector table to find
the address of the interrupt service routine (ISR).
5. ExecuteISR:TheCPUjumpstotheISRandexecutesthecodetohandle
the interrupt.
6. Restore State: After the ISR is complete, the CPU restores the saved
state.
7. Resume Execution: The CPU resumes the execution of the interrupted
program.
I /O Communication
Input/Output(I/O)communicationinvolvestransferringdatabetweentheCPU
andperipheraldevices(e.g.,keyboard,mouse,printers,storagedevices).There
are several methods to facilitate this communication:
I/O Methods
1. Polling: The CPU repeatedly checks the status of a peripheral device to
see if it needs attention. This method is simple but inefficient, as it
wastes CPU time.
2. Interrupt-Driven I/O: Devices signal the CPU with an interrupt when
they need attention. This method is more efficient than pollingbecause
the CPU can perform other tasks until an interrupt occurs.
3. Direct Memory Access (DMA): A DMA controller transfers data between
memoryandaperipheraldevicewithoutinvolvingtheCPU,freeingitfor
other tasks.
I/O Ports and Interfaces
● Memory-MappedI/O:UsesthesameaddressspaceformemoryandI/O
devices. The CPU can use regular memory instructions to interact with
I/O devices.
● Port-Mapped I/O (Isolated I/O): Uses a separate address space for I/O
devices, requiring special instructions (e.g., IN, OUT) for communication.
I/O Device Categories
1. Input Devices: Provide data to the computer (e.g., keyboard, mouse,
scanners).
2. OutputDevices:Receivedatafromthecomputer(e.g.,monitors,printers,
speakers).
3. StorageDevices:Storedatapermanentlyortemporarily(e.g.,harddrives,
SSDs, USB drives).
4. CommunicationDevices:Enabledataexchangebetweencomputers(e.g.,
network cards, modems).
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Interconnection Structure
heinterconnectionstructureincomputerarchitecturereferstothesystemof
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pathways and protocols that connect the various components of a computer,
allowing them to communicate and transfer data.Thisstructureiscrucialfor
ensuring efficient data flowbetweentheCPU,memory,I/Odevices,andother
peripheral components. Here’s an overview of the interconnection structures:
. Bus Interconnection
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A bus is a common pathway used for communication between multiple
components. There are several types of buses in a typical computer system:
Types of Buses
1. Data Bus: Carries the data between the CPU, memory, and peripherals.
2. AddressBus:Carriestheaddressesofdata(locationsinmemory)sothat
the CPU knows where to read or write data.
3. Control Bus: Carries control signals, including read/write signals and
interrupt requests, to coordinate the activities of the CPU and
peripherals.
Bus Organization
● Single Bus Structure: A single bus connects all the components. It is
simple but can become a bottleneck as more devices are added.
● Multiple Bus Structure: Multiple buses (e.g., separatedataandaddress
buses) can alleviate bottlenecks and improve performance.
●
2. Crossbar Switch
Acrossbarswitchprovidesagrid-likeinterconnectionbetweenmultipleinputs
and outputs. Each intersection has a switch that can connect aninputtoan
output, allowing multiple simultaneous data transfers.
Advantages
● High performance and parallel data transfer.
● Flexible and scalable interconnections.
Disadvantages
● Complex and expensive to implement.
● Not typically used for general-purpose computing due to cost and
complexity.
. Multistage Interconnection Networks (MINs)
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MINs use multiple stages of switches to connect inputs to outputs. These
networks provide a compromise between the simplicity of buses and the
complexity of crossbars.
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Types of MINs
1. OmegaNetwork:Consistsofmultiplestagesof2x2switchesarrangedin
a pattern that allows efficient routing.
2. Butterfly Network: A specific type of MIN that is commonly used in
parallel processing systems.
. Point-to-Point Interconnects
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Point-to-point interconnects provide direct connections between pairs of
components. This structure is often used in high-performance systems to
reduce latency and increase bandwidth.
Examples
● HyperTransport: Used in AMD processors for connecting the CPU to
other components.
● QuickPath Interconnect (QPI): Used in Intel processors for high-speed
data transfer between the CPU and other components.
. Network-on-Chip (NoC)
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In modern multi-core processors, a Network-on-Chip is used to connect the
multiple cores and other components on a single chip. NoC uses
packet-switched networks to manage communication efficiently.
Diagram of Basic Interconnection Structure
Here’s a simplified diagram showing the interconnection structure of a
computer system:
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Description
● System Bus: The central bus that connects the CPU, RAM, and I/O
devices. It typically includes data, address, and control lines.
● CPU: The central processing unit, connected tothesystembusfordata
exchange.
● RAM: The main memory, connected to the system bus for data storage
and retrieval.
● I/O Devices: Various input/output devicesconnectedtothesystembus
for communication with the CPU and memory.
● Cache:Ahigh-speedmemorylocatedbetweentheCPUandRAMtospeed
up data access.
● I/O Controllers: Manage the data exchange between the CPU and
peripheral devices.
I nterconnection Strategies
1. Single Bus System
● Simplest interconnection structure.
● All components share a common bus.
● Can become a bottleneck as more devices are added.
2. Multiple Bus System
● Separate buses for different types of data (e.g., data bus, address bus,
control bus).
● Reduces contention and improves performance.
3. Hierarchical Bus System
● Multiple levels of buses (e.g., system bus, backplane bus, I/O bus).
● Allows for efficient data transfer and scalability.
Bus Interconnection
us interconnection is a fundamental method for connecting various
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componentsofacomputersystem,allowingthemtocommunicateandtransfer
data. It involves a set of parallel wires or traces on a motherboard thatcarry
data,addresses,andcontrolsignalsbetweentheCPU,memory,andperipheral
devices. Here's an in-depth look at bus interconnection:
Key Components of a Bus
1. Data Bus
● Carries actual data between components.
● Width(numberoflines)determinestheamountofdatathatcanbe
transferred simultaneously (e.g., 8-bit, 16-bit, 32-bit, 64-bit).
2. Address Bus
● Carriestheaddressesofmemorylocationswheredataistoberead
from or written to.
● Width determines the maximum addressing capability (e.g., a
32-bit address bus can address 232 memory locations).
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3. Control Bus
● Carries control signals that manage various operations, such as
reading fromorwritingtomemory,acknowledginginterrupts,and
synchronizing data transfers.
● Common control signals include read/write signals, interrupt
requests, and bus control signals.
ypes of Buses
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1. System Bus
The primary bus connects the CPU, main memory (RAM), andotheressential
components.
● Data Bus: Transfers data.
● Address Bus: Transfers addresses.
● Control Bus: Transfers control signals.
. Expansion Bus
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Connects peripheral devices tothesystembus,providingameanstoaddnew
hardware components.
● Examples: PCI(PeripheralComponentInterconnect),PCIe(PCIExpress),
ISA (Industry Standard Architecture).
. Backplane Bus
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Used in server and industrial computer systems, where multiple cards
(modules) are connected in parallel to a common backplane.
. Front-Side Bus (FSB)
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ConnectstheCPUtothemainmemorycontroller,oftenconsideredpartofthe
system bus in older architectures.
us Architectures
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1. Single Bus Architecture
● Description: All components share a single communication bus.
● Advantages: Simplicity and low cost.
● Disadvantages: Limited bandwidth and potential for data collisions,
leading to bottlenecks.
2. Multiple Bus Architecture
● Description: Uses separate buses for different purposes (e.g., separate
data, address, and control buses).
● Advantages: Increased bandwidth and reduced contention.
● Disadvantages: Increased complexity and cost.
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3. Hierarchical Bus Architecture
● Description: Multiple levels of buses,typicallywithahigh-speedsystem
bus connecting the CPU and memory, and slower peripheral buses
connecting I/O devices.
● Advantages: Efficient handling of high-speed and low-speed devices,
scalability.
● Disadvantages: Complexity in design and implementation.
Bus Operations
1. Synchronous Bus
● Data transfers are synchronized with a clock signal.
● Each component operates in lock-step with the clock, ensuring
coordinated data transfers.
● Advantages: Simple control and timing.
● Disadvantages: Limited by the speed of the slowest component.
2. Asynchronous Bus
● Data transfers are not coordinated with a central clock.
● Handshaking signals are used to manage data transfers.
● Advantages: Flexibility and the ability to connect devices with
different speeds.
● Disadvantages: More complex control logic and potential timing
issues.
us Communication Protocols
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1. Arbitration
● Description:Mechanismtocontrolaccesstothebus,ensuringthatonly
one device uses the bus at a time.
● Methods:
● Daisy-Chaining: Devices are connected in series, and priority is
determined by the position in the chain.
● Centralized Arbitration: A centralarbitercontrolsaccess,granting
the bus to the highest priority request.
● Distributed Arbitration: Devices negotiate among themselves to
determine which device gets the bus.
2. Bus Cycle
● Description: The sequence of steps performed during a single data
transfer operation on the bus.
● Phases:
● Address Phase: The address of the data is placed on the address
bus.
● Data Phase: The actual data transfer takes place on the data bus.
● Control Phase: Control signals coordinate the transfer, indicating
read/write operations and acknowledging completion.
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xamples of Bus Standards
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1. PCI (Peripheral Component Interconnect)
● Widely used for connecting peripherals to the motherboard.
● Supports plug-and-play, allowing devices to be added without manual
configuration.
2. PCIe (PCI Express)
● SuccessortoPCI,providinghigherbandwidthandspeedthroughaserial
communication protocol.
● Uses lanes for data transfer, allowing for scalable performance (x1, x4,
x8, x16).
3. ISA (Industry Standard Architecture)
● An older standard, mainly used in early PCs for connecting peripherals.
● Operates at lower speeds and is largely obsolete in modern systems.
iagram of Bus Interconnection
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Here’s a simplified diagram showing a typical bus interconnection structure
Description
● CPU: Central Processing Unit, which processes data and instructions.
● System Bus: Main busconnectingtheCPU,memory,andotherprimary
components.
● Memory: Main memory (RAM) connectedtothesystembusforfastdata
access.
● Expansion Bus: Additional bus for connecting peripheral devices.
● I/O Devices: Various input/output devices connected through the
expansion bus.
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Multiple Bus Hierarchies
Inamultiplebushierarchy,acomputersystemusesseveralbusestoimprove
performance and scalability. This structure is designed to handle the varying
speedanddatatransferrequirementsofdifferentcomponentsefficiently.Here’s
an in-depth look at multiple bus hierarchies:
Key Concepts
1. Hierarchical Bus Structure
● Multiple buses organized in ahierarchy,typicallywithhigh-speed
busesatthetopconnectingcriticalcomponents(CPUandmemory)
and lower-speed buses connecting peripheral devices.
2. Bus Levels
● System Bus: High-speed bus connecting the CPU, main memory,
and sometimes high-speed I/O devices.
● Backplane Bus: Connects major components like the CPU,
memory, and other critical subsystems.
● I/O Bus: Lower-speed bus for connecting I/O devices such as
keyboards, mice, printers, etc.
Advantages of Multiple Bus Hierarchies
1. Improved Performance
● Reduces buscontentionandbottlenecksbyseparatinghigh-speed
and low-speed traffic.
● Allows simultaneous data transfers on different buses.
2. Scalability
● Easier to add more devices without degrading overall system
performance.
● Can support a wide range of device speeds and bandwidth
requirements.
3. Flexibility
● Different buses can beoptimizedfordifferenttypesofdevicesand
data transfers.
ultiple Bus Hierarchy Structure
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Here’s a typical structure for a multiple bus hierarchy:
1. System Bus
● Components: CPU, main memory (RAM), high-speed cache, and
sometimes high-speed I/O devices.
● Characteristics: High bandwidth and low latency, critical for
CPU-memory communication.
2. Backplane Bus
● Components:Connectsmajorsubsystemsincludingthesystembus,I/O
buses, and additional processors if present.
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● C haracteristics: Moderate speed, acts as an intermediary between the
system bus and I/O buses.
3. I/O Bus
● Components: Peripheral devices such as hard drives, USB devices,
network cards, sound cards, etc.
● Characteristics: Lower speed comparedtothesystembus,optimizedfor
peripheral communication.
Example: Typical Multiple Bus Hierarchy
Description
1. System Bus
● Connects CPU, RAM, and high-speed components.
● Handles fast data transfers and critical operations.
2. Backplane Bus
● Serves as a backbone, connecting various subsystems and buses.
● Facilitates communication between the system bus and I/O buses.
3. I/O Buses
● USBBus:Connectsdeviceslikekeyboards,mice,externalstorage,
and other peripherals.
● SATA Bus: Connects internal storage devices such asharddrives
and SSDs.
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● P CIe Bus: High-speed bus for components like GPUs, network
cards, and additional high-speed peripherals.
● Ethernet and Sound Card Buses: Specific buses for network
interfaces and audio devices, respectively.
etailed Example of Bus Hierarchy Operation
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1. High-Speed Data Transfer
● The CPU needs to transfer a large amount of data to RAM.
● The system bus handles thistransferdirectly,ensuringlowlatencyand
high bandwidth.
2. Peripheral Communication
● A user clicks a mouse connected via USB.
● ThesignaltravelsthroughtheI/ObustotheUSBcontroller,whichthen
communicates with the CPU via the backplane bus.
3. Storage Access
● A file is saved to an internal SSD.
● The data is transferred from the CPU to the SATA controller over the
backplane bus, and then to the SSD over the SATA bus.
Elements of bus design Performance metrics and measurement
lements of Bus Design
E
Bus design involves several critical elements that determine the performance
and efficiency of the data transfer between components. These elements
include the bus width, clock speed, arbitration methods, and signaling
techniques. Understanding these elementshelpsindesigningbusesthatmeet
the requirements of different computer architectures.
1. Bus Width
● Data Width: Number of data lines, determining how many bits can be
transferred simultaneously (e.g., 8-bit, 16-bit, 32-bit, 64-bit).
● Address Width: Number of address lines, determining the maximum
addressable memory (e.g.,a32-bitaddressbuscanaddressupto4GB
of memory).
2. Clock Speed
● The frequency at which the bus operates,typicallymeasuredinMHzor
GHz.
● Higher clock speeds result in faster data transfer rates.
3. Arbitration
● Mechanisms to control access to the bus and avoid conflicts when
multiple devices want to communicate simultaneously.
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● C entralized Arbitration: A single arbiter (usually part of the CPU or a
dedicated controller) grants bus access based on a priority scheme.
● Distributed Arbitration: Devices negotiate among themselves to
determine which device gets access to the bus.
. Signaling Techniques
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● Synchronous: Data transfers are coordinated with a clock signal,
ensuring that all components operate in lock-step.
● Asynchronous: Data transfers are managed using handshaking signals
without a central clock, allowing more flexibility and compatibility
between devices with different speeds.
5. Bus Protocol
● Definestherulesforcommunicationoverthebus,includinghowdatais
formatted, how control signals are used, and how devices initiate and
acknowledge transfers.
● Examples: PCI, PCIe, USB, and SATA.
erformance Metrics
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Evaluating the performance of a bus involvesseveralmetricsthatquantifyits
efficiency, speed, and capability to handle data transfers. Key performance
metrics include bandwidth, latency, throughput, and utilization.
1. Bandwidth
● The maximum rate at which data can be transferred over the bus,
typically measured in megabytes per second (MB/s) or gigabytes per
second (GB/s).
● Calculation:
● Bandwidth=Bus Width×Clock Speed
● Bandwidth=Bus Width×Clock Speed
2. Latency
● Thetimeittakesforasignaltotravelfromthesourcetothedestination,
measured in nanoseconds (ns) or milliseconds (ms).
● Lower latency is crucialforreal-timeapplicationsandhigh-performance
computing.
3. Throughput
● The actual rate at which data is successfully transferred over the bus,
considering overheads and inefficiencies.
● Often lower than the theoretical bandwidth due to protocol overheads
and bus contention.
4. Utilization
● Thepercentageoftimethebusisactivelytransferringdataversusbeing
idle.
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● H igh utilization indicates efficient use of the bus, but extremely high
utilization can lead to contention and delays.
easurement Techniques
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Measuringbusperformanceinvolvesusingvarioustoolsandmethodstocollect
data on the above metrics. These measurements help in optimizing and
validating bus designs.
1. Bus Analyzers
● Specialized hardware tools that monitor and record bus activity,
providing detailed insights into data transfers, protocol usage, and
timing.
● Useful for debugging and optimizing bus performance.
2. Software Profiling
● Software tools and operating system features that log bus activity and
performance.
● Examples include performance counters, profilers, and system
monitoring tools.
3. Simulation and Modeling
● Using software simulations to model bus behavior under different
conditions and workloads.
● Helps in predicting performance and identifying potential bottlenecks
before implementing the actual hardware.
xample of Bus Performance Metrics Calculation
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Let's consider a bus with the following characteristics:
● Data Width: 32 bits (4 bytes)
● Clock Speed: 100 MHz
Bandwidth = Data Width x Clock Speed
= 4 bytes x 100 MHz
= 400 MB/s
atency Measurement
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Using a bus analyzer, suppose the latency measured foradatatransferis50
ns.
hroughput Measurement
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If the actual data transfer rate observed (considering protocol overhead and
bus contention) is 350 MB/s, then:
Throughput = 350 MB/s
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Utilization Calculation
If the bus is active for 70% of the time during a given observation period, then:
Utilization = 70%
Chapter - 1.b. (Memory System)
Memory Hierarchy
emoryhierarchyincomputerarchitecturereferstoastructuredarrangement
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of different types of memory storagesystems,eachwithvaryingspeeds,sizes,
and costs. The primary goal is toprovideabalancebetweenperformanceand
cost, ensuring fast access to frequently used data while keeping the overall
system cost-effective.
Levels of Memory Hierarchy
he memory hierarchy is typically organized from fastest and smallest to
T
slowest and largest. Here are the common levels:
1. Registers
2. Cache Memory
3. Main Memory (RAM)
4. Secondary Storage
5. Tertiary Storage
1. Registers
● Location: Inside the CPU.
● Speed: Fastest type of memory.
● Size: Smallest (typically a few kilobytes).
● Cost: Most expensive per bit.
● Function: Temporary storage for instructions and data currently being
processed by the CPU.
● Access Time: 1 CPU clock cycle.
● Example: Program Counter (PC), Accumulator, General-purpose
registers.
2. Cache Memory
● Location: Between the CPU and main memory, often built intotheCPU
itself.
● Speed: Very fast but slower than registers.
● Size: Larger than registers but smaller than RAM (typically a few
megabytes).
● Cost: Expensive but less than registers.
● Function: Stores frequently accessed data and instructions to reduce
access time to main memory.
● Access Time: A few CPU clock cycles.
20
● Levels:
● L1 Cache: Closest to the CPU core, smallest, and fastest.
● L2 Cache: Larger and slower than L1, but faster than RAM.
● L3 Cache: Shared among CPU cores, larger and slower than L2.
3. Main Memory (RAM)
● Location: External to the CPU but directly accessible by the CPU.
● Speed: Slower than cache memory.
● Size: Larger than cache memory (typically gigabytes).
● Cost: Moderate.
● Function: Stores data and instructions that are currently in use bythe
CPU.
● Access Time: Tens of nanoseconds.
● Types:
● DRAM(DynamicRAM):Commonformainmemory,needsperiodic
refreshing.
● SRAM (Static RAM): Faster and used in cache memory, does not
need refreshing.
4. Secondary Storage
● Location: Connected via I/O buses.
● Speed: Much slower than main memory.
● Size: Larger than main memory (typically terabytes).
● Cost: Less expensive per bit than main memory.
● Function: Stores data and programs not currently in use; provides
long-term storage.
● Access Time: Milliseconds.
● Examples:
● HDD (Hard Disk Drive): Magnetic storage, slower access.
● SSD (Solid State Drive): Flash memory, faster access than HDD.
5. Tertiary Storage
● Location: Connected via I/O interfaces, often used for archival.
● Speed: Slowest type of storage.
● Size: Very large (up to petabytes).
● Cost: Least expensive per bit.
● Function: Backup and archival storage.
● Access Time: Seconds to minutes (often requires manual intervention).
● Examples:
● Tape Drives: Magnetic tape storage, used for backups.
● Optical Discs: CDs, DVDs, Blu-rays for long-term data storage.
21
emory Hierarchy Diagram
M
Here is a simplified diagram illustrating the memory hierarchy:
Temporal and Spatial Locality
● Temporal Locality: The principle that recently accessed data is likely to
be accessed again soon. This is why frequently used data is stored in
faster, smaller memory.
● SpatialLocality:Theprinciplethatdataclosetorecentlyaccesseddatais
likelytobeaccessedsoon.Thisiswhyentireblocksofmemoryareoften
transferred to cache.
emory Access Patterns
M
Understanding how programs access memory helpsinoptimizingthememory
hierarchy:
● Sequential Access: Accessing data in a linear order, often benefits from
prefetching.
● Random Access: Accessing data in a non-linear order, requiring more
sophisticated caching techniques.
Performance Considerations
● HitRate:Thepercentageofmemoryaccessesfoundinagivenlevelofthe
hierarchy. Higher hit rates in cache improve overall performance.
22
● M iss Penalty: The additional time required to fetch data from the next
levelofthehierarchywhenacachemissoccurs.Reducingmisspenalties
improves performance.
● Latency vs. Bandwidth: Latency is the time to access a single piece of
data,whilebandwidthistheamountofdatathatcanbetransferredper
unit time. Balancing these factors is critical for optimal performance.
Main Memory
ain memory, also known as primary memory or RAM (Random Access
M
Memory),isthecentralstorageareainacomputerthatisdirectlyaccessibleby
the CPU.IttemporarilystoresdataandinstructionsthattheCPUneedswhile
performing tasks, enabling fast access and processing.
Key Characteristics of Main Memory
1. Volatility: Main memory is volatile, meaning it loses all stored
information when the power is turned off.
2. Speed:Mainmemoryismuchfasterthansecondarystoragedevices(like
hard drives or SSDs) but slower than CPU registers and cache memory.
3. DirectAccess:TheCPUcanaccessanypartofthemainmemorydirectly
and quickly.
4. Dynamic and Static Types:
● DRAM (Dynamic RAM): Needs to be refreshed thousands of times
persecond.Commonlyusedforthemainmemorybecauseitoffers
a good balance between cost and performance.
● SRAM (StaticRAM):FasterandmorereliablethanDRAMbutalso
more expensive. Typically used for cache memory within theCPU
rather than the main memory.
Functions of Main Memory
1. DataStorage:Storesdatathatisactivelybeingusedorprocessedbythe
CPU.
2. Instruction Storage: Stores the instructions that the CPU executes.
3. Intermediate Storage: Holds intermediate results and data during
processing tasks.
tructure and Organization
S
Mainmemoryistypicallyorganizedintomultipleslotsormodules,allowingfor
easy upgrades and expansions. Eachmodulecontainsagridofcellsarranged
in rows and columns, where each cell represents a bit of data.
Performance Metrics
1. Capacity: Measured in gigabytes (GB) or terabytes (TB), it determines
how much data can be stored.
23
2. Speed: Often measuredinMHzorGHz,indicatinghowquicklydatacan
be read from or written to the memory.
3. Latency: The time it takes to access data from the memory, typically
measured in nanoseconds (ns).
ole in Memory Hierarchy
R
Mainmemorysitsbetweenthefaster,smallerCPUcacheandtheslower,larger
secondary storage in the memory hierarchy. It acts as a bridge, providing a
balance between speed and capacity.
Types of Main memory
ain memory, also known as primary memory or RAM (Random Access
M
Memory), comes inseveraltypes,eachwithitsowncharacteristicsintermsof
speed, volatility, and cost. The main types of main memory include:
1. Dynamic Random Access Memory (DRAM)
● Characteristics:
● Usesacapacitortostoreeachbitofdata,requiringperiodicrefresh
cycles to maintain the stored information.
● Slower and less expensive compared to SRAM.
● Commonly used as main memory in computer systems duetoits
lower cost per bit.
● Advantages:
● Higher storage density compared to SRAM.
● Lower cost per bit, making it suitable for main memory
applications.
● Disadvantages:
● Slower access times compared to SRAM.
● Requires periodic refreshing to maintain data integrity.
2. Static Random Access Memory (SRAM)
● Characteristics:
● Uses flip-flops to store each bit of data, eliminating the need for
refreshing.
● Faster and more expensive compared to DRAM.
● Commonly used as cache memory in CPUs due to its high speed.
● Advantages:
● Faster access times compared to DRAM.
● No need for periodic refreshing, leading to lower power
consumption.
● Disadvantages:
● Higher cost per bit compared to DRAM.
● Lower storage density compared to DRAM.
24
3. Synchronous Dynamic Random Access Memory (SDRAM)
● Characteristics:
● Synchronizedwiththesystemclock,allowingforfasterdataaccess
compared to asynchronous DRAM.
● Commonly used in older computer systems as main memory.
● Advantages:
● Faster access times compared to asynchronous DRAM.
● Supports higher clock frequencies, enabling higher bandwidth.
● Disadvantages:
● Morecomplextodesignandimplementcomparedtoasynchronous
DRAM.
● Higher power consumption due to continuous refresh cycles.
.DoubleDataRateSynchronousDynamicRandomAccessMemory(DDR
4
SDRAM)
● Characteristics:
● AtypeofSDRAMthattransfersdataonboththerisingandfalling
edgesoftheclocksignal,effectivelydoublingthedatatransferrate
compared to SDRAM.
● Provideshigherbandwidthandimprovedperformancecomparedto
traditional SDRAM.
● Advantages:
● Higher data transfer rates compared to SDRAM.
● Improved efficiency in data transmission, leading to better overall
system performance.
● Disadvantages:
● Higher cost compared to traditional SDRAM.
● Requires compatible hardware and motherboard support.
5. Non-Volatile Memory (NVRAM)
● Characteristics:
● Retains data even when power is turned off, unlike traditional
volatile RAM.
● Offers fast read and write speeds similar to DRAM.
● Examples include Phase Change Memory (PCM), Magnetoresistive
RAM (MRAM), and Ferroelectric RAM (FeRAM).
● Advantages:
● Provides persistence like secondary storage butwithfasteraccess
times.
● Suitable for applications requiring fast data storage and retrieval
with non-volatility.
25
● Disadvantages:
● Typically more expensive than traditional volatile RAM.
● LimitedavailabilityandcompatibilitycomparedtoestablishedRAM
technologies.
Types of RAM
1. DRAM (Dynamic RAM):
● Stores data in a cell consisting of a capacitor and a transistor.
● Requires periodic refreshing to maintain data integrity.
● Commonly used as main memory in computers due to its high
density and lower cost compared to SRAM.
● Slower access times compared to SRAM.
2. SRAM (Static RAM):
● Stores data using flip-flops, requiring no refreshing.
● Faster access times compared to DRAM.
● More expensive and less dense compared to DRAM.
● Commonly used in cache memory due to its high speed.
3. SDRAM (Synchronous Dynamic RAM):
● Synchronizedwiththesystemclock,allowingforfasterdataaccess
compared to asynchronous DRAM.
● Used in older computer systems as main memory.
● Offers higher clock frequencies, enabling higher bandwidth.
4. DDR SDRAM (Double Data Rate Synchronous Dynamic RAM):
● Transfers data on both the rising and falling edges of the clock
signal, effectively doubling the data transfer rate compared to
SDRAM.
● Provideshigherbandwidthandimprovedperformancecomparedto
traditional SDRAM.
● Commonly used in modern computer systems as main memory.
Types of ROM:
1. Mask ROM (Read-Only Memory):
● Dataispermanentlyencodedduringmanufacturingandcannotbe
changed.
● Commonly used for firmware and low-level system programming.
2. EPROM (Erasable Programmable Read-Only Memory):
● Data can be erased and reprogrammed using ultraviolet light
exposure.
26
● U
sed during development and testing phases but not typically in
end-user products due to the inconvenience of erasure.
3. EEPROM (Electrically Erasable Programmable Read-Only Memory):
● Data can be electrically erased and reprogrammed.
● Used in various applications, including storing BIOS settings,
firmware, and other small amounts of non-volatile data.
4. Flash Memory:
● A type of EEPROM that can be erased and reprogrammed in
blocks, making it suitable for mass storage applications.
● Commonly used in USB drives, SSDs, memory cards, and other
storage devices.
ifference Between SRAM & DRAM:
D
1. Technology:
● SRAM: Uses flip-flops to store data, requiring continuous power to
maintain information.
● DRAM: Stores data using a capacitor and transistor, needing periodic
refreshing to prevent data loss.
2. Access Time:
● SRAM: Faster a ccess times due to the simplicity of the storage
mechanism.
● DRAM: Slower access times compared to SRAM due to the need for
refreshing.
3. Density and Cost:
● SRAM: Less dense and more expensive compared to DRAM.
● DRAM: Higher density and lower cost per bit compared to SRAM.
4. Applications:
● SRAM: Commonly used in cache memory due to its high speed.
● DRAM:Usedasmainmemoryincomputersduetoitshigherdensityand
lower cost
Cache memory
achememoryisahigh-speedtypeofvolatilecomputermemorythatservesas
C
a buffer between the CPU and main memory(RAM)inacomputersystem.Its
primary function is to store frequently accessed data and instructions to
improve the overall speed and efficiency of the system.
27
Key Characteristics:
1. Speed: Cache memory is much faster than main memory and slower
thanCPUregisters.ThishighspeedallowstheCPUtoaccessfrequently
used data quickly.
2. ProximitytoCPU:CachememoryislocatedclosertotheCPUthanmain
memory, often integrated directly into the CPU chip or located on a
separate chip nearby. This proximity reduces access latency.
3. Hierarchy: Cache memory is organized into multiple levels (L1, L2, L3),
with each level offering varying speeds, sizes, and distances from the
CPU. L1 cache is the fastest but smallest, while L2 and L3 caches are
larger but slower.
4. Volatility: Likemainmemory,cachememoryisvolatile,meaningitloses
its contents when the power is turned off. This requires data to be
fetched from main memory or other storage devices upon system startup.
5. Data Management: Cache memory employs algorithms to determine
which data to store and when to evict datatomakeroomfornewdata.
CommonalgorithmsincludeLeastRecentlyUsed(LRU),LeastFrequently
Used (LFU), and Random Replacement.
Functionality:
1. Data Storage: Cache memory stores copies of frequently accessed data
and instructions from mainmemory.ThisreducestheneedfortheCPU
to access slower main memory for commonly used data.
2. Data Retrieval: When the CPU needs to access data, it first checks the
cachememory.Ifthedataisfoundinthecache(cachehit),itisretrieved
quickly. If thedataisnotinthecache(cachemiss),theCPUretrievesit
from main memory and stores a copy in the cache for future access.
3. Cache Coherency: In systemswithmultipleCPUcores,cachecoherency
protocols ensure that each core has consistent views of memory. This
prevents data inconsistencies that can occur when multiple cores have
their own caches.
Types of Cache:
1. L1 Cache (Level 1 Cache):
● Located closest to the CPU, often integrated into the CPU chip.
● Very fast but small in size.
● Stores frequently used instructions and data.
2. L2 Cache (Level 2 Cache):
● Located on a separate chip or on the same chip as the CPU but
further away from the core.
● Larger than L1 cache but slower.
● Acts as a backup to L1 cache, storing additional data and
instructions.
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3. L3 Cache (Level 3 Cache):
● Located on a separate chip or shared among multiple CPU cores.
● Larger than L2 cache but slower.
● Serves as a shared cache for multiple CPU cores, reducing the
need to access main memory.
Benefits:
1. Improved Performance:Cachememoryreducestheaveragetimeittakes
for the CPU to access data and instructions, thereby improving overall
system performance.
2. Reduced Latency: By storing frequently used data closer to the CPU,
cache memory reduces access latency compared to fetching data from
main memory.
3. Enhanced CPU Utilization: Cache memory helps in utilizing CPU
resources more efficiently by reducing idle time spent waiting for data
from main memory.
Cache Memory Mapping
ache memory mapping refers to the process of determining how data from
C
main memory is mapped to specific locations in thecache.Differentmapping
techniques dictate how data is stored, retrieved, and managed within the
cache. There are several cache mapping techniques commonly used in
computer architectures:
Direct Mapping
In direct mapping, each block of main memory is mapped to exactly one
specific cache line. The mapping is determined using a hashingfunctionthat
maps main memory addresses to specific cache lines. This technique is
relatively simple and efficient but can lead to cache conflicts.
Key Components of Direct Mapping:
1. Cache Lines:
● The cache is divided into fixed-size blocks called cache lines.
● Each cache line can store data from a single block of main
memory.
2. Main Memory Blocks:
● Main memory is divided into blocks, each of the same size as a
cache line.
● Each block of main memory is mapped to exactly one specific
cache line.
29
3. Mapping Function:
● A hashing function is used to determine which cache line a
particular block of main memory should be mapped to.
● Themappingfunctiontypicallyusesaportionofthemainmemory
address to determine the cache line index.
4. Tag:
● Each cache line contains a tag field that stores the memory
address of the block currently stored in the cache line.
● Thetagisusedtodeterminewhethertherequesteddataispresent
in the cache line.
Advantages of Direct Mapping:
● Simplicity: Direct mapping isstraightforwardtoimplementandrequires
minimal hardware complexity.
● Low Hardware Overhead: The hardware required to implement direct
mapping is minimal, making it cost-effective.
Disadvantages of Direct Mapping:
● Limited Flexibility: Each block of main memory can only map to one
specific cache line, limiting flexibility in cache usage.
● Cache Conflicts: Multiple main memory blocks may map to the same
cache line due to the hashing function, leading to cache conflicts. This
can result in performance degradation.
xample of Direct Mapping:
E
Consider a cache with 8 cache lines and main memory with 32blocks.Ifthe
cacheandmainmemoryarebothdividedintoblocksofsize4bytes,eachblock
of mainmemorymapstoonespecificcachelinebasedontheindexportionof
its memory address.
● Block 0 of main memory maps to cache line 0.
● Block 1 maps to cache line 1.
● Block 2 maps to cache line 2.
● ...
● Block 31 maps to cache line 7.
When a memory address is accessed, the mapping function determines the
correspondingcachelinebasedontheindexportionoftheaddress.Ifthedata
is presentinthecachelineandthetagmatchestherequestedaddress,itisa
cache hit. Otherwise, it is a cache miss, and the data must be fetched from
main memory.
Associative Mapping
ssociative mapping, also known as fully associative mapping, is a cache
A
mapping technique where each block of main memory can be placed in any
cacheline.Therearenorestrictionsonwhereablockcanbestoredwithinthe
30
ache. This provides maximum flexibility butrequiresadditionalhardwarefor
c
tag comparison.
Key Components of Associative Mapping:
1. Cache Lines:
● The cache is divided into fixed-size blocks called cache lines,
similar to other mapping techniques.
● Each cache line can store data from any block of main memory.
2. Main Memory Blocks:
● Main memory is divided into blocks, each of the same size as a
cache line.
● Eachblockofmainmemorycanbeplacedinanycachelinewithin
the cache.
3. Tag Comparison:
● Each cache line contains a tag field that stores the memory
address of the block currently stored in the cache line.
● During cache access, the CPU compares the requested memory
address with the tags of all cache lines simultaneously to
determine if the data is present in the cache.
Advantages of Associative Mapping:
● Flexibility: Associative mapping provides maximum flexibility in cache
usage, allowing any block of main memory to be stored in any cache line.
● Elimination of Cache Conflicts: Since there are norestrictionsoncache
line placement, associative mapping eliminates cache conflicts
altogether.
Disadvantages of Associative Mapping:
● HardwareComplexity:Associativemappingrequiresadditionalhardware
for tag comparison of all cache lines simultaneously.
● Higher Cost: The increased hardware complexity results in higher
manufacturing costs for cache memory.
● Slower Access Times: Tag comparison for all cache lines can lead to
longer access times compared to other mapping techniques.
xample of Associative Mapping:
E
Consider a cache with 8 cache lines and main memory with 32 blocks. With
associative mapping, any block of main memory can be placed in any cache
line.
henamemoryaddressisaccessed,theCPUcomparestherequestedaddress
W
with the tags of all cache lines simultaneously. If the data is present in any
cache line and the tag matches the requested address, it is a cache hit.
Otherwise, it is a cache miss, and the data must be fetched from main memory.
31
Set Associative
et associative mapping is a cache mapping techniquethatcombinesaspects
S
of both direct mapping and fully associative mapping. In set associative
mapping, the cache is divided into a number of sets, and each set contains
multiple cache lines. Each block of main memory is mappedtoaspecificset,
andwithinthatset,itcanbeplacedinanycacheline.Thisprovidesabalance
between flexibility and simplicity, reducing the potential for cache conflicts
compared to direct mapping.
Key Components of Set Associative Mapping:
1. Cache Sets:
● The cache is divided into a number of sets, each containing
multiple cache lines.
● The number of sets is determined by the associativity of the cache.
2. Cache Lines:
● Each set contains multiple cache lines, similar to direct mapping.
● Each cache line can store data from any block of main memory
within its corresponding set.
3. Main Memory Blocks:
● Main memory is divided into blocks, each of the same size as a
cache line.
● Each blockofmainmemoryismappedtoaspecificsetwithinthe
cache.
4. Tag Comparison:
● Each cache line within a set contains a tag field that stores the
memory address of the block currently stored in the cache line.
● During cache access, the CPU compares the requested memory
addresswiththetagsofcachelineswithinthecorrespondingsetto
determine if the data is present in the cache.
Advantages of Set Associative Mapping:
● Flexibility: Set associative mapping provides more flexibility than direct
mapping by allowing each block of main memory to be placed in any
cache line within its corresponding set.
● ReducedCacheConflicts:Bydividingthecacheintosets,setassociative
mapping reduces the potential for cache conflicts compared to direct
mapping.
● Lower Hardware Complexity: Set associative mapping requires less
hardware complexity than fully associative mapping, making it more
cost-effective.
32
Disadvantages of Set Associative Mapping:
● HigherComplexity:Setassociativemappingismorecomplexthandirect
mapping due to the need for tag comparison within each set.
● Potential for Cache Conflicts:Whilesetassociativemappingreducesthe
potential for cache conflicts compared to direct mapping, it may still
experience cache conflicts within sets, especially with limited
associativity.
xample of Set Associative Mapping:
E
Consider a cache with 8 cache lines and main memory with 32 blocks. With
2-way set associativity, the cache is divided into 4 sets, each containing 2
cache lines.
hen a memory address is accessed, the CPU determines the corresponding
W
setbasedontheaddressandcomparestherequestedaddresswiththetagsof
cache lines within that set. If the data ispresentinanycachelinewithinthe
set and the tagmatchestherequestedaddress,itisacachehit.Otherwise,it
is a cache miss, and the data must be fetched from main memory.
Virtual Memory
irtual memory is a memory management technique used by operating
V
systems to provide the illusion of a larger and contiguous memory space to
applicationsthanphysicallyavailableinthesystem.Itallowsprogramstorun
withmemoryrequirementsexceedingthephysicalRAMcapacitybytemporarily
transferring data from RAM to disk storage.
Key Concepts of Virtual Memory:
1. Address Space:
● Each process in a computer system has its own virtual address
space, which represents the range of memory addresses that the
process can access.
● Virtual address spaces are typically larger than physical memory
and may exceed the available RAM capacity.
2. Pages:
● Memory is divided into fixed-size blocks called pages, typically
ranging from 4 KB to 8 KB in size.
● Both physical memory (RAM) and disk storage are divided into
pages.
3. Page Table:
● Each process has a page table that maps virtual memory
addresses to physical memory addresses.
● The page table ismaintainedbytheoperatingsystemandisused
for address translation during memory access.
33
4. Page Fault:
● When a process attempts to access a memory page that is not
currently in physical memory (RAM), a page fault occurs.
● The operating system handles page faults by swapping the
required page from disk storage into physical memory.
5. Page Replacement:
● Ifphysicalmemoryisfullandanewpageneedstobebroughtinto
memory,theoperatingsystemselectsapagetoevictfromphysical
memory and replace with the new page.
● Page replacement algorithms (e.g., Least Recently Used,
First-In-First-Out) are used to decide which page to replace.
6. Demand Paging:
● On demand paging, pages are brought into physicalmemoryonly
whentheyareneeded,ratherthanloadingtheentireprograminto
memory at once.
● Thisallowsformoreefficientmemoryusageandreducestheinitial
memory requirements of programs.
Advantages of Virtual Memory:
1. Increased Address Space: Virtual memory allows programs to access a
larger address space than physically available in the system, enabling
the execution of larger programs.
2. Memory Isolation: Each process has its own virtual address space,
providing memory isolation and security between processes.
3. Efficient Memory Utilization:Virtualmemoryallowsforefficientmemory
utilizationbyswappingdatabetweenRAManddiskasneeded,reducing
the memory footprint of idle or less frequently accessed programs.
Disadvantages of Virtual Memory:
1. Performance Overhead: The useofvirtualmemoryintroducesadditional
overhead duetoaddresstranslation,pagefaults,andpagereplacement,
which can impact system performance.
2. Potential for Thrashing: If the system is heavily loaded and constantly
swappingpagesbetweenRAManddisk,itmayenterastateofthrashing,
where the performance degrades significantly due to excessive page
faults.
3. Complexity: Managing virtual memory is complex and requires
sophisticatedalgorithmsforaddresstranslation,pagemanagement,and
page replacement.
Mapping using Pages
apping using pages is a memory management technique where the system
M
divides the physical memory and the virtual memory into fixed-size blocks
called pages. Each page typically consists of a contiguous range of memory
34
ddresses. The mapping process involves associating virtual memory pages
a
with physical memory pages.
Here's how mapping using pages works:
1. Page Size:
● Memory is divided into fixed-size blockscalledpages.Thesizeofapage
is determined by the operating system and hardware architecture.
Common page sizes range from 4 KB to 8 KB.
2. Virtual Memory:
● Eachprocessisgivenitsownvirtualmemoryspace,whichisdividedinto
pages. Virtual memory provides the illusion of a large and contiguous
address space to each process.
3. Physical Memory:
● The physical memory (RAM) is also divided into pages, with each page
corresponding to a fixed-size block of physical memory.
4. Page Table:
● Each process has apagetablemaintainedbytheoperatingsystem.The
page table maps virtual memory pages to physical memory pages.
● Thepagetablecontainsentriesthatstorethemappinginformation,such
as the virtual page number and the corresponding physical page
number.
5. Address Translation:
● Whenaprocessaccessesamemoryaddress,theCPUgeneratesavirtual
memory address.
● The memory management unit (MMU) translates the virtual memory
address into a physical memory address using the page table.
● TheMMUlooksupthevirtualpagenumberinthepagetabletofindthe
corresponding physical page number.
6. Page Fault:
● If the required page isnotpresentinphysicalmemory(i.e.,apagefault
occurs), the operating system must bring the required page into memory.
● The operating system may fetch the required page from secondary
storage (e.g., hard disk) into physical memory, updating the page table
accordingly.
7. Page Replacement:
● If physical memory is full and a new page needs to be brought into
memory, the operating system must selectapagetoevictfromphysical
memory.
35
● P age replacement algorithms (e.g., Least Recently Used,
First-In-First-Out) are used to decide which page to replace.
apping using pages allows for efficient memory management by providing a
M
flexible and scalable approach to managing memory. It enables processes to
access a larger address space than physically available in the system and
facilitates efficient memory allocation and sharing among multiple processes.
Page fault
page fault occurs in a virtual memory system when a program accesses a
A
memory pagethatisnotcurrentlypresentinphysicalmemory(RAM).Whena
page fault happens, the operating system needs to handle it by loading the
required page from secondary storage (such as a hard disk) into physical
memory, thus resolving the fault.
Here's how a page fault typically occurs and how it is handled:
1. Page Table Lookup:
● Whenaprogramaccessesamemoryaddress,theCPUgeneratesa
virtual memory address.
● The memory management unit (MMU) translates this virtual
address into a physical address using the page table.
2. Page Table Entry Check:
● If the page table lookup indicates that the required page is not
present in physical memory, a page fault is triggered.
3. Handling the Page Fault:
● The operating system receives a page fault interrupt from the
MMU, indicating that the requested page is not in physical
memory.
● The operating system must then decide how to handle the page
fault. It typically follows these steps:
a. Locate the Required Page:
● The operating system identifies thepagethatneedstobebrought
into physical memory. This information isavailablefromthepage
table entry corresponding to the virtual memory address that
triggered the fault.
b. Disk I/O Operation:
● The operating system initiates a disk I/O operation to read the
required page from secondary storage (e.g., hard disk) into an
available page frame in physical memory.
● This involves accessing the page from its location on disk and
transferring it into RAM.
36
c. Update Page Table:
● Once the required page is loaded into physical memory, the
operating system updates the page table entry for that page to
reflect its new location in memory.
4. Resuming Execution:
● After the page fault is handled and the required page is
successfullyloadedintophysicalmemory,theprogram'sexecution
can resume.
● The program can now access the memory address that triggered
the page faultwithoutencounteringanotherfault,astherequired
page is now present in memory.
age faults are a fundamental aspect of virtual memory systems and play a
P
crucial role in allowing programs to access a larger address space than
physically available memory. Efficient handling of page faults is essential for
maintaining system performance and ensuring smooth execution of programs.
Mapping using segments
apping using segments is another memory management technique used in
M
computer systems, particularly in architectures that support segmented
memorymodels.Inthisapproach,memoryisdividedintosegmentsofvariable
sizes,eachrepresentingalogicaldivisionofmemorycorrespondingtoaspecific
part of a program or data structure. Unlike paging, where memory is divided
into fixed-size blocks (pages), segmentation allows for more flexible memory
allocation and management.
ere's how mapping using segments typically works:
H
1. Segmentation:
● Memory is divided into segments, with each segment representing a
logical unit such as code, data, stack, or heap.
● Segments can vary in size and may have different access permissions
and attributes.
2. Segment Descriptor Table:
● Eachprocesshasasegmentdescriptortablemaintainedbytheoperating
system.
● The segment descriptor table containsentriesforeachsegmentusedby
the process, specifying the base address, size, access rights, and other
attributes of each segment.
3. Segment Selector:
● When a program accesses a memory address, it provides a segment
selector along with the offset within the segment.
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● T he segment selector is an index into the segment descriptor table,
specifying which segment the memory access belongs to.
4. Address Translation:
● The CPU's memory management unit (MMU) translates the segment
selector and offset into a physical memory address.
● Itretrievesthesegmentdescriptorcorrespondingtothesegmentselector
from the segment descriptor table.
● Using the information in the segment descriptor (such as the base
address), the MMU calculates the physical memory address by adding
the offset to the base address of the segment.
5. Protection and Access Control:
● Segmentation allows for fine-grained access control and protection by
assigning different access rights to different segments.
● The segment descriptor table contains information about access
permissions(e.g.,read,write,execute)foreachsegment,whichtheMMU
enforces during address translation.
6. Fragmentation:
● One challenge with segmentation is internal fragmentation, where
segments may not fully utilize thememoryallocatedtothem,leadingto
wasted space.
● Fragmentationcanoccurwhensegmentsareofvariablesizesanddonot
align neatly with memory boundaries.
7. Paging and Segmentation:
● Insomesystems,pagingandsegmentationareusedtogethertocombine
the benefits of both approaches.
● This approach, known as segmented paging, divides memory into
segments and further divides each segment into fixed-size pages.
TLB
LB stands for Translation Lookaside Buffer. It is a hardware cache used in
T
computer processors to improve the speed of virtual memory translation.
Functionality:
1. Translation of Virtual Addresses:
● When a program accesses memory, it generates avirtualmemory
address.
● Thevirtualaddressneedstobetranslatedintoaphysicalmemory
address before the data can be accessed in RAM.
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● T
his translation is performed by the Memory Management Unit
(MMU) in the CPU.
2. TLB Cache:
● The TLB is a small, high-speed cache that stores recently used
virtual-to-physical address translations.
● It acts as a lookaside buffer, allowing the MMU to quickly access
commonly used translations without having to consult the main
page table stored in memory.
3. Address Translation:
● When the CPUgeneratesavirtualmemoryaddress,itfirstchecks
the TLB to see if the translation is already present.
● If the translation is found in the TLB (TLB hit), the physical
memory address is retrieved directly from the TLB cache.
● If the translation is not found in the TLB (TLB miss), the MMU
consults the main page table stored in memory to retrieve the
translation.
4. TLB Management:
● The TLB is managed by hardware within the CPU.
● When a TLB miss occurs, the MMU retrievesthetranslationfrom
the main page table and stores it in the TLB for future use.
● If the TLB is full when a new translation needs to be stored, the
MMU uses a replacement algorithm (e.g., Least Recently Used) to
evict an entry from the TLB to make room for the new translation.
Benefits:
1. Speed: The TLB cache provides fast access to frequently used address
translations, reducing the time required for memory access.
2. Efficiency: By storing commonly used translations in a cache, the TLB
reduces the need to access the main page table stored in memory,
improving overall system performance.
3. Reduced Power Consumption: Accessing the TLB cache consumes less
power compared to accessing main memory, contributing to energy
efficiency in the system.
TLB Size and Associativity:
● The size of the TLB and its associativity (how entries are mapped to
cache lines) can vary depending on the CPU architecture and design.
● Larger TLBs can store more translations,reducingthelikelihoodofTLB
misses.
● Associativity determines how the TLB handles collisions and eviction of
entries when the cache is full.
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TLB Miss Penalty:
● ATLBmissoccurswhentherequiredtranslationisnotfoundintheTLB
and must be retrieved from the main page table.
● Thetimeittakestoretrievethetranslationfrommemoryisknownasthe
TLB miss penalty, which can impact overall system performance.
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Chapter - 2 (Computer Arithmetic)
Addition and Subtraction algorithm of sign magnitude number
ign-magnitude representation is a method of representing both positive and
S
negative numbers in binary. In this representation, the leftmost bit (most
significant bit) is used to indicate the signofthenumber,where0represents
positiveand1representsnegative.Theremainingbitsrepresentthemagnitude
of the number.
ere's how addition and subtraction of sign-magnitude numbersaretypically
H
performed:
Addition Algorithm:
1. Sign Extension:
● If the signs of the two numbers are the same, perform normal
addition of their magnitudes.
● If the signs are different, perform subtraction ofthemagnitudeof
the number with the larger magnitude from the magnitudeofthe
number with the smaller magnitude.
● The sign of the result will be the same as thesignofthenumber
with the larger magnitude.
2. Magnitude Addition:
● Add the magnitudes of the numbers, ignoring the sign bit.
● Ifthereisacarry-outfromthemostsignificantbit(MSB),overflow
has occurred, indicating that the result cannot be represented in
the given number of bits.
3. Sign Bit Adjustment:
● If overflow has occurred, set the result tooverfloworhandleitas
appropriate for the application.
● Otherwise, set the sign bit of the result to match the sign of the
number with the larger magnitude.
Subtraction Algorithm:
1. Sign Extension:
● If the signs of the two numbers are different, perform addition of
the magnitude of the number with the larger magnitude and the
magnitude of the number with the smaller magnitude.
● Ifthesignsarethesame,performsubtractionofthemagnitudesof
the two numbers.
2. Magnitude Subtraction:
● Subtract the magnitudes of the numbers, ignoring the sign bit.
● Iftheresultisnegative(borrowrequired),performborrowfromthe
next higher bit until there are no more borrow operations to
perform.
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3. Sign Bit Adjustment:
● Setthesignbitoftheresulttomatchthesignofthenumberwith
the larger magnitude.
● Ifthesignsofthetwonumberswereoriginallydifferent,theresult
will be negative. Otherwise, it will be positive.
xample:
E
Let's consider the addition and subtraction of two sign-magnitude numbers:
● Number 1: +1101 (positive)
● Number 2: -1001 (negative)
Addition:
● Magnitude of Number 1: 1101
● Magnitude of Number 2: 1001 (subtracting as signs are different)
● Result: 1010 (Sign: positive)
Subtraction:
● Magnitude of Number 1: 1101
● Magnitude of Number 2: 1001 (adding as signs are different)
● Result: 010 (Sign: positive)
dditionandsubtractionalgorithmforsigned2’scomplement
A
data
erforming addition and subtraction with signed 2's complement numbers
P
involves a few key steps. Here's how these operations are typically carried out:
Addition Algorithm:
1. Sign Extension:
● Ensure that both numbers have the same number of bits by
sign-extending the shorter number, i.e., replicating the sign bit
(MSB) of the original number to the leftmost positions.
2. Binary Addition:
● Perform binary addition on the two numbers, including the sign
bits. Start from the rightmost bit (least significant bit) and move
towards the left.
● Ignore any carry-out from the leftmost bit (MSB) during the
addition.
3. Overflow Detection:
● If there is a carry-out from the leftmost bit (MSB), it indicates
overflow. In 2's complement arithmetic, overflow occurs when the
signsofthetwooperandsarethesamebutthesignoftheresultis
different.
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● D etect overflow by comparing the carry-out from the leftmost bit
(MSB) with the carry-in to the leftmost bit. If they are different,
overflow has occurred.
4. Result Adjustment:
● If overflow occurs, discard the resultorhandleitaccordingtothe
application's requirements.
● Otherwise, the result is valid and represents the sum of the two
signed numbers.
ubtraction Algorithm:
S
Subtraction in 2's complement is performed by negating the second operand
(subtrahend) and then adding it to the first operand (minuend), similar to
addition.
1. Negation:
● Negate the second operand (subtrahend) by taking its 2's
complement. This is done by inverting all bits and adding 1.
2. Addition:
● Add the negated subtrahend to the minuend using the addition
algorithm described above.
3. Overflow Detection:
● Perform overflow detection as described above.
4. Result Adjustment:
● Handle overfloworinterprettheresultasthedifferenceofthetwo
signed numbers.
xample:
E
Let's perform addition and subtraction with signed 2's complement numbers:
● Number 1: 0101 (positive)
● Number 2: 1100 (negative)
Addition:
● Sign Extension: 0101 (positive) and 11100 (negative)
● Binary Addition: 0101 + 11100 = 10001 (ignore carry-out from MSB)
● Overflow Detection: No overflow (signs of operands differ, but sign of
result is correct)
● Result: 0001 (positive)
Subtraction:
● Negation of Number 2: 1100 (original) → 0011 (negated)
● Sign Extension: 0101 (positive) and 00011 (negated)
● Binary Addition: 0101 + 00011 = 00100 (ignore carry-out from MSB)
● Overflow Detection: No overflow
● Result: 0100 (positive)
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Multiplication Algorithm
ultiplication in computer arithmetic can be performed using various
M
algorithms,dependingonthehardwarearchitectureandrequirementssuchas
speed, area efficiency, and power consumption. One of the most common
multiplicationalgorithmsusedincomputerarchitectureisthe"ShiftandAdd"
algorithm, also known as the "Booth's algorithm" or "Multiplier-Array
Multiplication."
Shift and Add (Booth's) Algorithm:
1. Initialization:
● Initializetheproductregistertozero,andinitializeacountertothe
number of bits in the multiplicand and multiplier.
2. Loop:
● Repeat the following steps until the counter becomes zero:
a. Check the two least significant bits of the multiplier:
● If they are00or11,performnooperation(movetothenext
step).
● If they are 01, subtract the multiplicand from the product
register.
● If they are 10, add the multiplicand to the product register.
● b. Right-shift the multiplier and the product register by 1 bit.
c. Decrement the counter by 1.
3. Result:
● After the loop, the product register contains the result of the
multiplication.
xample:
E
Let's perform multiplication using the Shift and Add algorithm:
● Multiplicand: 5 (binary: 0101)
● Multiplier: 3 (binary: 0011)
Steps:
1. Initialize the product register to 0.
2. Perform the following steps for each bit of the multiplier (from right to
left):
● Initial Product Register: 0000
● Bit 0: 1 (LSB) → No operation (00)
● Bit 1: 1 → Add the multiplicand (0101) to the product register:
● Product Register: 0101
● Bit 2: 0 → Subtract the multiplicand from the product register:
● Product Register: 0101 - 0101 = 0000
● Bit 3: 0 (MSB) → No operation (00)
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3. Thefinalproductregistervalueis0000,whichcorrespondstotheresult
of the multiplication (5 * 3 = 15).
Advantages and Disadvantages:
● Advantages:
● Simple and straightforward algorithm.
● Requires only shift and add/subtract operations.
● Suitable for hardware implementation.
● Disadvantages:
● Slower than more advanced multiplication algorithms, especially
for large numbers.
● Requires multiple iterations for each bit of the multiplier.
Division Algorithm
erforming division in computer arithmetic typically involves using iterative
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algorithms to find the quotient and remainder of the division operation. One
common algorithm used for integer division is the "Restoring Division"
algorithm. Thisalgorithmisparticularlysuitableforhardwareimplementation
due to its simplicity and regularity.
Restoring Division Algorithm:
1. Initialization:
● Initializethequotientregister(Q)andtheremainderregister(A)to
the dividend (numerator).
● Initialize the divisor (denominator) register (B) with the divisor.
2. Main Loop:
● Repeat the following steps until the divisor register (B) becomes
zero:
a. Compare the sign of A and the sign of B:
● IfAisnon-negativeandBisnon-negative,orifAisnegative
and B is negative, perform subtraction: subtract B from A.
● IfAisnegativeandBisnon-negative,performaddition:add
B to A.
● b.Left-shiftthequotientregister(Q)andtheremainderregister(A)
by 1 bit.
● Settheleastsignificantbit(LSB)ofQto0or1basedonthe
result of the comparison step.
● c. Decrement the divisor register (B) by 1.
3. Result Extraction:
● After the main loop, the quotientisstoredinthequotientregister
(Q), and the remainder is stored in the remainder register (A).
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xample:
E
Let's perform division using the Restoring Division algorithm:
● Dividend (Numerator): 10 (binary: 1010)
● Divisor (Denominator): 3 (binary: 0011)
Steps:
1. Initialization:
● Quotient Register (Q): 0 (binary: 0)
● Remainder Register (A): 10 (binary: 1010)
● Divisor Register (B): 3 (binary: 0011)
2. Main Loop:
● Initial Registers: Q = 0, A = 1010, B = 0011
● Step 1: Subtract B from A (1010 - 0011 = 0111)
● Shift Q and A left by 1 bit: Q = 0, A = 0110
● Decrement B by 1: B = 0010
● Step 2: Subtract B from A (0110 - 0010 = 0100)
● Shift Q and A left by 1 bit: Q = 00, A = 1000
● Decrement B by 1: B = 0001
● Step 3: Add B to A (1000 + 0001 = 1001)
● Shift Q and A left by 1 bit: Q = 001, A = 0010
● Decrement B by 1: B = 0000 (terminating condition)
3. Result Extraction:
● Quotient (Q) = 001 (binary), which is the integer quotient of the
division.
● Remainder (A) = 0010 (binary), which is the remainder of the
division.
Advantages and Disadvantages:
● Advantages:
● Simple and regular algorithm suitable for hardware
implementation.
● Can be implemented efficiently in pipelined architectures.
● Provides both quotient and remainder as outputs.
● Disadvantages:
● May require multiple iterations for long division operations,
impacting performance.
● Requires additional hardware for handling subtraction and
comparison operations.
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Chapter - 3 (Input and Output System)
Peripheral devices
eripheraldevicesareexternalhardwarecomponentsconnectedtoacomputer
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system that provide input, output, or storage functions. Thesedevicesextend
the capabilities of the computer and allow users to interact with it. Here are
some common types of peripheral devices:
Input Devices:
1. Keyboard:
● Allows users to input text and commands into the computer by
pressing keys.
2. Mouse:
● Provides a pointing device for navigating graphicaluserinterfaces
(GUIs) and interacting with on-screen elements.
3. Touchpad:
● Similar to a mouse, it allows users to control the cursor on the
screen by moving their finger across a touch-sensitive surface.
4. Trackball:
● Astationarypointingdevicewheretheuserrotatesaballwiththeir
fingers to move the cursor.
5. Scanner:
● Converts physical documents, images, or objects into digital
formats that can be stored or manipulated on the computer.
6. Webcam:
● Captures video and images, allowing for video conferencing,
streaming, and video recording.
7. Microphone:
● Records audio input, enabling voice commands, audio recording,
and communication.
Output Devices:
1. Monitor:
● Displays visual output from thecomputer,includingtext,images,
videos, and graphical user interfaces.
2. Printer:
● Produces hard copies of digital documents, images, or other
content stored on the computer.
3. Projector:
● Projects visual output onto a large screen or surface, useful for
presentations, meetings, and multimedia displays.
4. Speakers:
● Output audio from the computer, including music, sound effects,
and spoken text.
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5. Headphones:
● Provide audio output for private listening, especially useful in
environments where sound needs to be contained.
Storage Devices:
1. Hard Disk Drive (HDD):
● Stores and retrieves data on spinning magnetic disks, providing
large storage capacities for files, applications, and operating
systems.
2. Solid State Drive (SSD):
● Similar to an HDD but uses flash memory for faster read/write
speeds and increased durability.
3. USB Flash Drive:
● Portable storage device that uses flash memory to store data and
can be easily connected to computers via USB ports.
4. External Hard Drive:
● Similar to internal HDDs but housed in an external enclosure,
providing additional storage capacity and portability.
5. Memory Card:
● Small, removable storage devices used in cameras, smartphones,
and other devices to store digital data.
Input – output interface
n input-output interface, often abbreviated as I/O interface, is a set of
A
hardware and software components that facilitate communication between a
computerandexternaldevices,allowingfortheexchangeofdata,instructions,
andcontrolsignals.Theinterfacemanagestheflowofinformationbetweenthe
computer's central processing unit (CPU) and peripheral devices, such as
keyboards, mice,displays,printers,storagedevices,andnetworkconnections.
Here's an overview of the key components and functions of an input-output
interface:
Hardware Components:
1. Ports:
● Physical connectors or sockets on the computer that allow
peripheral devices to be connected.
● Examples include USB ports, Ethernet ports, HDMI ports, audio
jacks, and serial ports.
2. Controller Chips:
● Integratedcircuitsresponsibleformanagingdatatransferbetween
the CPU and peripheral devices.
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● E
ach type of peripheral typically requires its own controller chip,
such as USB controllers, Ethernet controllers, or display
controllers.
3. Data Buses:
● Electricalpathwaysorchannelsthatenabledatatransferbetween
the CPU, memory, and peripheral devices.
● Busesmaybeparallelorserialandcanhavedifferentdatatransfer
speeds and widths.
4. Drivers:
● Softwareprogramsthatprovideaninterfacebetweentheoperating
system and specific hardware devices.
● Drivers facilitate communication by translating high-level
commands and data formats used by the operating system into
low-level signals and protocols understood by the hardware.
Software Components:
1. Device Drivers:
● Operating system components responsible for managing
communication with peripheral devices.
● Devicedriversenabletheoperatingsystemtorecognize,configure,
and control hardware devices connected to the computer.
2. I/O Subsystems:
● Softwarelayerswithintheoperatingsystemthatmanageinputand
output operations.
● I/O subsystems coordinate data transfer between applications,
device drivers, and peripheral devices, ensuring efficient and
reliable communication.
3. File Systems:
● Software components responsible for organizing and managing
data stored on storage devices such as hard drives, solid-state
drives, and memory cards.
● File systems provide a hierarchical structure for organizing files
and directories, as well as mechanisms for reading from and
writing to storage media.
Functions:
1. Data Transfer:
● Facilitates the exchange of data between the CPU and peripheral
devices, allowing input data to be received from external sources
and output data to be sent to external destinations.
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2. Device Control:
● Enables the CPU to configure and control the operation of
peripheral devices, such as setting display resolutions, adjusting
audio volume, or controlling printer settings.
3. Error Handling:
● Detects and handles errors that may occur during data transfer,
such as communication failures, data corruption, or device
malfunctions.
4. Interrupt Handling:
● Manages interrupts generated by peripheral devices to signal the
CPU when input data is available or when output operations are
complete.
5. Protocol Conversion:
● Converts data formats, protocols, and signal levels between the
computer and external devices to ensure compatibility and
interoperability.
Isolated I/O
Isolated I/O, also known as memory-mapped I/O, is a technique used in
computer architecture to facilitate communication between the CPU and
peripheral devices. In isolated I/O, special memoryaddressesarereservedfor
interfacing with peripheral devices, allowing them to be accessed as if they
were memory locations. This approach simplifies the programming interface
and enables devices to be treated similarly to memory-mapped locations.
ere's how isolated I/O typically works:
H
1. Memory-Mapped Addresses:
● A portion of the address space is reserved for I/O devices.
● Each peripheral device is assigned a range of memoryaddressesthatit
can respond to.
● These addresses are mapped tospecificcontrolregistersordatabuffers
within the device.
2. Address Decoding:
● When the CPU issues a memory read or write operation, the memory
management unit (MMU) or address decoder identifies whether the
address corresponds to a memory location or an I/O device.
● If the address falls within the reserved range for I/O devices, the
operation is directed to the appropriate device instead of main memory.
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3. Accessing Peripheral Devices:
● To read from or write to a peripheral device,theCPUperformsmemory
read or write operations to the corresponding memory-mapped
addresses.
● For example, to send data to a device, the CPU writes the data to a
specific memory address reserved for that device. Similarly, to receive
data from a device, the CPU reads from the corresponding
memory-mapped address.
Advantages of Isolated I/O:
1. Simplified Programming:
● By treating I/O devices as memory-mapped locations,
programmers can use standard memory access instructions (e.g.,
load and store) to interact with devices.
● This simplifies the programming interface and reduces the
complexity of device interaction.
2. Efficient Data Transfer:
● Memory-mapped I/O allows forefficientdatatransferbetweenthe
CPU and peripheral devices without the need for special I/O
instructions or protocols.
● Data can be transferred using the same mechanisms as memory
access, leading to faster and more streamlined communication.
3. Hardware Integration:
● Isolated I/O facilitates tight integration between the CPU and
peripheral devices, as they can share the same address space.
● This integration simplifies system design and can lead to more
efficient hardware implementations.
Disadvantages of Isolated I/O:
1. Limited Address Space:
● Reserving a portion of the address space for I/O devices reduces
the available memory space for main memory.
● In systems with a limited address space, this may lead to
constraints on thenumberandsizeofperipheraldevicesthatcan
be supported.
2. Potential for Conflicts:
● If multiple devices are assigned overlapping memory-mapped
addresses, conflicts may occur when accessing the devices
simultaneously.
● Proper address allocation and decoding mechanisms are required
to avoid conflicts and ensure correct operation.
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IsolatedI/Oisawidelyusedtechniqueincomputerarchitectureforinterfacing
with peripheral devices. It offers simplicity, efficiency, and tight integration
between the CPU and peripherals, making it well-suited for a variety of
applications and system designs.
Memory mapped I/O
emory-mapped I/O is a technique used in computer architecture to enable
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communication between the CPU and peripheral devices by mapping the
control and status registers of these devices directly into the processor's
address space. In memory-mapped I/O, special memory addresses are
assigned to control and interact with the peripheral devices, making them
accessible to the CPU using standard memory read and write instructions.
Here's how memory-mapped I/O typically works:
1. Address Mapping:
● Each peripheral device is assigned a range of memory addresses in the
computer's address space.
● Thesememoryaddressesareusedtoaccessthecontrolregisters,status
registers, and data buffers of the peripheral devices.
2. Control and Status Registers:
● Each peripheral device typically has control registers for configuring its
operation and status registers for reporting its current state.
● These registers canbereadfromorwrittentobytheCPUtocontrolthe
device and monitor its activity.
3. Memory Access Instructions:
● To interact with peripheral devices, the CPU uses standard memory
access instructions such as load (read) and store (write).
● WhentheCPUaccessesamemoryaddresswithintherangereservedfor
a peripheral device, the memory management unit (MMU) or address
decoder recognizes it as an I/O operation rather than a memory
operation.
4. Data Transfer:
● Data transfer between the CPU and peripheral devices occurs through
memory read and write operations to the memory-mapped addresses
assigned to the devices.
● For example, to send data to a device, the CPU writes the data to a
specific memory-mapped address corresponding to the device's data
buffer. Similarly, to receive data from a device, the CPU reads fromthe
appropriate memory-mapped address.
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Advantages of Memory-Mapped I/O:
1. Simplified Programming:
● Memory-mapped I/O provides a uniform and simplified
programming interface for interacting with peripheral devices.
● Programmers can use standard memory access instructions to
access control and status registers, simplifying software
development.
2. Efficient Data Transfer:
● Data transfer between the CPU and peripheral devices can be
performedusingthesamemechanismsasmemoryaccess,leading
to efficient and streamlined communication.
3. Hardware Integration:
● Memory-mapped I/O facilitates tight integration between theCPU
and peripheral devices, as they share the same address space.
● This integration simplifies system design and can lead to more
efficient hardware implementations.
Disadvantages of Memory-Mapped I/O:
1. Limited Address Space:
● Reserving a portion of the address spaceformemory-mappedI/O
reduces the available memory space for main memory.
● In systems with a limited address space, this may lead to
constraints on thenumberandsizeofperipheraldevicesthatcan
be supported.
2. Potential for Conflicts:
● If multiple devices are assigned overlapping memory-mapped
addresses, conflicts may occur when accessing the devices
simultaneously.
● Proper address allocation and decoding mechanisms are required
to avoid conflicts and ensure correct operation.
Asynchronous data transfer: strobe & handshaking
synchronous data transfer techniques,suchasstrobeandhandshaking,are
A
usedincomputerarchitecturetofacilitatecommunicationbetweentwodevices
that operate at different speeds or have varying processing times. These
techniques ensure reliable data transfer without requiring both devices to be
synchronized to a common clock signal. Here's an overview of strobe and
handshaking techniques:
. Strobe Technique:
1
In the strobe technique,acontrolsignalcalledastrobeorclockpulseisused
to indicate the availability of data. The sender devicewaitsforastrobesignal
from the receiver device before transmitting data. Once the strobe signal is
53
r eceived, the sender transfersthedatatothereceiver.Thistechniqueensures
that data is transferred only when the receiver is ready to receive it.
Steps Involved:
1. Data Preparation:
● The sender device prepares the data to be transmitted.
2. Waiting for Strobe Signal:
● The sender device waits for a strobe signal from the receiver device.
3. Data Transfer:
● Upon receiving the strobe signal, the sender device transfers the
prepared data to the receiver.
4. Acknowledgment:
● Optionally,thereceiverdevicemaysendanacknowledgmentsignal
to indicate that the data transfer was successful.
. Handshaking Technique:
2
Handshaking is a more sophisticated asynchronous data transfer technique
that involves a predefined sequence of signals exchanged between the sender
andreceiverdevicestocoordinatedatatransfer.Handshakingtypicallyinvolves
multiple signals, such as request, acknowledge, ready, and busy signals, to
establish communication and ensure data integrity.
Steps Involved:
1. Request:
● The sender device sends a request signal to thereceiverdeviceto
initiate data transfer.
2. Acknowledgment:
● Upon receiving the request signal, the receiver device sends an
acknowledgment signal to indicate readiness to receive data.
3. Data Transfer:
● The sender device transfers the data to the receiver device.
4. Completion:
● After receiving the data, the receiver device sends a completion
signal to indicate successful data transfer.
5. Optional Flow Control:
● Handshaking may includeflowcontrolsignalstoregulatetherate
of data transfer and prevent data loss or overflow.
Advantages and Use Cases:
1. Flexibility:
● Asynchronous data transfer techniques like strobe and
handshaking allow devices with different speeds or processing
times to communicate effectively.
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2. Reliability:
● These techniques ensure reliable data transfer by coordinating
communication between sender and receiver devices.
3. Efficiency:
● Asynchronousdatatransfertechniquescanimproveoverallsystem
efficiency by minimizing idle time and maximizing throughput.
4. Compatibility:
● Thesetechniquesarecompatiblewithvarioustypesofdevicesand
communication protocols, making them widely applicable in
computer systems.
Programmed I/O
rogrammed I/O (Input/Output) is a basic method for transferring data
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between a CPU and peripheral devices in computer architecture. In
programmedI/O,theCPUdirectlycontrolsthedatatransferprocessbyissuing
commands and monitoring the status of the I/O devices. Here's how
programmed I/O typically works:
1. Command Issuance:
● TheCPUinitiatesdatatransferbywritingcommandstocontrolregisters
in the I/O devices.
● Commands may include read, write, start, stop, or reset operations,
depending on the type and functionality of the device.
2. Data Transfer:
● After issuing a command, the CPU waits for the I/O devicetocomplete
the requested operation.
● For output operations, the CPU writes data to be transferred to the
device's data register.
● For input operations,theCPUreadsdatafromthedevice'sdataregister
after the operation is completed.
3. Status Monitoring:
● While waiting for the I/O operation to complete, the CPU continuously
polls or checks the status of the I/O device.
● Status information may include flags or status registers indicating
whetherthedeviceisreadyfordatatransfer,busyprocessingaprevious
command, or encountering an error condition.
4. Interrupt Handling:
● Programmed I/OmayinvolvepollingthestatusofI/Odevicesinaloop,
which can be inefficient and consume CPU resources.
55
● T o alleviate this issue, interrupts can be used to asynchronously notify
theCPUwhenanI/Ooperationiscompletedorwhenthedevicerequires
attention.
● When an interrupt occurs, the CPU suspends its current task, handles
the interrupt, and executes aninterruptserviceroutine(ISR)toprocess
the I/O operation.
Advantages of Programmed I/O:
1. Simplicity:
● ProgrammedI/Oisstraightforwardtoimplementandunderstand,
making it suitable for basic I/O operations.
2. Control:
● The CPU has full control over the data transfer process, allowing
for precise timing and error handling.
3. Compatibility:
● Programmed I/O is compatible with a wide range of I/O devices
and communication protocols, making it versatile and widely
applicable.
Disadvantages of Programmed I/O:
1. CPU Overhead:
● Continuous polling of the I/O device status can consume CPU
resources and reduce overall system performance, especially in
systems with high I/O activity.
2. Inefficiency:
● Polling for device status can lead to inefficient use of CPUcycles,
particularly in systems with slow I/O devices or frequent
interrupts.
3. Limited Scalability:
● Programmed I/O may not scale well in systems with a large
number of I/O devices or high-speed data transfer requirements,
as it relies on the CPU to handle data transfer operations.
Interrupt initiated I/O
Interrupt-initiated I/O is a method used in computer systems to handle
input/output (I/O) operations more efficiently compared to the traditional
programmedI/Oapproach.Ininterrupt-initiatedI/O,theCPUinitiatesanI/O
operation and then continues executing other tasks while waiting for the I/O
operation to complete. When the I/O operation finishes, an interrupt is
generatedbytheI/OdevicetonotifytheCPU,whichthensuspendsitscurrent
task and handles the interrupt by servicing the I/O operation.
56
ere's how interrupt-initiated I/O typically works:
H
1. Initialization:
● The CPU initiates an I/O operation by sending a command to the I/O
device, specifying the operation to beperformed(e.g.,readorwrite)and
the data to be transferred.
2. Asynchronous Operation:
● After initiating the I/O operation, the CPU continues executing other
tasks without waiting for the operation to complete.
● This asynchronous operation allows the CPU to perform useful work
while waiting for slower I/O operations to finish, improving overall
system efficiency.
3. Interrupt Generation:
● WhentheI/Ooperationcompletes,theI/Odevicegeneratesaninterrupt
signal to notify the CPU.
● The interrupt signal typically triggers an interrupt request (IRQ) line
connected to the CPU, causing it to stop its current task andswitchto
the interrupt service routine (ISR) associated with the I/O operation.
4. Interrupt Service Routine (ISR):
● Upon receiving the interrupt signal, the CPU suspends its current task
and begins executing the ISR associated with the I/O operation.
● The ISR performs any necessary tasks related to the completed I/O
operation, such as processing the received data or updating status
information.
5. Resume Execution:
● After servicing the interrupt and completing the ISR, the CPU resumes
executionofthetaskthatwasinterrupted,oritmayswitchtoadifferent
task depending on the system's scheduling algorithm.
Advantages of Interrupt-Initiated I/O:
1. Improved Efficiency:
● Interrupt-initiated I/O allows the CPU to perform useful work
while waiting for I/O operations to complete, maximizing system
efficiency and throughput.
2. Reduced CPU Overhead:
● Unlike programmed I/O, which requires continuouspollingofthe
I/Odevicestatus,interrupt-initiatedI/OreducesCPUoverheadby
allowing the CPU to handle other tasks until an interrupt occurs.
57
3. Support for Multiple Devices:
● Interrupt-initiatedI/Oiswell-suitedforsystemswithmultipleI/O
devices, as each device can generate its own interrupt signal to
notify the CPU when its operation completes.
Disadvantages of Interrupt-Initiated I/O:
1. Complexity:
● Implementing interrupt-driven I/O requires additional hardware
and software support for handling interrupts, which can increase
system complexity and development effort.
2. Interrupt Handling Overhead:
● Handling interrupts introduces some overhead, such as context
switching and interrupt servicing, which may impact system
performance, especially in systems with high interrupt rates.
Basic idea of DMA
he basic idea behind Direct Memory Access (DMA)istooffloaddatatransfer
T
tasksfromtheCPUtoaspecializedDMAcontroller,therebyimprovingsystem
performance and efficiency. DMA allows devices like disk controllers,network
interfaces, and graphics cards to transfer data directly to and from memory
without CPU intervention, freeing up the CPU to perform other tasks
concurrently. Here's how DMA works:
1. CPU Initialization:
● The CPU sets up the DMA controller by configuring its registers and
providing it with information about the data transfer operation to be
performed.
● This includes specifying the source and destination addresses in
memory, the number of data bytes to transfer, and any control
parameters such as transfer mode and data width.
2. DMA Request:
● The device (e.g., a disk controller) requests DMA access to the system
bus by asserting a DMA request (DRQ) signal.
● The DMA controller detects the request and gains controlofthesystem
bus from the CPU.
3. Data Transfer:
● The DMA controller transfers data directly between the device and
memory without CPU intervention.
● Itreadsdatafromthedevice'sdataregistersandwritesittothespecified
destination address in memory, or vice versa.
● TheCPUremainsidleorcontinuesexecutingothertaskswhiletheDMA
controller handles the data transfer.
58
4. Interrupt Notification:
● Once thedatatransferiscomplete,theDMAcontrollermaygeneratean
interrupt signal to notify the CPU.
● The interrupt triggers an interrupt service routine (ISR) in the CPU,
allowing it to perform any necessary post-processing tasks or handle
errors.
Advantages of DMA:
1. Improved Performance:
● DMAreducesCPUoverheadbyallowingdatatransferoperationsto
be performed concurrently with CPU processing, leading to faster
overall system performance.
2. Efficient Data Transfer:
● DMA transfers data directly between devicesandmemorywithout
CPU intervention, minimizing latency and improving throughput.
3. Offloading CPU Burden:
● ByoffloadingdatatransfertaskstotheDMAcontroller,theCPUis
freed up to perform other tasks, improving system multitasking
and responsiveness.
4. Support for High-Speed Devices:
● DMA is particularly useful for high-speed devices such as disk
drives,networkinterfaces,andgraphicscards,whereefficientdata
transfer is critical for performance.
Disadvantages of DMA:
1. Complexity:
● DMA adds complexity to system design and programming,
requiring careful coordination between the CPU, DMA controller,
and devices to ensure proper data transfer and synchronization.
2. Potential for Bus Contention:
● DMA controllers compete with the CPU for access to the system
bus, which can lead to bus contention and performance
degradation if not managed effectively.
3. Resource Sharing Challenges:
● DMAcontrollersmustcoordinateaccesstosystemresourcessuch
as memory and I/O ports with other devices and the CPU,which
can be challenging in multi-device systems.
59
Chapter - 4 (Instruction Set and addressing modes)
Instruction codes
Instruction codes, often referred to as opcodes, are fundamental elements of
computer instruction sets. These codes represent the basic operations that a
processorcanperform,suchasarithmeticoperations,datamovement,control
flow operations, and input/output operations. Each instruction code
corresponds to a specific operation that the CPU can execute. Here's an
overview of instruction codes and their characteristics:
1. Operation Representation:
● Instruction codes arebinarypatternsthatrepresentdifferentoperations
supported by the CPU.
● Each instruction code corresponds to a specific operation, such as
addition,subtraction,multiplication,division,load,store,jump,branch,
etc.
2. Format:
● Instruction codes typically have fixed or variable-length formats,
depending on the architecture of the processor.
● Fixed-length instruction formatsallocateafixednumberofbitsforeach
instruction, simplifying instruction decoding and execution.
● Variable-lengthinstructionformatsallowinstructionsofdifferentlengths
to be encoded, providing flexibilityininstructionencodingbutrequiring
more complex decoding logic.
3. Mnemonics:
● Instruction codes are often represented using mnemonics, which are
human-readable symbols or abbreviations that correspond to specific
operations.
● Mnemonics make it easier for programmers to write and understand
assembly language code, as they provide intuitive representations of
instructions.
4. Encoding:
● Instruction codes are encoded usingbinarydigits(bits)accordingtothe
instruction set architecture (ISA) of the processor.
● Each instruction code consists of opcode bits thatspecifytheoperation
tobeperformed,alongwithadditionalfieldsthatmayindicateoperands,
addressing modes, or other parameters.
60
5. Execution:
● When a CPU fetches an instruction from memory, it decodes the
instruction code to determine the operation to be performed and any
associated operands or parameters.
● The CPU then executes the instruction by performing the specified
operation, potentially fetching additional data from memory,performing
calculations, updating register values, or modifying program flow based
on the instruction's semantics.
Example:
● In a hypothetical instruction set architecture, the opcode "0001" might
represent the ADD operation, while "0010" represents SUBTRACT, and
"0100" represents LOAD.
● Mnemonics corresponding to these opcodes could be ADD, SUB, and
LOAD, respectively.
Direct Addressing
In direct addressing, the operand of an instruction directly specifies the
memoryaddressofthedatatobeaccessedoroperatedon.Thismeansthatthe
memory address is explicitly encoded within the instruction itself. Direct
addressing is straightforward and efficient for accessing data located at fixed
memory locations. However, it is limited in flexibility, as it requires the
programmer to know the exact memory address of the operand at compile time.
xample:
E
LOAD R1, 1000 ; Load the contents of memory address 1000 into register R1
Indirect Addressing
In indirect addressing, the operand of an instruction contains a memory
address that points to the actual memory location where the data is stored.
Instead of directly specifying the memory address of the operand, the
instruction contains a pointer to the memory address. This allows for more
flexibility, as the memory address can be determineddynamicallyatruntime.
Indirect addressing is commonly used for implementing data structures such
as arrays and linked lists.
xample:
E
LOADR1,(R2) ;Loadthecontentsofthememorylocationpointedtobythe
value in register R2 into register R1
61
Effective Address
he effective address is the memory address that is computed by the
T
addressing mode of an instruction to determine the location of the operand.
The effective address is not explicitly encodedwithintheinstructionitselfbut
is calculated based on the addressing mode and any additional parameters
provided in the instruction. Effective address calculation allows for more
flexible and dynamic memory access, as it can take into account various
factors such as register values, displacement values, and index values.
xample
E
ADDR1,(R2)+10 ;Addthecontentsofthememorylocationpointedtobythe
value in register R2 plus an offset of 10 to the value in register R1
List of basic computer registers
asic computer registers play crucial roles in the operationofaCPU(Central
B
ProcessingUnit)bystoringandmanagingvarioustypesofdataduringprogram
execution. Here's a list of some common types of basic computer registers:
1. Program Counter (PC):
● Stores the memory address of the next instruction to be fetched and
executed.
● Increments automatically after each instruction fetch.
2. Instruction Register (IR):
● Holds the currently fetched instruction from memory.
● Decoded to determine the operation to be executed by the CPU.
3. Memory Address Register (MAR):
● Holds the memory address of data to be accessed (read fromorwritten
to) in main memory.
4. Memory Data Register (MDR):
● Holds the data being transferred between the CPU and main memory.
● For write operations, it holds data to be written into memory.
● For read operations, it holds data read from memory.
5. Accumulator (ACC):
● A general-purpose register used for arithmetic and logic operations.
● Often used to store intermediate results and final results of
computations.
62
6. Index Registers:
● Used for memory addressing calculations.
● Examples include Base Register (BR), Index Register (IX), and Stack
Pointer (SP).
7. Status Registers:
● Holdstatusflagsthatindicatevariousconditionsorresultsofarithmetic
and logic operations.
● Common flags include zero flag, carry flag, overflow flag, and sign flag.
8. Stack Pointer (SP):
● Points to the top of the stack in memory.
● Used for managing function calls, subroutine nesting, and local
variables.
9. Instruction Pointer (IP):
● Similar to the program counter, but used in architectures with
segmented memory models.
● Storestheoffsetwithinthecurrentcodesegmentofthenextinstruction
to be executed.
10. Data Registers:
● Hold data temporarily during arithmetic, logic, and data manipulation
operations.
● Examples include General-Purpose Registers (GPRs) and Floating-Point
Registers (FPRs).
11. Control Registers:
● Manage various aspects of CPU operation and system configuration.
● Examples include the Control Status Register (CSR), Program Status
Register (PSR), and Machine Status Register (MSR).
12. Vector Registers:
● Used in vector processing or SIMD (Single Instruction, Multiple Data)
operations to hold vectors or arrays of data.
omputerinstructions:memoryreference,registerreference&
C
input–output instructions
omputer instructions, also known as machine instructions, are the basic
C
operations that a CPU (Central Processing Unit) can execute. These
instructions manipulate data and control the operation of the computer
system. Instructions can be categorized into different typesbasedonthetype
63
f operands they operate on and the actions they perform. Here are three
o
common categories of computer instructions:
1. Memory Reference Instructions:
● Memory reference instructions operate on data stored in memory.
● These instructions typically involve loading data from memory into
registers, storing data from registers into memory, or performing
arithmetic or logic operations on data in memory.
● Examples include:
● Load (LD): Load data from memory into a register.
● Store (ST): Store data from a register into memory.
● Add (ADD), Subtract (SUB), Multiply (MUL), Divide (DIV): Perform
arithmetic operations on data in memory.
2. Register Reference Instructions:
● Register reference instructions operate on data stored in registers.
● These instructions perform arithmetic, logic, and data manipulation
operations directly on data stored in CPU registers.
● Examples include:
● Add (ADD), Subtract (SUB), Multiply (MUL), Divide (DIV): Perform
arithmetic operations on data in registers.
● Logical AND (AND), OR (OR), XOR (XOR): Perform bitwise logical
operations on data in registers.
● Move (MOV): Copy data between registers.
3. Input-Output (I/O) Instructions:
● Input-output instructions control the transfer of data between the CPU
and external devices, such as keyboards, displays, storage devices,and
communication interfaces.
● TheseinstructionsfacilitateinputfromexternaldevicesintotheCPUand
output from the CPU to external devices.
● Examples include:
● Input (IN): Transfer data from an input device to the CPU.
● Output (OUT): Transfer data from the CPU to an output device.
● Input-OutputControl(IOCTL):Controlandconfigureinput-output
devices.
Example Instructions:
● Memory Reference Instruction
LD R1, 1000 ; Load data from memory address 1000 into register R1
ST R1, 2000 ; Store the contents ofregisterR1intomemoryaddress
2000
64
● R
egister Reference Instruction:
ADD R1, R2, R3 ;AddthecontentsofregistersR2andR3and
store the result in register R1
MOV R2, R3 ; Copy the contents of register R3 into register R2
● I nput-Output Instruction
INR1,PORT ;Inputdatafromanexternaldeviceconnectedto
port PORT into register R1
OUT PORT, R2 ; Output the contents of register R2 to an
external device connected to port PORT
Block diagram & brief idea of control unit of basic computer
hecontrolunitisavitalcomponentoftheCPU(CentralProcessingUnit)ina
T
computer system. It coordinates and controls the execution of instructions,
managesdataflowbetweendifferentcomponentsoftheCPU,andensuresthat
instructions are executed inthecorrectsequence.Here'sablockdiagramand
a brief overview of the control unit:
Overview of Control Unit Components:
1. Instruction Decoder:
● Decodestheinstructionfetchedfrommemorytodetermineitstype
and operation.
● Generates control signals based on the instruction's opcode to
coordinate the execution of the instruction.
2. Program Counter (PC):
● Stores the memory address of the next instruction to be fetched.
● Increments automatically after each instruction fetch.
3. ALU (Arithmetic Logic Unit) Control Unit:
65
● C ontrols the operation of the ALU, including arithmetic and logic
operations.
● Generates control signals to specify the type of operation to be
performed based on the instruction.
4. Timing Generator:
● Generates timing signals to synchronize the operation of different
components of the CPU.
● Ensuresthatinstructionsareexecutedinthecorrectsequenceand
at the appropriate times.
5. Control Signals:
● Various control signals are generated by the control unit to
coordinate the activities of different CPU components.
● These signals include read and write signals for memory access,
enable signals for register transfers, and signals for ALU
operations.
6. Bus Interface:
● FacilitatescommunicationbetweentheCPUandothercomponents
of the computer system via the system bus.
● Controls the transfer of data and instructions between the CPU,
memory, and I/O devices.
Functionality of Control Unit:
● Fetches instructions from memory based on the address stored in the
program counter.
● Decodes the fetched instructions to determine their types and operations.
● Generates control signals to coordinate the execution ofinstructionsby
other CPU components.
● Manages the timing and sequencing of instruction execution to ensure
correct operation.
● Controls the transfer of data between the CPU and memory, registers,
and I/O devices via the system bus.
Instruction Cycle
he instruction cycle, also known as the fetch-decode-execute cycle, is the
T
fundamental process by which a CPU (Central Processing Unit) executes
instructions. It consists of a sequence of steps that the CPU performs
repeatedlyforeachinstructioninaprogram.Here'sanoverviewofthestagesof
the instruction cycle:
1. Fetch:
● In the fetch stage, the CPU retrieves the next instruction from memory.
● The memory address of the next instruction is stored in the program
counter (PC).
66
● T he CPU sends a memory read request to the memory controller,
specifying the address stored in the PC.
● The instruction is fetched from memory and stored in aspecialregister
called the instruction register (IR).
2. Decode:
● In the decode stage, the CPU decodes the fetched instruction to
determine its type and operation.
● The opcode (operation code) of the instruction is extracted from the
instruction register (IR).
● The control unit interprets the opcode and generates control signals to
coordinate the execution of the instruction.
● Depending on the opcode, the control unit may activate specific
components of the CPU, such as the ALU (Arithmetic Logic Unit) or
registers.
3. Execute:
● In the execute stage, the CPU performs the operation specified by the
decoded instruction.
● This may involve arithmetic or logic operations, data movement, or
control flow changes.
● The ALU performs arithmetic and logic operations, and data may be
transferred between registers or between registers and memory.
● The result of the operation is stored in registers or memory, depending
on the instruction.
4. Write Back (Optional):
● In some cases, after the execution stage, the CPU may perform a
write-backoperationtoupdateregistersormemorywiththeresultofthe
instruction.
● For example, after executing an arithmetic operation, theresultmaybe
stored back in a register or memory location specified by the instruction.
Repeat:
● After completing the execute (and optionally write-back) stage, the CPU
increments the program counter to point to the next instruction in
memory.
● The instruction cycle repeats, with the CPU fetching, decoding, and
executing the next instruction in sequence.
67
Figure - Instruction Cycle
68
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