Verilog Code
Expt. No.: 6 Multiplexer and Demultiplexer
4 t0 1 Line Multiplexer 1 to 4 Demultiplexer
a) Gate level module Practical1( module DeMuxGate(
modeling input [3:0] D, input D,
output Y0, input s0,s1,
input s0,s1 output y0,y1,y2,y3
); );
wire w0,w1,w2,w3; and(y0,D,~s0,~s1);
and(w0,D0,~s0,~s1); and(y1,D,s0,~s1);
and(w1,D1,s0,~s1); and(y2,D,~s0,s1);
and(w2,D2,~s0,s1); and(y3,D,s0,s1);
and(w3,D3,s0,s1); endmodule
or(Y0,w0,w1,w2,w3);
endmodule
b) Data Flow module DataFlowMux( module DataFlowDeMux(
modeling input [3:0] D, input D,
input s0,s1, input s0,s1,
output y0 input [3:0] y
); );
assign y0=(~s1&~s0&D[0])| assign y[0]=(~s1&~s0&D);
(~s1&s0&D[1])| assign y[1]=(~s1&s0&D);
(s1&~s0&D[2])| assign y[2]=(~s1&~s0&D);
(s1&s0&D[3]); assign y[3]=(s1&s0&D);
endmodule
endmodule
c) Behavioral module BehavioralMux( module BehavioralDeMux(
modeling input D0,D1,D2,D3, input D,
input s0,s1, input s0,s1,
output reg y0 output reg [3:0] y
); );
always @(D0,D1,D2,D3,s0,s1) always @(D,s0,s1)
begin begin
case({s1,s0}) if(s0==0&&s1==0)
2'b00:y0=D0; y[0]=D;
2'b01:y0=D1; else if (s0==1&&s1==0)
2'b10:y0=D2; y[1]=D;
2'b11:y0=D3; else if (s0==0&&s1==1)
default:y0=0; y[2]=D;
endcas0065 else if (s0==1&&s1==1)
end y[3]=D;
endmodule end
endmodule
Expt. No.: 7 Arithmetic Circuits
Half Adder – module Half_Adder (x, y, Sum, Carry);
Gate level modelling input x, y; // Input A and B
output Sum, Carry; // Sum output
xor (Sum, x, y); // XOR gate for Sum
and (Carry, x, y); // AND gate for Carry
endmodule
Half Adder – module Half_Adder (x, y, Sum, Carry);
Data flow modelling input x, y; // Input A and B
output Sum, Carry; // Sum output
assign Sum = x ^ y; // XOR for Sum
assign Carry = x & y; // AND for Carry
endmodule
module Full_Adder (x, y, z, Sum, Cout);
Full Adder – Gate level modelling input x, y, z ; // Input x, y,z
output Sum, Cout ; // Sum output
wire S1, C1, C2; // Intermediate wires
xor (S1, x, y); // XOR gate for first stage
xor (Sum, S1, z); // XOR gate for final sum
and (C1, x, y); // AND gate for first carry
and (C2, S1, z); // AND gate for second carry
or (Cout, C1, C2); // OR gate for final carry-out
endmodule
module Full_Adder (x, y, z, Sum, Cout);
Full Adder – Data flow modelling input x, y, z ; // Input x, y,z
output Sum, Cout ; // Sum output
assign Sum = x ^ y ^ z; // XOR for Sum
assign Cout = (x & y) | (y & z) | (z & x); //
Carry-out logic
endmodule
Expt. No.: 8 Design of Flip-Flops
T Flip Flop
module T_FlipFlop (
input clk, // Clock signal
input reset, // Reset signal
input T, // T input (toggle control)
output reg Q // Output Q
);
always @(posedge clk or posedge reset)
begin
if (reset)
begin
Q <= 1'b0; // Reset Q to 0
end
else if (T)
begin
Q <= ~Q; // Toggle Q when T is 1
end
// If T is 0, Q remains unchanged
end
endmodule
D Flip Flop
module D_FlipFlop (
input D, // Data input
input clk, // Clock signal
input reset, // Reset signal
output reg Q // Output Q
);
// Dataflow logic for D flip-flop
always @(posedge clk)
begin
if (reset)
Q <= 1'b0; // Reset Q to 0
else
Q <= D; // On clock edge, assign D to Q
end
endmodule
JK FP
module JK_FlipFlop
input J, // J input
input K, // K input
input clk, // Clock signal
input reset, // Reset signal
output reg Q // Output Q
);
always @(posedge clk or posedge reset)
begin
if (reset) begin
Q <= 1'b0; // Reset Q to 0
end
else
begin
case ({J, K})
2'b00: Q <= Q; // No change
2'b01: Q <= 1'b0; // Reset Q to 0
2'b10: Q <= 1'b1; // Set Q to 1
2'b11: Q <= ~Q; // Toggle Q
endcase
end
end
endmodule
SR flip flop using Dataflow modelling
module SR_FlipFlop_Dataflow (
input S, // Set input
input R, // Reset input
input Qn, // Current state Q(n)
output Qn1 // Next state Q(n+1)
);
// Define the next state based on the given equation
assign Qn1 = S | (~R & Qn);
endmodule
SR flip flop using Behavioral modeling
module SR_FlipFlop (
input S, // Set input
input R, // Reset input
input clk, // Clock signal
input reset, // Asynchronous reset
output reg Q, // Output Q
output Q_bar // Complement of Q
);
// Generate Q_bar using dataflow assignment
assign Q_bar = ~Q;
always @(posedge clk or posedge reset)
begin
if (reset)
begin
Q <= 1'b0; // Reset Q to 0
end
else
begin
case ({S, R})
2'b00: Q <= Q; // No change
2'b01: Q <= 1'b0; // Reset
2'b10: Q <= 1'b1; // Set
2'b11: Q <= 1'bx; // Invalid condition
endcase
end
end
endmodule
Expt. No.9 : Design of Shift Registers
1. PISO:
module PISO_Shift_Register(
input clk,
input reset,
input load, // Load control signal
input [3:0] parallel_in, // Parallel input data
output reg serial_out // Serial output
);
reg [3:0] shift_reg;
always @(posedge clk or posedge reset)
begin
if (reset) begin
shift_reg <= 4'b0000;
serial_out <= 1'b0;
end else if (load) begin
shift_reg <= parallel_in; // Load parallel data into the shift register
end else begin
serial_out <= shift_reg[3]; // Output MSB
shift_reg <= shift_reg << 1; // Shift left
end
end
endmodule
PIPO
module PIPO_Shift_Register(
input clk,
input reset,
input load, // Load control signal
input [3:0] parallel_in, // Parallel input data
output reg [3:0] parallel_out // Parallel output
);
always @(posedge clk or posedge reset)
begin
if (reset)
begin
parallel_out <= 4'b0000;
end else if (load)
begin
parallel_out <= parallel_in; // Load and output parallel data
end
end
endmodule
SISO
module SISO_Shift_Register(
input clk,
input reset,
input serial_in, // Serial input
output reg serial_out // Serial output
);
reg [3:0] shift_reg;
always @(posedge clk or posedge reset)
begin
if (reset)
begin
shift_reg <= 4'b0000;
serial_out <= 1'b0;
end
else
begin
shift_reg <= {shift_reg[2:0], serial_in}; // Shift left and input new bit
serial_out <= shift_reg[3]; // Output MSB
end
end
endmodule
SIPO
module SIPO_Shift_Register(
input clk,
input reset,
input serial_in, // Serial input
output reg [3:0] parallel_out // Parallel output
);
reg [3:0] shift_reg;
always @(posedge clk or posedge reset)
begin
if (reset)
begin
shift_reg <= 4'b0000;
parallel_out <= 4'b0000;
end
else
begin
shift_reg <= {shift_reg[2:0], serial_in}; // Shift left and input new bit
parallel_out <= shift_reg; // Update parallel output
end
end
endmodule
