DIGITAL

ELECTRONIC

Chapter One
 SYNCHRONOUS SEQUENTIAL LOGIC
 A sequential circuit is a logic circuit that employ memory elements
in addition to (combinational) logic gates.
 Their outputs are determined from the state of the memory cells (as
well as the present input combination).
 The state of the memory elements, in turn, is a function of the
previous inputs (and the previous state).
 Its behavior therefore is specified by a time sequence of inputs and
internal states.
 The binary information stored in the memory elements (flip-flops)
at any given time defines the state of the sequential circuit.
 Example : Ring counter that starts the answering machine
after 4rings
 Sequential components can be
(1) Asynchronous or
(2) Synchronous
 An asynchronous sequential circuit changes their
states and output values whenever a change in input
values occurs.
 Its behavior depends on the order in which its input
signals change and
 can be affected at any time.
 A synchronous sequential circuit changes their states
and output values at fixed points of time, which are
specified by the rising and/or falling edge of a free-
running clock signal.
 Its behavior is defined at discrete instants of time.
 A synchronous sequential circuit can be modeled by a
finite state machine (FSM):
 A synchronous sequential circuit changes their
states and output values at fixed points of time,
which are specified by the rising and/or falling
edge of a free-running clock signal.
 Its behavior is defined at discrete instants of
time.
 Synchronization usually is achieved by a timing device
called a clock generator, which generates a periodic train of
clock pulses distributed throughout the system to trigger
the memory elements.
 A synchronous sequential circuit can be modeled by a finite
state machine (FSM):
FLIP FLOPS (FFS)

 The most important memory element is the flip-flop, which is

made up of an assembly of logic gates.
 Even though a logic gate, by itself, has no storage capability,
several can be connected together in the ways that permit
information to be stored.
 Several different gate arrangements are used to produce these
flip-flops (FF).
 Two outputs, labeled Q and Q’, That are the inverse of each
other.
CONT’D…
 Note that the High or 1 state (Q=1/Q’=0) is also referred to as the
SET state.
 Whenever the inputs to a FF cause it to go to the Q=1 state, we
call this setting the FF; The FF has been set.
 Similarly, LOW or 0 state (Q’=1/Q=0) is referred to as the CLEAR
or RESET state.
 Whenever the inputs to a FF cause it to go to the Q=0 state, this
is clearing or setting the FF.
 Fig above implies that a FF can have one or more inputs that are
used to cause the FF to switch back and forth (Flip-Flop) between
its possible output states.
 The FF inputs need only to be momentarily activated (Pulsed) in
order to cause a change in the FF o/p state.
 The O/p will remain in that new state even after the input pulse
is over. This is the FF’s memory characteristics
SR LATCH
 The SR latch is a basic memory element (FF)
which can store one bit of information.
 It consists of two cross-coupled NOR gates or two
cross-coupled NAND gates.

 It has two input signals, the Set signal (S) and the
Reset signal ®
 It has two output signals, Q and Q’.
 It has two states, the Set state (when Q= 1 and Q’ =
0) and the Reset signal (when Q = 0 and Q’ = 1)
RESETING AND CLEARING

Setting

Clearing
 Simultaneous Setting and Clearing
 When SET and CLEAR are both pulsed LOW, it will produce HIGH
level at both NAND o/p. this is an undesired condition since both o/p
has to be in inverse.
 Simultaneous transition of SET and CLEAR back to 1 produces
unpredictable o/p. for this reason SET=CLEAR=0 is not normally
used in NAND Latchs.
 From the description of the NAND latch operation, it the SET and
CLEAR inputs are active-LOW (fig 2).
 Therefore the NAND gate can be alternatively represented by Fig 1.

Fig 1 Fig 2
APPLICATION: NAND SWITCH
It is virtually impossible to
obtain a clean voltage transition
form a mechanical switch. Due
to contact bounce.

The multiple Transition on the

o/p signal generally (~ms) but
This is unacceptable. A NAND
Can be used to prevent the
Switch bounce.
APPLICATION 2: BURGLAR ALARM
 The light is focused on a phototransistor that is connected
in the common-emitter configuration to operate as a switch.
 Assume that the latch has previously been cleared to the 0
state by momentarily opening switch SW1.
 what will happen if the light beam is momentarily
interrupted.
With light on phototransistor, we
Can assume that it is fully conducting
So that resistance between the collector
And emitter is very small.
Thus v0 will be 0 V. SET = 0, CLEAR = 0
NOR
When light beam is interrupted?
Phototransistor turns off, and its CE
Resistance becomes very high (open ckt)
v0 =5 V. SET = 1, Alarm = ON
CLOCKED SIGNAL AND CLOCKED FF
 Digital Systems can operate either Asynchronously or Synchronously.
 In ASYN, the o/p of logic ckts can change state any time one or more
of the inputs change. It is generally more difficult to design and
troubleshoot than SYN system.
 In SYN systems, the exact times at which any o/p can change states
are determined by a signal commonly called the CLOCK.
 This clock signal is generally a rectangular pulse train or a square
wave as shown fig below.
 It is distributed to all parts of the system and most of the system o/p
can change state only when the clock makes a transition (edges).
 When the clock changes from a 0 to a 1, this is called the Positive-
going-transition (PGT), when it changes 1 to 0, it Negative-going-
transition (NGT).
 In SYN, almost everything is synchronized to the clock-signal
transition.
 The Synchronizing action of the clock signals is accomplished through
the use of clocked FFs that are designed to change states on one or
the other of the clock’s transition.
 CLOCKED FFS
 Several types of clocked FFs are used in a wide range of applications.
Before we begin our study of the different clocked FFs, we will describe
the principal ideas that are common to all of them.
 1. clocked FFs have a clock input that is typically labeled CLK, CK, CP.
 FF with a small triangle on its CLK input to indicate that this input
is activated only when PGT occurs
 FF with bubble as well as a triangle on its CLK input, the CLK input
is activated only when a NGT occurs
 2. Clocked FFs also have one or more control inputs that can have
various names, depending on their operation.
 This control inputs will have no effect on Q until the active clock
transition occurs.
 3. We can say, that the control inputs get the FF o/p ready to change,
while the active transition at the CLK input actually triggers the change.
 The control inputs controls the WHAT (what state the o/p will go to);
the CLK input determines the WHEN.
 Two timing requirements must be met if a clocked FF is to respond
reliably to its control inputs when the active CLK transition occurs.
 Setup time (ts) is the time Interval immediately preceding The active
transition of the CLK Signal during which the control Input must be
maintained At the proper level.
 Hold time (th) is the time Interval immediately following The active
transition of the CLK Signal during which the control Input must be
maintained At the proper level.

The control input must be

Stable for at least (th + ts)
Typicaly FFS have ts (5 – 50ns),
th (0 – 10ns).
CLOCKED SR FF
 Fig below shows a clocked SR FF that is PGT. The S and R inputs
control the state of the FF in the same manner as described
earlier for the NOR gate latch at PGT.
o The S and C inputs are SYN control inputs; they control which
state the FF will go to when the clock pulse occurs; the CLK input
is the trigger input that causes the FF to change states according
to what the S and C input are when the active clock transition
occurs.
o The circuit contains three sections
o A basic NAND latch formed by NAND-3 and NAND-4
o A pulse-steering ckt formed by NAND-1 and NAND-2
o An edge-detector ckt
 CLOCKED J-K FF
 Fig below shows a clocked J-K FF that is triggered by PGT of CLK.
 The J and K input control the state of the FF in the way as the S
and C input do for the clocked S-C FF except one condition
 In J-K FF, when J=K=1 condition does not result ambiguous o/p .
 At this condition the FF will always go to its opposite state upon PGT.
 This is called toggle mode of operation.
Note: FF is not affected by NGT
J and K i/p levels have no effect
Except upon the occurrence of the
PGT of the clock signal.
CLOCKED D FF
 Unlike S-C and J-K, Clocked/Edge-triggered D FF has only one
SYN control i/p, D, which stands for data.
 The operation of D FF is, Q will go to the same state that is
present on D i/p when PGT occurs at CLK.
 Assuming Q is initially HIGH
D LATCH/TRANSPARENT
 The edge-triggered D FF uses an edge-detector ckt to ensure that the
o/p will respond to the D i/p only when the active transition of the clock
occurs.
 If this edge detector is not used, the resultant ckt operates somewhat
differently, it is called D latch

Note: even though the EN i/p operates as CLK i/p of an edge triggered FF,
There is no small triangle on the EN i/p. this symbol is for i/p that cause an
o/p change only when a transition occurs. The D latch is not edge-triggered.
When EN is High, Q o/p
Will look like exactly as D.
At this time D latch is Transparent

When EN is Low, The o/p are latched

To their current value and can not
even if D is Changed.
 Before the development of edge triggered FFS, with little or no hold
time requirement, timing problem was often handled by using a a class
of FF called Master/Slave FFS.
 A Master/slave FF actually contains two FFs, a master and Slave.
When the CLK signal goes low, the level on the control input (D,J,K)
are used to determine the o/p of the master.
 On the rising edge of the CLK, the state of the master is transferred to
the slave, whose o/p is Q and Q’.
 Thus Q and Q’ change just after PGT of the clock.
ASYNCHRONOUS INPUT
 For the clocked FFs (S,C,J,K and D) i/ps have been referred to as control
input. These i/p are also called SYN i/p because their effect on the FF o/p
is synchronized with the CLK i/p.
 Most of clocked FFs also have one or more asynchronous i/p which operate
independently of the SYN i/p.
 These ASYN i/p can be used to set the FF to the 1 state or clear the FF to
the 0 state at any time regardless of the condition at the other i/p.
 These are called OVERIDE INPUTS.
ANALYSIS OF A SEQUENTIAL CIRCUITS
 The analysis of a sequential circuit consists of obtaining a
table or a diagram for the time sequence of inputs, outputs,
and internal states: the state table or the state diagram.
 The relationship that exists among the inputs, outputs,
present states and next states can be specified by either the
state table or the state diagram.
 It is also possible to write Boolean expressions including
the necessary time sequence.
 State Table
 The state table representation of a sequential circuit
consists of three sections labeled present state, next state
and output.
 The present state designates the state of flip-flops before the
occurrence of a clock pulse.
 The next state shows the states of flip-flops after the clock
pulse,
 the output section lists the value of the output variables
during the present state.
State Diagram
 In addition to graphical symbols, tables or equations, flip-flops can also be
represented graphically by a state diagram.
 In this diagram, a state is represented by a circle, and the transition between
states is indicated by directed lines (or arcs) connecting the circles.
 An example of a state diagram is shown in Figure below
The binary number inside each circle
identifies the state the circle represents. The
directed lines are labeled with two binary
numbers separated by a slash (/). The input
value that causes the state transition is
labeled first. The number after the slash
symbol / gives the value of the output.
The behavior of the circuit is determined by the following Boolean expressions:

EXAMPLE
 Consider a sequential circuit shown in Figure below. It has one
input x, one output Z and two state variables Q1Q2 (thus having
four possible present states 00, 01, 10, 11).

These equations can be used to form the state

table.
Suppose the present state (i.e. Q1Q2) = 00
Suppose
and input x = 0. Under these conditions, we
get Z = 0, D1 = 1, and D2 = 1.
Thus the next state of the circuit D1D2 = 11,
and this will be the present state after the
clock pulse has been applied.
The output of the circuit corresponding to
The behavior of the ckt can be the present state Q1Q2 = 00 and x = 1 is Z = 0.
expressed as :
Z = x * Q1
D1 = x' + Q1
D2 = x * Q2' + x' * Q1'
State table for the sequential circuit State Diagram for the sequential circuit
FLIP FLOP TYPES
 We assume only positive (rising) edge-triggered FFs.
 SR (Set-Reset), JK, D (data), and T(toggle) FFs are four
major FFs commonly used.
 The characteristic table gives for every input and
state combination before the rising edge of clk the
corresponding state of the FF after the falling edge of
clk.
 A characteristic equation for each FF can be derived from
the characteristic table using the map method
 The excitation table is derived from the characteristic
table by transposing input and output columns.
 It gives the value of the FF inputs that are necessary to
change the FF’s present state to the desired next state.
 What should be the value of the control i/ps to get the
desired next state from the present state.?
ANALYZING PROCEDURE
 Given a logic schematic, the analysis procedure is
as follows:
1. Derive excitation equations
2. Derive next-state and output equations
3. Generate next-state and output tables
4. Generate state diagram
5. Develop timing diagram
6. Simulate logic schematic
3
For the given value of current state, What is the value
of FF i/p to get the next state value?

It gives the value of the FF inputs that are necessary to

change the FF’s present state to the desired next state
  In Synchronous counters/design all of the FFs are clocked at the same
time. Before each clock pulse, the J and K input of each FF in the counter
must be at the correct level to ensure that the FF goes to the correct state.
 E.g. consider the situation shown below. When the next clock pulse occurs,
the J and K input of the FFs must be at the correct levels that will cause
flip-flop C to change from 1 to 0, FF B from 0 – 1 and FF A from 1 o 1 (no
change).

o The Process of designing a Synch Counter, then, becomes one of the designing
The logic ckt that decode the various states of the counter to supply the logic
Levels to each J and K i/p.
The i.ps to these decoder ckts will come from the o/p of One or more of the FFs
EXAMPLE 1:
 Design a Syn sequential ckt that behaves (counts) as (000, 001,
010, 011, 100, 000, 001…)
 Design Procedure:
 We will now go through a complete Syn counter design
procedure.

We have 5 states, with three bits we can have 8 states----> 3 States are
undesired.(101, 110, 111) 110 101
000
Therefore we need 3 FFs.
100 001 111

011 C=1 010

  Step Three: Generate the next state and o/ table
using state transition diagram
 Step Four: Drive next state * * *
and o/p equations.

A’ A
C’B’ 001 010
C’B 011 100
CB 000 000 A’ A
CB’ 000 000 C’B’ 0 0
C*B*A* C’B 0 1

Next State Table 0 0

CB

CB’ 0 0
C*
 A’ A A’ A A’ A
C’B’ 0 0 C’B’ 0 1 C’B’ 1 0
C’B 0 1 C’B 1 0 1
C’B 1 0
CB 0 0 CB 0 0 CB 0 0
CB’ 0 0 CB’ 0 0 CB’ 0 0
C* B* A*

 Next state Equation:

 C* = C’BA B* = C’BA’ + C’B’A A* = A’C’

 Now choose implementation? Exitationn Equations

 Step Five: Choose Memory Element and Drive
excitation Equation. (We choose J and K)
Drive the excitation equation :

A’ A A’ A
C’B’ 001 010 C’B’ 0x 0x 1x 0x 1x x1
C’B 011 100
C’B 0x x0 1x 1x x1 x1
CB 000 000
CB’ 000 000 CB x1 x1 0x x1 x1 x1

C*B*A* CB’ x1 0x 0x x1 0x x1
JCKC, JBKB, JAKA
K-MAP
A’ A

C’B’ x 1 KA = 1, Similarly;
C’B x 1
CB x 1
CB’ x 1
KA
STEP SIX: LOGIC IMPLEMENTATION