SEQUENTIAL LOGIC CIRCUIT SEQUENTIAL CIRCUIT: + Itis a circuit whose output depends upon the present input, previous output and the sequence in which the inputs are applied HOW THE SEQUENTIAL CIRCUIT IS DIFFERENT FROM COMBINATIONAL CIRCUIT? :- + In combinational circuit output depends upon present input at any instant of time and do not use memory. Hence previous input does not have any effect on the circuit. But sequential circuit has memory and depends upon present input and previous output. * Sequential circuits are slower than combinational circuits and these sequential circuits are harder to design. SEQUENTIAL LOGIC Input Output m CIRCUIT = Ou Memory fe Clock ] J L [Block diagram of Sequential Logic Circuit] + The data stored by the memory element at any given instant of time is called the present state of sequential circuit IYPES:- Sequential logic circuits (SLC) are classified as () Synchronous SLC (i) Asynchronous SLC ‘© The SLC that are controlled by clack are called synchronous SLC and those which are not controlled by a clock are asynchronous SLC. ‘© Clock:- A recurring pulse is called a clock. ‘LOP AND LATC! * A flip-flop or lateh is a circuit that has two stable states and can be used to store information. «A flipclop is a binary storage device capable of storing one bit of information. In a stable state, the output of a flip-flop is either 0 or 1 + Latchis a non-clocked flip-flop and itis the building block for the flip-flop. + A storage element in digital circuit can maintain a binary state indefinitely until directed by an input signal to switch state. * Storage element that operate with signal level are called latches and those operate with clock transition are called as fip-fops.The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. A flip-flop is called so because its output either flips or flops meaning to switch back and forth. A flip-flop is also called a bi-stable muli-vibrator as it has two stable states. The input signals which ‘command the flip-flop to change state are called excitations. Flip-flops are storage devices and can store 1 or 0. Flip-flops using the clock signal are called clocked flip-flops. Control signals are effective only if they are applied in synchronization with the clock signal Clock-signals may be positive-edge triggered or negalive-edge triggered. Positive-edge triggered flip-flops are those in which state transitions take place only at positive- going edge of the clock pulse. Negative-edge triggered flip-flops are those in which state transition take place only at negalive- going edge of the clock pulse. JUuUL ‘Some common type of flip-flops include a) SR (set-reset) F-F b) D (data or delay) F-F ¢) T (toggle) F-F and 0) JKF-F SR latch The SR latch is a circuit with two cross-coupled NOR gates or two cross-coupled NAND gates. It has two outputs labeled Q and Q’. Two inputs are there labeled S for set and R foe reset. The latch has two useful states. When Q=0 and Q’=1 the condition is called reset state and when Q=1 and Q'=0 the condition is called set state. Normally Q and Q are complement of each other. The figure represents a SR latch with two cross-coupled NOR gates. The circuit has NOR gates and as we know if any one of the input for a NOR gate is HIGH then its output will be LOW and if both the inputs are LOW then only the output will be HIGH. ' 0 Reset) —o Under normal conditions, both inputs of the latch remain at 0 unless the state has to be changed. The application of a momentary 1 to the S input causes the latch to go to the set state. The S input must go back to 0 before any other changes take place, in order to avoid the occurrence of an undefined next state that results from the forbidden input condition, The first condition (S = 1, R the action that must be taken by input § to bring the circuit to the set state. Removing the active input from S leaves the circuit in the same state. After both inputs return to O, itis then possible to shift to the reset state by momentary applying a 1 to the R input. The 1 can then be removed from R, whereupon the circuit remains in the reset state. When both inputs S and R are equal to 0, the latch can be in either the set or the reset stale, depending on which input was most recently a 4«If 1 is applied to both the S and R inputs of the latch, both outputs go to 0, This action produces an undefined next state, because the state that results from the input transitions depends on the order in which they retum to 0. It also violates the requirement that outputs be the complement of each other. In normal operation, this condition is avoided by making sure that 1's are not applied to both inputs simultaneously. ‘+ Truth table for SR latch designed with NOR gates is shown below. Input Output Comment s R a e Qhee en oO 0 0 1 o 1 No change a o 7 0 7 a 0 7 0 7 0 7 Reset oO 1 1 oO o 1 i a o i 7 a Set 7 0 7 0 7 a 7 7 0 7 x x Prohibited 7 7 1 0 x x state See Symbol for SR NOR Latch Racing Condition:- In case of a SR latch when S-R=1 input is given both the output will try to become 0. This is called Racing condition. SR latch using NAND gate:- ‘* The below figure represents a SR latch with two cross-coupled NAND gates. The circuit has NAND gates and as we know if any one of the input for a NAND gate is LOW then its output will be HIGH and if both the inputs are HIGH then only the output will be LOW. ‘+ It operates with both inputs normally at 1, unless the state of the latch has to be changed. The application of O to the S input causes output Q to go to 1, putting the latch in the set stale. When the S input goes back to 1, the circuit remains in the set state. After both inputs go back to 1, we are allowed to change the state of the latch by placing a 0 in the R input. This action causes the circuit to go to the reset state and stay there even after both inputs return to 1. i 0 ” Q — » LI y =. ‘+ The condition that is forbidden for the NAND latch is both inputs being equal to 0 at the same time, an input combination that should be avoided.In comparing the NAND with the NOR latch, note that the input signals for the NAND require the complement of those values used for the NOR latch. Because the NAND latch requires a 0 signal to change its state, it is sometimes referred to as an S'R’ latch. The primes (or, sometimes, bars over the letters) designate the fact that the inputs must be in their complement form to activate the circuit a — SR ‘The above represents the symbol for inverted SR latch or SR latch using NAND gate, Truth table for SR latch using NAND gale or Inverted SR latch s R ons Oren 0 0 Race Race 0 1 0 1 (Reset) 4 0 4 0(Set) 1 1 (No change) "(No change) DLATCH © One way to eliminate the undesirable condition of the indeterminate state in the SR latch Is to ensure thal inputs $ and R are never equal to 1 at the same time. D [> DB ’ tn poD—D—" (a) Loge éayrim ‘* This is done in the D latch. This latch has only two inputs: D (data) and En (enable). ‘* The D input goes directly to the S input, and its complement is applied to the R input. D (Symbol for D-Latch) * As long as the enable input is at 0, the cross-coupled SR latch has both inputs al the 1 level and the circuit can't change state regardless of the value of D. ‘+ The below represents the truth table for the D-latch. En D Next State of Q No change ‘Q=0;Reset Stale x 0 1FLIP. The D input is sampled when En = 4. If D = 1, the Q output goes to 1, placing the circuit in the set state, If D = 0, output Q goes to 0, placing the circuit in the reset state, This situation provides a path from input D to the output, and for this reason, the circuit is often called a TRANSPARENT latch. RIGGERING METHODS:- The state of a latch or flip-flop is switched by a change in the control input. This momentary change is called a trigger, and the transition it causes is said to trigger the flip-flop. Flip-fop circuits are constructed in such a way as to make them operate properly when they are part of a sequential circuit that employs a common clock The problem with the latch is that it responds to a change in the level of a clock pulse. For proper operation of a fip-flop it should be triggered only during a signal transition. This can be accomplished by eliminating the feedback path that is inherent in the operation of the sequential circuit from 1 to 0. using latches. A clock pulse goes through two transitions: from 0 to 1 and the return Aways that a latch can be modified to form a flip-flop is to produce a flip-flop that triggers only during a signal transition (from 0 to 4 oF from 4 to 0) of the synchronizing signal (clock) and is disabled during the rest of the clock pulse. et J) LL ()Posive edge rape NLL. ()Nepaie ape ropee \P: The JK flip-flop can be constructed by using basic SR latch and a clock. In this case the outputs Q and Q’ are returned back and connected to the inputs of NAND gates. This simple JK flip Flop is the most widely used of all the flip-flop designs and is considered to be a universal flip-flop circuit. The sequential operation of the JK flip flop is exactly the same as for the previous SR flip-flop with the ‘same “Set” and “Reset” inpu! ts. The difference this time is that the “JK flip flop” has no invalid or forbidden input states of the SR Latch even when S and R are both at logic “1”, (The below diagram shows the circuit diagram of a JK flip-flop) J CLK — i> [> K <> Q ;-Q The JK flip lop is basically a gated SR Flip-flop with the addition of a clock input circuitry that prevents the illegal or invalid output condition that can occur when both inputs S and R are equal to logic level 1" Due to this additional clocked input, a JK flip-flop has four possible input combinations, “logic 1”, “logic 0°, “no change” and “toggle”.The symbol for a JK flip flop is similar to that of an SR bistable latch except the clock input. (The above diagram shows the symbol of a JK flip-flop.) Both the S and the R inputs of the SR bi-stable have now been replaced by two inputs called the J and K inputs, respectively after its inventor Jack and Kilby. Then this equates to: J = S and K= R. The two 2-input NAND gates of the gated SR bi-stable have now been replaced by two 3-input NAND gates with the third input of each gate connected to the outputs at Q and Q’. This cross coupling of the SR flip-lop allows the previously invalid condition of S = "1" and R to be used to produce a “toggle action” as the two inputs are now interlocked Ifthe circuit is now “SET” the J input is inhibited by the “0” status of Q’ through the lower NAND gate. If the circuit is “RESET” the K input is inhibited by the “0” stalus of Q through the upper NAND gate. As Q and Q’ are always different we can use them to control the input. 1" state (Truth table for JK ip-flop) Output ‘Comment a No change Reset Set Toggle When both inputs J and K are equal to logic "1", the JK flip flop toggles. FLO! Toggle fip-flop or commonly known as T flip-flop, This flip-flop has the similar operation as that of the JK flip-flop with both the inputs J and K are shorted ie. both are given the common input. it Hence its truth table is same as that of JK flip-flop when J=K= 0 and J=K=1.So its truth table is as follows.T a Gren ‘Comment 0 0 0 No change 1 1 7 0 1 Toggles 1 0 CHARACTERISTIC TABLE:- A characteristic table defines the logical properties of a flip-flop by describing its operation in tabular form. The next state is defined as a function of the inputs and the present state. Q ( refers to the present state and Q (1 + 1) is the next. Thus, Q (t) denotes the state of the flip-flop immediately before the clock edge, and Qi + 1) denotes the slate that results from the clock transition. ‘The characteristic table for the JK flip-flop shows that the next state is equal to the present state when inputs J and K are both equal to 0. This condition can be expressed as Q (t + 1) = Q (0, indicating that the clock produces no change of state. Characteristic Table Of JK Flip-Flop J K atte) 0 0 Qi) No change 0 7 0 Reset 7 0 1 ‘Set 7 7 Q() Complement ‘When K = 4 and J = 0, the clock resets the flip-flop and Q(t + 1) = 0. With J = 1 and K = 0, the flip-flop sets and Q(t + 1) = 1. When both J and K are equal to 1, the next state changes to the complement of the present state, a transition that can be expressed as Q(t + 1) = Q°() The characteristic equation for JK flip-flop is represented as Qt+1)= JO'+ K'Q. Characteristic Table of D Flip-Flop D Q(t+1) 0 0 7 1 The next state of a D flip-flop is dependent only on the D input and is independent of the present slate. This can be expressed as Q ({ + 1) = D. It means that the next-state value is equal to the value of D. Note that the D flip-flop does not have a “no-change” condition and its characteristic equation is written as Q(t+1)=D. Characteristic Table of T Flip-Flop T Qty 0 Q()_No change 7 Q'W)_Complement* The characteristic table of T flip-flop has only two conditions: When T = 0, the clock edge does not change the state; when T = 1, the clock edge complements the state of the flip-flop and the characteristic equation is Q(t+1)=T ®Q=TQ4TQ' + The Master-Slave Flip-Flop is basically two gated SR flip-flops connected together in a series configuration with the slave having an inverted clock pulse. ‘+ The outputs from Q and Q' from the “Slave” flip-flop are fed back to the inputs of the “Master” with the outputs of the “Master” flip flop being connected to the two inputs of the “Slave” flip flop. ‘* This feedback configuration from the slave's output to the master’s input gives the characteristic toggle of the JK flip flop as shown below. ‘The Master-Slave JK Flip Flop Master | Slave Flip-flop | Flip-flop ‘+ The input signals J and K are connected to the galed “master” SR flip flop which “locks” the input condition while the clock (Cik) input is “HIGH! at logic level + As the clock input of the “slave” flip flop is the inverse (complement) of the “master” clock input, the “slave” SR flip flop does not toggle. ‘+ The outputs from the “master” flip lop are only “seen” by the gated “slave" flip flop when the clock input goes “LOW’ to logic level “0°. When the clock is “LOW”, the outputs from the “master” flip flop are latched and any additional changes to its inputs are ignored ‘+ The gated "slave" flip flop now responds to the stale of its inputs passed over by the “master” section. + Then on the “Low-to-High" transition of the clock pulse the inputs of the “master” fip flop are fed through to the gated inputs of the “slave" flip flop and on the “High-to-Low’ transition the same inputs are reflected on the output of the “slave” making this type of flip flop edge or pulse-triggered. ‘+ Then, the circuit accepts input data when the clock signal is "HIGH", and passes the data to the output on the falling-edge of the clock signal. + Inother words, the Master-Slave JK Flip flop is a “Synchronous” device as it only passes data with the timing of the clock signal FLIP-FLOP CONVERSIONS:. Flip Flop to JK Flip Flo, For this J and K will be given as external inputs to S and R. As shown in the logic diagram below, S and R will be the outputs of the combinational circuit.‘The truth tables for the flip flop conversion are given below. The present state is represented by Qp and Qp+1 is the next state to be obtained when the J and K inputs are applied. For two inputs J and K, there will be eight possible combinations. For each combination of J, K and Qp, the corresponding Qp+4 states are found. Qp+1 simply suggests the future values to be obtained by the JK flip flop after the value of Qp. The table is then completed by writing the values of S and R required to get each Qp+1 from the corresponding Qp. That is, the values of S and R thal are required to change the state of the flip flop from Qp to Op+1 are written. S-R Flip Flop to 3-K Flip Flop Conversion abe Logi Bagram Tas . 2 fo 0 |e ofa os alo | Te che JK Flip Flop to SR Flip Flop ‘+ This will be the reverse process of the above explained conversion. S and R will be the external inputs to J and K. J and K will be the outputs of the combinational circuit. Thus, the values of J and K have to be obtained in terms of S, R and Qp. + Aconversion table is to be written using S, R, Qp, Qp+4, J and K. ‘+ For two inputs, S and R, eight combinations are made. For each combination, the corresponding Qp+1 ‘outputs are found out. ‘+ The outputs for the combinations of S=1 and Re1 are not permitted for an SR flip flop. Thus the outputs are considered invalid and the J and K values are taken as “don't cares”.Conversion able 2:K Flip Flop to S-R Flip Flop, 2 tute tone Dapeam SR Flip Flop to D Flip Flop «Sand R are the actual inputs of the flip flop and D is the external input of the flip flop. «The four combinations, the logic diagram, conversion table, and the K-map for $ and R in terms of D and Qp are shown below. S-R Flip Flop to D Flip Flop Conversion Table ‘+ Dis the actual input of the flip flop and S and R are the external inputs. Eight possible combinations are achieved from the extemal inputs S, R and Qp. ‘But, since the combination of S=1 and R=1 are invalid, the values of Qp+1 and D are considered as “don't cares”, ‘+ The logic diagram showing the conversion from D to SR, and the K-map for D in terms of S, Rand Qp are shown below.D Flip Flop to S-R Flip Flop Conversion Table Logie Diagram | 7 a b= sin IK Flip Flop to T Flip Flop: * Jand K are the actual inputs of the fip flop and T is taken as the external input for conversion Four combinations are produced with T and Qp. J and K are expressed in terms of T and Qp. ‘+ The conversion table, K-maps, and the logic diagram are given below. 14 FlipFlop tT Fp Flop 2 Ls gL D Flip Flop to JK Flip Flop: In this conversion, D is the actual input to the flip flop and J and K are the external inputs. J, K and Qp make eight possible combinations, as shown in the conversion table below. D is expressed in terms of J, K and Qp. The conversion table, the K-map for D in terms of J, K and Qp and the logic diagram showing the conversion from D to JK are given in the figure below.D Flip Flop to J-K Flip Flop Conversion Table remap Lone Diagram * Dis the external input and J and K are the actual inputs of the flip flop. D and Qp make four combinations. J and K are expressed in terms of D and Qp. * The four combination conversion table, the K-maps for J and K in terms of D and Qp. °K Flip Flop to D Flip Flop Conversion Table Logie Dageam @L— I