Digital Logic Design Lab

(EE-123L) Lab Report # 09

Group No. ____

Submitted by:
Name: Reg No: Name: Reg No: Name:
Reg No: Name: Reg No:

Submitted to:

Engr. Awais Mehmood

Department of Computer Science (BS-CS)

Air University Aerospace and Aviation
Campus Kamra
AIR UNIVERSITY, AEROSPACE
& AVIATION CAMPUS KAMRA
DEPARTMENT OF COMPUTER SCIENCE

DIGITAL LOGIC DESIGN LAB (EE-123L)

LAB NO # 09

LAB TITLE: Introduction and Implementation of Memory unitsLAB

ASSESSMENT:

Student Names (CLO-1,GA-4, P2) (CLO-2, GA-6, P3) Total

Marks
(20)

Ability to use IT Ability Ability Individual and Obtained

Trainer and to to group participation Marks
results conduc investig
demonstration t ate the (05)
(05) experim results
ent (05) (05)

LAB REPORT ASSESSMENT:

ASSESSMENT OF (CLO-3, GA-7, A2)

Performance Indicator Excellent Good Average Unsatisfactory

5 3-4 1-2 0

Experimental Results

Data Presentation

Total Marks: ______________ Obtained Marks: ______________

Instructor’s Signature: _________

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Introduction and Implementation of Memory units
(Latches and Flip Flops)
OBJECTIVE
∙ To understand how binary data is stored using memory elements ∙
To learn about the basic building blocks of storage devices
∙ To distinguish between latches and flip-flops
∙ Sequential circuits (Latch & Flip Flops) Implementation on an IT trainer
THEORY
What are Sequential circuits?
Sequential circuit consists of combinational logic circuit to which memory elements
are connected to form a feedback path.

Figure 1. Sequential Circuit

Types of storage elements:

Figure 2. Memory Elements

1. Latch
A latch is an electronic device that changes its output immediately on the basis of the
applied input. One can use it to store either 0 or 1 at a specified time. A latch contains two
̅
inputs- SET and RESET, and it also has two outputs (Q and �� ).

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They complement each other. One can use a latch for storing one bit of data. It is a level
triggered memory device, means it stores data whenever the level of the input gets
changed. Circuit Diagram & Characteristic Table
 Figure 3. SR Latch based on NOR Gate with characteristic table

Figure 4. SR Latch based on NAND Gate with characteristic table

Figure 5: 2 Input QUAD NAND Gate SN74LS00 Figure 6:

2 Input QUAD NOR Gate SN74LS02 PROCEDURE
∙ SR Latch NOR Gate:
1. Implement the SR Latch based on NOR Gate on breadboard, the circuit diagram is
given in Figure 1.
2. Connect the two data lines from input of the trainer to the NOR Gate inputs. There are
4 NOR Gates available in SN74LS02, utilizing only two NOR gates from the IC. 3.
Connect the first input data lines to pin 2 and pin 5 of NOR Gate (SN74LS02). 4. The
output of first NOR Gate pin 1 will then be connected to the pin 6 (2nd input of the 2nd
NOR Gate).
5. The output of 2nd NOR Gate pin 4 will then be connected to the pin 3 (2nd input of the
1st NOR Gate).
6. Connect the pin 1 and pin 4 of NOR Gate to the LEDs. Now, implement the following
cases for the implemented latch given below Set (S) and Reset (R).
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Case 1: R = 1 and S = 0
In this case, the ‘R’ input is 1, which means the output of the NOR Gate A will become 0
i.e., Q is 0 (LOW). As a result, both the inputs of NOR Gate B become 0 and hence the
output of the NOR Gate B is 1 (HIGH). As ‘1’ at input R makes the output to switch to
one of its stable states and resets it to ‘0’, the R input is known as RESET input.

Case 2: R = 0 and S = 0
In the first case, the inputs of both the NOR gates are Logic ‘0’. As neither of them are
dominating inputs, they have no effect on the output. So, the output retains their previous
states i.e., there is no change in the output. This condition is called as Hold Condition or
No Change Condition.

Case 3: R = 0 and S = 1
In this case, the ‘S’ input is 1, which means the output of the NOR Gate B will become 0.
As a result, both the inputs of NOR Gate A become 0 and hence the output of the NOR
Gate A and thus the value of Q is 1 (HIGH). As ‘1’ at input S makes the output to switch
to one of its stable states and sets it to ‘1’, the S input is known as SET input.

Case 4: R = 1 and S = 1
This input condition is forbidden as it forces outputs of both NOR Gates to become 0,
which is a violation of complementary outputs. Even if this input condition is applied, if
the next inputs become R = 0 and S = 0 (hold condition), then it causes a ‘race condition’
between the NOR Gates, which causes an unstable or unpredictable state at the output.
Hence, the input condition R = 1 and S = 1 is simply not used.
∙ SR Latch NAND Gate:
1. Implement the SR Latch based on NAND Gate on breadboard, the circuit diagram is
given in Figure 2.
2. Connect the two data lines from input of the trainer to the NAND Gate inputs. There
are 4 NAND Gates available in SN74LS00, utilizing only two NAND gates from the
IC.
3. Connect the input data lines to pin 1 and pin 4 of NAND Gate (SN74LS00). 4. The
output of 1st NAND Gate pin 3 will then be connected to pin 5 (2nd input of the 2nd
NAND Gate).
5. The output of 2nd NAND Gate pin 6 will then be connected to pin 2 (2nd input of the 1st
NAND Gate).
6. Connect the pin 3 and pin 6 of NAND Gate to the LEDs. Now, implement the
following cases for the implemented latch given below Set (S) and Reset (R).

Case 1: S = 0 and R = 1
When R input is HIGH and S input is LOW, Latch will be in Reset state. As R is HIGH,
the output of NAND gate B i.e., Q’ becomes LOW. This causes both the inputs of NAND
gate A to become LOW and hence, the output of NAND gate A i.e., Q becomes HIGH.

Case 2: S = 1 and R = 1
When both the S and R inputs are HIGH, the output remains in previous state i.e., it holds
the previous data.
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Case 3: S = 1 and R = 0
When R input is LOW and S input is HIGH, the Latch will be in SET state. As S is HIGH,
the output of NAND gate A i.e., Q becomes LOW. This causes both the inputs of NAND
gate B to become LOW and hence, the output of NAND gate A i.e., Q becomes Low.

Case 4: R = 0 and S = 0
When both the R and S inputs are LOW, the Latch will be in undefined state. Because the
low inputs of S and R, violates the rule of Latch that the outputs should complement to
each other. So, the Latch is in undefined state (or forbidden state).

2. Flip Flop
A flip-flop is a digital memory circuit that stores one bit of data. They are the primary
blocks of the most sequential circuits. It is also called one-bit memory, binary, or a
bistable multivibrators. Flip-flops act as memory elements in a sequential circuit. You can
obtain the output in the sequential circuits using a flip-flop, a combinational circuit, or
both.
It is an edge triggered storage device, stores data whenever the edge the clock pulse edge
is detected. It is a synchronous device which needs some kind of timing pulse to store data
while Latch doesn’t depend on clock pulse.
Either the latch or flip flop both has 2 outputs which are complement of each other.
̅
Consider The output Q the other output will be ��.

2.1. RS Flip Flop

RS Flip-flop (or Reset – set flip-flop) is the simplest of all flip-flops. This basic type of
flip-flop is also called direct – coupled flip-flop or a latched flip-flop. Remember that as a
flip-flop has two possible stable states (precisely analogous to a toggle switch which can
either turn ON or OFF) and remains on its stable state or hold its one particular state until
its input changes and as such, forcefully changes its hold position. This holding feature is
known as a latch, due to which a RS flip-flop is also known as a latch flip-flop.

Figure 7: SR Flip flop in terms of NAND and Nor gates

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Truth Table

Figure 8. SR flip flop truth table

2.2 D Flip-Flop
One of the main disadvantages of the basic SR NAND Gate Bistable circuit is that the
indeterminate input condition of SET = “0” and RESET = “0” is forbidden while SR
NOR Gate Bistable circuit has indeterminate input condition SET = “1” and RESET =
“1” is forbidden.
The D Flip Flop is by far the most important of all the clocked flip-flops. By adding an
inverter (NOT gate) between the Set and Reset inputs, the S and R inputs become
complements of each other ensuring that the two inputs S and R are never equal (0 or 1) to
each other at the same time allowing us to control the toggle action of the flip-flop using
one single D (Data) input.
Thus, this single input is called the “DATA” input. If this data input is held HIGH the flip
flop would be “SET” and when it is LOW the flip flop would change and become
“RESET”. However, this would be rather pointless since the output of the flip flop would
always change on every pulse applied to this data input.
To avoid this an additional input called the “CLOCK” or “ENABLE” input is used to
isolate the data input from the flip flop’s latching circuitry after the desired data has been
stored. The effect is that D input condition is only copied to the output Q when the clock
input is
active. This then forms the basis of another sequential device called a D Flip
Flop. Circuit Diagram
 Figure 9. D Flip flop
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Characteristic Table

Note that: ↓ and ↑ indicates direction of clock pulse as it is assumed D-type flip flops are
edge triggered.
Pin-Out Configuration

Figure 7. D Flip Flop pin-out Configuration

PROCEDURE
1. Implement the Flip Flop, there are 2 D Flip-Flops available in IC 74LS74 Gate on
breadboard, the circuit diagram is shown above in Figure 5.
2. Utilizing any one Data Flip Flop from 74LS74, connect single data line as input to pin
2 of IC.
3. Provide the Clock signal to the pin 3 as clock pulse CLK, it acts as an enable pin for
the flip flop to work.
4. There are two pins PR (Preset) at pin 4 and CLR (Clear) at pin 1, PR which sets the
output while CLR clear the output or reset the IC even if input is applied. 5. Connect the
output pin 5 and its complement pin 6 to the LEDs.
6. Now, apply the different states of input from data line at pin 2 and see the output.
Truth Table:
̅̅ ̅̅
̅ CLK D Q Function
����̅ ����� ��̅
�̅
0 1 x x 1 0 D- flip flop
Manual
1 0 x x 0 1
Override

1 1 1 1 0 D Flip flop
Normal
1 1 0 0 1 Functionality
1 1 0 x Memory State

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LAB TASKS

Task 1:

Implement the sequential circuits mentioned below using only NAND gates (7400 IC) on
a breadboard, utilizing the IT Trainer for input and output connections.

1. SR Latch circuit
2. SR Flip-Flop circuit
3. D Flip-Flop circuit

Task 2:

Implement the D flip-flop logic on a breadboard using the 74LS74 IC. Use the IT Trainer
for inputs and outputs, and compare the results with Task 1 (Part 3).
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