Computer Organization and Architecture

Module-2

Sequential circuit

The sequential circuit is a special type of circuit that has a series of inputs and outputs. The
outputs of the sequential circuits depend on both the combination of present inputs and previous
outputs. The previous output is treated as the present state. So, the sequential circuit contains
the combinational circuit and its memory storage elements. A sequential circuit doesn't need to
always contain a combinational circuit. So, the sequential circuit can contain only the memory
element.

Block diagram

Combinational Circuits Sequential Circuits

1) The outputs of the The outputs of the sequential circuits

combinational circuit depend depend on both present inputs and
only on the present inputs. present state(previous output).

2) The feedback path is not The feedback path is present in the

present in the combinational sequential circuits.
circuit.

3) In combinational circuits, In the sequential circuit, memory

memory elements are not elements play an important role and
required. require.

4) The clock signal is not required The clock signal is required for
 for combinational circuits. sequential circuits.

5) The combinational circuit is It is not simple to design a sequential

simple to design. circuit.

Difference between the combinational circuits and sequential circuits are

given below:

Clock signal
A clock is a signal that oscillates between a high and a low state. It is used to coordinate the
actions of a digital circuit (like a metronome).

A clock signal

Types of Triggering
These are two types of triggering in sequential circuits:

Level triggering (Pulse triggering)

The logic High and logic Low are the two levels in the clock signal. In level
triggering, when the clock pulse is at a particular level, only then the circuit
is activated. There are the following types of level triggering:

Positive level triggering

In a positive level triggering, the signal with Logic High occurs. So, in this
triggering, the circuit is operated with such type of clock signal. Below is
the diagram of positive level triggering:
Negative level triggering
In negative level triggering, the signal with Logic Low occurs. So, in this triggering, the
circuit is operated with such type of clock signal. Below is the diagram of Negative level
triggering:

Edge triggering
In clock signal of edge triggering, two types of transitions occur, i.e., transition
either from Logic Low to Logic High or Logic High to Logic Low.

Based on the transitions of the clock signal, there are the following types of
edge triggering:

Positive edge triggering

The transition from Logic Low to Logic High occurs in the clock signal of
positive edge triggering. So, in positive edge triggering, the circuit is
operated with such type of clock signal. The diagram of positive edge
triggering is given below.
Negative edge triggering
The transition from Logic High to Logic low occurs in the clock signal of
negative edge triggering. So, in negative edge triggering, the circuit is
operated with such type of clock signal. The diagram of negative edge
triggering is given below.

Latches

A Latch is a special type of logical circuit. The latches have low and high two stable states.
Due to these states, latches also refer to as bistable-multivibrators. A latch is a storage device
that holds the data using the feedback lane. The latch stores 1 -bit until the device set to 1. The
latch changes the stored data and constantly trials the inputs when the enable input set to 1.

Based on the enable signal, the circuit works in two states. When the enable input is high, then
both the inputs are low, and when the enable input is low, both the inputs are high.

SR Latch

The SR latch is a special type of asynchronous device which works separately for control
signals. It depends on the S-states and R-inputs. The SR latch design by connecting
two NOR gates with a cross loop connection. The SR latch can also be designed using
the NAND gate.

A latch is a temporary storage element that has two stable states (bistable). They operate in
signal levels rather than signal transitions. An active-HIGH input SR latch is formed with two
cross-coupled NOR gates and an active-LOW input S’-R’ latch is formed with two cross-
coupled NAND gate.

An SR Latch with two cross-coupled NOR gate is shown in the figure. It has two input S for
SET and R for RESET and two outputs Q and Q’
SR latch using NOR gate.

Working of an SR Latch

When S=1 the output of G2 will be 0 (the output of a NOR gate is 0 when any of its input are
1). Since this output is connected back to an input of G1, and the R input is also 0, the
output of G1 must be 1. This output 1 is coupled back to an input of G2, making its
output remain 1 even when the 1 on the S input is removed(Memory State). When the Q
output is HIGH, the latch is said to be in the SET state.

S=1, R=0 then Q=1 & Q’=0

SET operation of SR Latch

When R=1 and S=0, the output of G1 becomes 0. This 0 on the Q output is coupled back to
an input of G2, and since the S input is 0, the output of G2 becomes 1. This 1on Q’output is
then coupled back to an input of G1, making the output Q remains 0 even when the 1 on the
R input is removed (Memory State). We can now say that the latch is in the RESET state.

S=0, R=1 then Q=0& Q’=1

RESET operation of SR Latch

When 1s are applied to both S and R at the same time, an invalid condition occurs in the
operation of an SR latch. As long as the 1s are held simultaneously on the inputs, both
the Q and Q’ outputs are forced to become 0. It will violate the basic complementary
operation of the outputs. Also, if the 1s are released simultaneously, both outputs will attempt
to go 1. In this situation, you cannot reliably predict the next state of the latch.

This operation is summarized in the following truth table.

INPUTS OUTPUTS
STATE
S R Q Q’

0 0 NC NC Memory State

0 1 0 1 RESET

1 0 1 0 SET

1 1 – – Not Used.

SR Latch using NAND gate

An SR latch can be also constructed by cross-coupling two NAND gates as shown in the
figure.
SR latch using NAND gate

The operation is described in the following truth table.

INPUTS OUTPUTS
STATE
S R Q Q’

1 1 NC NC Memory State

0 1 1 0 SET

1 0 0 1 RESET

0 0 – – Not Used

SR Flip Flop

The SR flip flop is a 1-bit memory bistable device having two inputs, i.e., SET and RESET.
The SET input 'S' set the device or produce the output 1, and the RESET input 'R' reset the
device or produce the output 0. The SET and RESET inputs are labeled as S and R,
respectively.

The SR flip flop stands for "Set-Reset" flip flop. The reset input is used to get back the flip flop
to its original state from the current state with an output 'Q'. This output depends on the set and
reset conditions, which is either at the logic level "0" or "1".

The NAND gate SR flip flop is a basic flip flop which provides feedback from both of its
outputs back to its opposing input. This circuit is used to store the single data bit in the memory
circuit. So, the SR flip flop has a total of three inputs, i.e., 'S' and 'R', and current output 'Q'.
This output 'Q' is related to the current history or state. The term "flip-flop" relates to the
actual operation of the device, as it can be "flipped" to a logic set state or "flopped" back to the
opposing logic reset state.

Block Diagram of SR flip flop

CLK S R Q Q’ State
0 X X No change No change Memory
1 0 0 No change No change Memory
1 0 1 0 1 Reset
1 1 0 1 0 Set
1 1 1 X X Undefined

Actual Truth table

JK Flip Flop

The SR Flip Flop or Set-Reset flip flop has lots of advantages. But, it has the following
switching problems:

o When Set 'S' and Reset 'R' inputs are set to 0, this condition is always avoided.
o When the Set or Reset input changes their state while the enable input is 1, the incorrect latching
action occurs.
The JK Flip Flop removes these two drawbacks of SR Flip Flop.

The JK flip flop is one of the most used flip flops in digital circuits. The JK flip flop is a
universal flip flop having two inputs 'J' and 'K'. In SR flip flop, the 'S' and 'R' are the shortened
abbreviated letters for Set and Reset, but J and K are not. The J and K are themselves
autonomous letters which are chosen to distinguish the flip flop design from other types.

The JK flip flop work in the same way as the SR flip flop work. The JK flip flop has 'J' and 'K'
flip flop instead of 'S' and 'R'. The only difference between JK flip flop and SR flip flop is that
when both inputs of SR flip flop is set to 1, the circuit produces the invalid states as outputs,
but in case of JK flip flop, there are no invalid states even if both 'J' and 'K' flip flops are set to
1.

Block Diagram:

Circuit Diagram:
In SR flip flop, both the inputs 'S' and 'R' are replaced by two inputs J and K. It means the J
and K input equates to S and R, respectively.

The two 2-input AND gates are replaced by two 3-input NAND gates. The third input of each
gate is connected to the outputs at Q and Q'. The cross-coupling of the SR flip-flop permits the
previous invalid condition of (S = "1", R = "1") to be used to produce the "toggle action" as the
two inputs are now interlocked.

If the circuit is "set", the J input is interrupted from the "0" position of Q' through the lower
NAND gate. If the circuit is "RESET", K input is interrupted from 0 positions of Q through the
upper NAND gate. Since Q and Q' are always different, we can use them to control the input.
When both inputs 'J' and 'K' are set to 1, the JK toggles the flip flop as per the given truth table.

CLK J K Q Q’ State
0 X X No change No change Memory
1 0 0 No change No change Memory
1 0 1 0 1 Reset
1 1 0 1 0 Set
1 1 1 T T Toggle
condition

Actual Truth table of JK flip flop

CLK J K Qn+1 State

0 X X No change Memory
1 0 0 No change Memory
1 0 1 1 Reset
1 1 0 0 Set
1 1 1 T Toggle
condition

D Flip Flop

In SR NAND Gate Bistable circuit, the undefined input condition of SET = "0" and RESET
= "0" is forbidden. It is the drawback of the SR flip flop. This state:

1. Override the feedback latching action.

2. Force both outputs to be 1.
3. Lose the control by the input, which first goes to 1, and the other input remains "0" by
which the resulting state of the latch is controlled.

We need an inverter to prevent this from happening. We connect the inverter between the Set
and Reset inputs for producing another type of flip flop circuit called D flip flop, Delay flip
flop, D-type Bistable, D-type flip flop.
The D flip flop is the most important flip flop from other clocked types. It ensures that at the
same time, both the inputs, i.e., S and R, are never equal to 1. The Delay flip-flop is designed
using a gated SR flip-flop with an inverter connected between the inputs allowing for a single
input D(Data).

This single data input, which is labeled as "D" used in place of the "Set" input and for the
complementary "Reset" input, the inverter is used. Thus, the level-sensitive D-type or D flip
flop is constructed from a level-sensitive SR flip flop.

So, here S=D and R= ~D(complement of D)

Block Diagram

Circuit Diagram

Or
We know that the SR flip-flop requires two inputs, i.e., one to "SET" the output and another to
"RESET" the output. By using an inverter, we can set and reset the outputs with only one input
as now the two input signals complement each other. In SR flip flop, when both the inputs are
0, that state is no longer possible. It is an ambiguity that is removed by the complement in D-
flip flop.

In D flip flop, the single input "D" is referred to as the "Data" input. When the data input is set
to 1, the flip flop would be set, and when it is set to 0, the flip flop would change and become
reset. However, this would be pointless since the output of the flip flop would always change
on every pulse applied to this data input.

The "CLOCK" or "ENABLE" input is used to avoid this for isolating the data input from the
flip flop's latching circuitry. When the clock input is set to true, the D input condition is only
copied to the output Q. This forms the basis of another sequential device referred to as D Flip
Flop.

When the clock input is set to 1, the "set" and "reset" inputs of the flip-flop are both set to 1.
So it will not change the state and store the data present on its output before the clock transition
occurred. In simple words, the output is "latched" at either 0 or 1.

Truth Table for the D-type Flip Flop

Symbols ↓ and ↑ indicates the direction of the clock pulse. D-type flip flop assumed these
symbols as edge-triggers.
Actual Truth Table of D flip flop
CLK D Qn+1 State
0 X Qn Memory
1 0 0 Reset
1 1 1 Set

T Flip Flop

In T flip flop, "T" defines the term "Toggle". In SR Flip Flop we provide only a single input
called "Toggle" or "Trigger" input to avoid an intermediate state occurrence. Now, this flip-
flop work as a Toggle switch. The next output state is changed with the complement of the
present state output. This process is known as "Toggling"'.

We can construct the "T Flip Flop" by making changes in the "JK Flip Flop". The "T Flip Flop"
has only one input, which is constructed by connecting the input of JK flip flop.

This single input is called T. In simple words, we can construct the "T Flip Flop" by converting
a "JK Flip Flop". Sometimes the "T Flip Flop" is referred to as single input "JK Flip Flop".

Block diagram of the "T-Flip Flop" is given where T defines the "Toggle input", and CLK
defines the clock signal input.

T Flip Flop Circuit

The simplest construction of a D Flip Flop is with JK Flip Flop. Both the inputs of the "JK Flip
Flop" are connected as a single input T. Below is the logical circuit of the T Flip Flop" which
is formed from the "JK Flip Flop":
The block diagram of "T Flip Flop" using "JK Flip Flop" is given below:

Truth table for T flip flop

CLK T Q Q’ State
0 X No change No change Memory
1 0 No change No change Memory
1 1 T T Toggle

Actual Truth table of T flip flop

CLK T Qn+1 State

0 X Qn Memory
1 0 Qn Memory
1 1 Q’n Toggle
Master-Slave JK Flip Flop

In "JK Flip Flop", when both the inputs and CLK set to 1 for a long time, then Q output toggle
until the CLK is 1. Thus, the uncertain or unreliable output produces. This problem is referred
to as a race-round condition in JK flip-flop and avoided by ensuring that the CLK set to 1 only
for a very short time.

Explanation

The master-slave flip flop is constructed by combining two JK flip flops. These flip flops are
connected in a series configuration. In these two flip flops, the 1st flip flop work as "master",
called the master flip flop, and the 2nd work as a "slave", called slave flip flop. The master-
slave flip flop is designed in such a way that the output of the "master" flip flop is passed to
both the inputs of the "slave" flip flop. The output of the "slave" flip flop is passed to inputs of
the master flip flop.

In "master-slave flip flop", apart from these two flip flops, an inverter or NOT gate is also used.
For passing the inverted clock pulse to the "slave" flip flop, the inverter is connected to the
clock's

Race Around Condition In JK Flip-flop – For J-K flip-flop, if J=K=1, and if clk=1 for a
long period of time, then Q output will toggle as long as CLK is high, which makes the output
of the flip-flop unstable or uncertain. This problem is called race around condition in J-K
flip-flop. This problem (Race Around Condition) can be avoided by ensuring that the clock
input is at logic “1” only for a very short time. This introduced the concept of Master Slave
JK flip flop.

Master Slave JK flip flop –

The Master-Slave Flip-Flop is basically a combination of two JK flip-flops connected

together in a series configuration. Out of these, one acts as the “master” and the other as
a “slave”. The output from the master flip flop is connected to the two inputs of the slave
flip flop whose output is fed back to inputs of the master flip flop.
In addition to these two flip-flops, the circuit also includes an inverter. The inverter is
connected to clock pulse in such a way that the inverted clock pulse is given to the slave flip-
flop. In other words if CP=0 for a master flip-flop, then CP=1 for a slave flip-flop and if
CP=1 for master flip flop then it becomes 0 for slave flip flop.
Block diagram of master slave JK flip flop

Working of a master slave flip flop –

1. When the clock pulse goes to 1, the slave is isolated; J and K inputs may affect the state
of the system. The slave flip-flop is isolated until the CP goes to 0. When the CP goes
back to 0, information is passed from the master flip-flop to the slave and output is
obtained.
2. Firstly the master flip flop is positive level triggered and the slave flip flop is negative
level triggered, so the master responds before the slave.
3. If J=0 and K=1, the high Q’ output of the master goes to the K input of the slave and the
clock forces the slave to reset, thus the slave copies the master.
4. If J=1 and K=0, the high Q output of the master goes to the J input of the slave and the
Negative transition of the clock sets the slave, copying the master.
5. If J=1 and K=1, it toggles on the positive transition of the clock and thus the slave toggles
on the negative transition of the clock.
6. If J=0 and K=0, the flip flop is disabled and Q remains unchanged.