>4y LT ask onithmetic. right Shift —xASRY Cgigned) am >> -TRoR qgotate Bigot xRORY [Lwnsigned) 94) tw < Explain Ss => ly processes singtervc tions §— aye eureol 0 extend the PE eUSemeC COC sOT CAO either provide addons! computation capability os be wid tp contro athe memory, supsystem Sinetucling esches and memory management * The co-processoy Sastru eto “include — < Date PYOCeKIng ° * Regcte Tervafer + Memoty Treusfer Instavcbows: Syntax 1! 4 EDP Ft eh, Opeoded, Cd, en Fo opcot?} | emec J Mer> feond> } eb, eptodet , Rd, en, 6m J, ope fcond >} Cp | ce, edtdaening ' oo, | CDP — COprocessor date procedsingy = pevform ano feo '9 n oper MRE MCR coprocessey veoister opr CEMehs hs tepistey trmsfer = mye dam Ryn ¥" ene ste - coptoceu 27 EMONY FIMSey — fond ami core DIT( plain with exomples the follovoing 32-bit (_[rostewetion of ARM processow — | a pon MN owen. compagison natroction which, gd fg Uscl +0 COM prt value with negative 3. | ng tneyse | | CMIN Stan for compsze Negative « LH; niax- oMN €Rn> , -o andl Accumvbte Tn a Single tattivction eyckhi> MRS— CMove Register from Status veg iste ) eee ; MRG\epeds foo: move to ARM RBIStE trom y Status Register: DB is wreol +o copy the stontents of a Psogzam Status Regisrey © Grae ot spsk) into % genet! bexpo CeFistey. > MRS ,cpsR mes oes S ese ED Rs eo, cece 5 copy cPse into Ro x ancl CP SR HAH vQ@aeET mode fees a 6 100l! ~ Move fis 32-bit CPSR UslLe Ino Lo, | cteay CAND NoT J of tio © bet with +eLoad Registers grands fo D + qs used te toad a Single valve fiat In_ memory © som Vittval eT Rol [Rnd ror Ra, [Ra Offset J ide Rd, evalue #021000 tdR Ri , CRO memoty. at 0xI000 has valve onde) O ADEADBEEF pgeer) proach With Adty« d and_fiom the Se tood and stores the Faults + avin STRH — SS STRH Stn -for Dt storey fre Lowes mamory * gtote Registet Halfword iv) pits (ha Poort J BF aeFIsts i, ntax— sry ed, [en] Sten ea, [en , Hoffset] STRH Re [Ra] , Hoffset Moy RO, HOKI23+ LDR RE, = O%200000000 STRH Ro CRI] Wi! Store - loses [6 bi Of Ro (9% 1234) -fo AAA? Ox 20000000. Swab seyister cvoith memory » ) Oo wepister Wales with & word inDate... Page No. ..3 jain single Bogie te¥ {oad Baie adldtsexsing mode jax, table, indlex Mode with an example: ~ Regishet Nnsttuctions cise reel for moving = §{ 4 QBy Ra | addressing? J 4 LDR }dtond>} $B HSH Rd, addvering® BTR Jetond> TH, Wd addvesing® } | [PIR > toad word hcto a register | Rdc—mensafaciren STR > Save byte ox word fiom svegictey | Rd ~> menPLedeleeni] load byte into _o tepister Rd & megng [acitaen] gel —pmem’ [acids] Save byfe fam 9 tegister Ra & Sin Extend} Cinem 8 hadeews Rd € SignExtend: Rd — mem I aes Rd > mem l6Lacld ters ]7 Index Methods — ee Se Base Ares | Gacler Methra | peta Registes | *°MPle ae = J | MPeeindex with weitebret| mern[ be | base toffset [LOR vo,[7, Hy + offset] ; NS Pac iqclex em[wetoffarl] oot updated /LOR xo Pr ind Post inden mere[ base] jbase +offct \UPRoo,[n] 4, Ss Pre inder with wr'itebsck calevrliotes an adore ftom 9 base register ples acldTOM offset And -then updoctes ~tnat ocldlvets brite weqistey with a new addacn- ti) The preindex Offsef Is the same as the pre index | with ursitebsck bet does Not update the oldies bare BOPSHT* we >festindex only updater ne aclerem bare tcqister after address is ete > a ep) PRE 40 , [ec] t#4 Cd) 0 = 0x 00000000 an pal aad 41 = 0X 0009 H000 as | mem32['7% 00090008] = 0X0 1010101 Pos 0s): Bo = 0x01 ™MeEM32 [0 x 0O0GN0EF = O AO2020202. s(t Ox vo0gy 4 LR vo, [4,44]! Preindesing with urtiteback s | PosT(1) “vo Ox 02020202 12 Ox 00009004 Loe to, [v, , t#4] Pre inclexing $ POst(2) : vo 70N02020202 %, =0x00009000; Date... Page No. .3. | pot N° ———— Cerise otis logical insrwetiont in ARM processes wh | lan example” es ‘abbrootions pev-fore bihoise logical Operations Logis! ra Closes Sovtee Tess Hers: i 2 —Teyntax 3 logics! Cruise AND of $0 _9)-bi+ vatuss] Rel2Rne [eee S logial vinwise OR of tar s-cit RAK [Ro= Rel) [eo S logical exclubve OR of tO B2-Vt valves |Rd= RoI BIC > logical bit clear (ANB NOT] Rd =Rn orl Ch | i> Qnty — ogi eal 4NS— | vow ei #OKFO 5 1110000 Mov R2, #OxOF 5 0000 III! AND Ro, 2, ,R2 3 Ros @ AND R2 = 0000 5000 ~ Exclvsve_ iSEOR — Logical, OR- Mov er, #OxKAA 4 O10 1010 Mov R2, +6 * Peel Aah) LL BOR Re, RRs 5 RO = OIO! 0101 Sir M.Visvesvaraya Institute of Technology, Bengaluru - 57i Wy ORR— logiesl OR- ae Mov @1 ,w#oxFO 3119 | 0000 mov R2, to xOF; 00 00 Wee! ORR Roeh,e2 ; Rossii) NN | WS BIC (Rit Cleat)— AND with NOT- Mov Ri, HORE 4 @\\ ian Mov @®, , ORKOF 34 pooo iil Bie RO,& kX 3 FO=RI AND (HOTF2) = INI] D000 ; —- oC g- Explain different onithmene ingtietiong in ARM pw comes vorth an example: @ ane omithmetc “AStauctions implement actlition and Sobteaction Of 32-bit signed And onsinned values: = fau- fp 3st Rd 2 Syngas ABC — Add with came Ot adds 00 3) bit Yaluah and cary Yea = Rn +N + orty | Mov Ri, 4 OXFFFREFFF Mov R2, #2 A_CS RO, RI,RX 5} RO=ORXPEFFEFFR Fat canny iDates eheten a Page No. = Ade «AC! 1. rw peas 4wO 32-bit valuet + (3 2 Ra +N } | e 4 if) Ri 410 Ot | P| mov 22,490 7 ABD ko,e1 (22 5 ROFP' +P2 = 30 a | Feoisve = stoect E bo Fl gubtsact 200 32-bit nls - § Rd =Rn -N} -_— + : g MOV Ri _, #50 mov Pr, +20 Rue Re,k, P23 RO= &i-Ro = 30 wl $BC— Subtraction With cerry Lt T+ substacts With easy of huo 2) -bit Vsluey- fed = Ra-N — !@sey fag) Mov 1 ,4P10 Mou R2,+43 SBC Ro, Ri R22 5 RO=k, - R2~ (1- casry) [| ks8 — Reverse Subtvact - LIT tevesse subgtacts of two 32-bit valuets _jRat = N -ROf L2) Mov ei #20 Mov Ra, #10 | ea S** Ro, Ri, RD 4 RO=Q-ki =O Sir M.Visvesvaraya Institute of Technology, Bengaluru - 57ise cavty =1 7 RO=Ro -R1-(2-C) =10-S-9 5 a eet