Module 1- Verilog HDL –

Data Flow & Structural

Modeling
Dr.P.Augusta Sophy,
SENSE,
VIT Chennai
Module 1
 Lexical Conventions
 Ports and Modules
 Operators
 Gate Level Modeling
 Data Flow Modeling
 System Tasks & Compiler Directives
 Test Bench.
What is HDL?

 Hardware Description Language

 It is a High Level Language
To describe the circuits by syntax and
sentences
 Widely used HDLs
Verilog – Similar to C
SystemVerilog – Similar to C++
VHDL – Similar to PASCAL
Verilog HDL
 Verilog HDL is a Hardware Description Language (HDL).
 A HDL can be used to describe a digital system, like ALU, MUX ,
adder, processor and so on
 We can describe a digital system at several levels of abstraction,
Switch level, Gate level and even high level called as Register
Transfer Level (RTL)
 Verilog is one of the two major Hardware Description Languages
(HDL) used by hardware designers in industry and academia
 Verilog was introduced in 1985 by Gateway Design System
Corporation, now a part of Cadence Design Systems
 In Verilog we can describe designs at a high level of abstraction
such as at the architectural or behavioral level as well as the
lower implementation levels (i. e. , gate and switch levels)
Very Important

 While writing a Verilog code

Think in hardware !!
Basic Limitation of Verilog

Description of digital systems only

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Abstraction Levels (in Verilog)

Behavioral

RTL Our focus

Gate

Layout (VLSI)

7
Important concept (i)

 Concurrency

 Structure

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Important Concept (ii)

 Procedural Statements

 Time

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Lexical Conventions

 Formats related to the Verilog language

 Keywords
 Spaces
 Number formats
 Strings
 Operators
 Identifiers
 Program Structure
 User Identifiers
 Formed from {[A-Z], [a-z], [0-9], _, $}, but ..
 .. can’t begin with $ or [0-9]
◦ myidentifier
◦ m_y_identifier
◦ 3my_identifier - wrong
◦ $my_identifier - wrong
◦ _myidentifier$ - Correct
 Case sensitivity
◦ myid  Myid

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 Comments

 // The rest of the line is a comment

 /* Multiple line
comment */

 /* Nesting /* comments */ do NOT

work */

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Verilog Value Set
 0 represents low logic level or false
condition

 1 represents high logic level or true

condition

 x represents unknown logic level

 z represents high impedance logic level

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 Numbers in Verilog
<size>’ <radix> <value>

Binary  b or B
No of Consecutive chars
Octal  o or O
bits 0-f, x, z
Decimal  d or D
Hexadecimal  h or H

◦ 8’h ax = 1010xxxx
◦ 12’o 3zx7 = 011zzzxxx111
◦ 4’d 15 = 1111
◦ 6’b 1100_10
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Numbers in Verilog -contd
 You can insert “_” for readability
◦ 12’b 000_111_010_100
◦ 12’b 000111010100
Represent the same number
◦ 12’o 07_24
 Bit extension
◦ MS bit = 0, x or z  extend this
 4’b x1 = 4’b xx_x1
◦ MS bit = 1  zero extension
 4’b 1x = 4’b 00_1x

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Numbers in Verilog - contd
 If size is ommitted it
◦ is inferred from the value or takes the
simulation specific number of bits or
◦ takes the machine specific number of bits (32
or 64)

 If radix is ommitted

 .. decimal is assumed
◦ 15 = <size>’d 15
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Negative Numbers
 ‘-’ sign before the no of bits
 -6’d14 – 6 bit is used to store -14 in the
2’s complement form
 6’d-14 – illegal format
Negative numbers
 +22D = 0001 0110B
 +22 = 0001 0110 - SM
 -22 = 1001 0110- sign Magnitude form
 -22 = 1110 1010 – 2’s complement form
37 & -37 –use 8 bits
37D = 00100101B
-37 = 1010 0101 – SM
-37 = 11011011- 2CM
 Nets & Netlists
 Can be thought as hardware wires driven by logic
 Equal to z when unconnected
 Various types of nets
◦ Wire – net having single driver
◦ wand (wired-AND) – has multiple drivers
◦ wor (wired-OR)
◦ tri (tri-state) – net having multiple driver
 In following examples: Y is evaluated,
automatically, every time A or B changes
 The netlist logically consists of several different
components: Blocks, Ports, Pins and Nets

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 Nets - contd
Input A,B;
A wire A,B,Y; // declaration
Y
B assign Y = A & B;

wire A,B;
wand Y; // declaration
A
Y
B
wire A,B;
wor Y; // declaration

dr
tri Y; // declaration
A Y
assign Y = (dr) ? A : z;

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 Registers
 Variables that store values
 Do not represent real hardware but ..
 .. real hardware can be implemented with registers
 Only one type: reg
reg A, C,B; // declaration
// assignments are always done inside a
always@(*)//* - inputs
begin
A = 1;
C = ~A;
B = C;
end
Register values are updated explicitly!!

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 Vectors
 Represent buses
input A,B[3:0];// A = A[3]A[2]A[1]A[0]
Input A[0:3];// A =A[0]A[1]A[2]A[3]
wire [3:0] busA; //A3A2A1A0
reg [1:4] busB;
reg [1:0] busC;

 Left number is MS bit

 Slice management
busC = busA[3:2];
busC[1] = busA[2];

busC[0] = busA[1];

 Vector assignment (by position!!)

busB[1] = busA[3];
busB[2] = busA[2];
busB = busA;
busB[3] = busA[1];

busB[4] = busA[0];

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Integer & Real Data Types
 Declaration
integer i, k;
real r;
i = 1; // assignments occur
inside procedure
r = 2.9;
k = r; // k is rounded to 3
 Integers are not initialized!!
 Reals are initialized to 0.0

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Time Data Type
 Special data type for simulation time measuring
 Declaration
time my_time;
 Use inside procedure
my_time = $time; // get current sim
time
 Simulation runs at simulation time, not real
time

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 Arrays (i)
 16bits X 32 words
 Reg [15:0] mem [31:0]
 Syntax
◦ integer count[1:5]; // 5 integers named count[1],
count[2] etc
◦ reg var[-15:16]; // 32 1-bit regs
◦ reg count[3:0] ; // count is a 4-bit reg
◦ reg [7:0] mem[0:1023];//1024 8-bit regs
 Accessing array elements
◦ Entire element: mem[10] = 8’b 10101010;
◦ Element subfield (needs temp storage):
reg [7:0] temp;
..
temp = mem[10];
var[6] = temp[2];

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Arrays -contd
 Limitation: Cannot access array subfield
or entire array at once
 No multi-dimentional arrays
reg var[1:10] [1:100];//WRONG!!
 Arrays don’t work for the Real data type
real r[1:10]; // WRONG !!

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 Strings
 Implemented with regs:
reg [8*13:1] string_val; // can hold up to 13 chars
..
string_val = “Hello Verilog”;
string_val = “hello”; // MS Bytes are filled with 0
string_val = “I am overflowed”; // “I ” is truncated

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Verilog Operators
Logical Operators
 &&  logical AND
 ||  logical OR
!  logical NOT
 Operands evaluated to ONE bit value: 0, 1
or x
 Result is ONE bit value: 0, 1 or x
A = 6; A && B  1 && 0  0
B = 0; A || !B  1 || 1  1
C = x; C || B  x || 0  x
but C&&B=0

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Bitwise (Logical) Operators
 &  bitwise AND
|  bitwise OR
~  bitwise NOT
^  bitwise XOR
 ~^ or ^~  bitwise XNOR

 Operation on bit by bit basis

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 Bitwise Operators - contd
c = ~a; c = a & b;

 a = 4’b1010;
b = 4’b1100;

c = a ^ b;

 a = 4’b1010;
b = 2’b11;

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 Reduction Operators
 &  AND
 |  OR
 ^  XOR
 ~&  NAND
 ~|  NOR
 ~^ or ^~  XNOR

 One multi-bit operand  One single-bit result

a = 4’b1001;
..
c = |a; // c = 1|0|0|1 = 1

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Shift Operators
 >>  shift right
 <<  shift left

 Result is same size as first operand

 always zero filled

a = 4’b1010;
...
d = a >> 2; // d = 0010
c = a << 1; // c = 0100

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 Concatenation Operator
 {op1, op2, ..}  concatenates op1, op2, .. to single number
 Operands must be sized !!
reg a;
reg [2:0] b, c;
..

a = 1’b 1;
b = 3’b 010;
c = 3’b 101;
catx = {a, b, c}; // catx = 1_010_101
caty = {b, 2’b11, a}; // caty = 010_11_1
catz = {b, 1}; // WRONG !!
 Replication ..
catr = {4{a}, b, 2{c}}; // catr =
1111_010_101101

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 Relational Operators
 >  greater than
 <  less than
 >=  greater than or equal
 <=  less than or equal

 Result is one bit value: 0, 1 or x

1 > 0 1
’b1x1 <= 0 x
10 < z x

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 Equality Operators
 ==  logical equality
Return 0, 1 or x
 !=  logical inequality
 ===  case equality (identity)
Return 0 or 1
 !==  case inequality

◦ 4’b 1z0x == 4’b 1z0x x

◦ 4’b 1z0x != 4’b 1z0x x
◦ 4’b 1z0x === 4’b 1z0x 1
◦ 4’b 1z0x !== 4’b 1z0x 0

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Conditional Operator
 cond_expr ? true_expr :
false_expr

 Like a 2-to-1 mux ..

A
1
Y
B Y = (sel)? A : B;
0
sel

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 Arithmetic Operators
 +, -, *, /, %
 If any operand is x the result is x
 Negative registers:
◦ regs can be assigned negative but are treated as unsigned
reg [15:0] regA;
..
regA = -4’d12; // stored as 216-12 = 65524
regA/3 evaluates to 21861

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 Arithmetic Operators - contd
 Negative integers:
◦ can be assigned negative values
◦ different treatment depending on base specification or not
reg [15:0] regA;
integer intA;
..
intA = -12/3; // evaluates to -4 (no base spec)
 Avoid negative numbers of the type <sss> '<base> <nnn> in expressions
because they are converted to unsigned 2's complement numbers and hence
yield unexpected results.
intA = -’d12/3; // evaluates to 1431655761 (base spec)

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Operator Precedence

Use parentheses to
enforce your
priority

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Have a good day!

41
 Verilog is case sensitive.

 Verilog synthesizers treat the white space ‘ ‘ and carriage

returns differently

 “beginmodule” and “endmodule” are reserved words in

Verilog.

 The semantics of an “&” operator depends on the number of

operands.

 An “if” statement must always be inside of an “always” block.

 Verilog is case sensitive. - True

 Verilog synthesizers treat the white space ‘ ‘ and carriage

returns differently - False

 “beginmodule” and “endmodule” are reserved words in

Verilog. - False

 The semantics of an “&” operator depends on the number of

operands. - True

 An “if” statement must always be inside of an “always” block.

- True