Module 1- Verilog HDL –

Data Flow & Structural

Modeling
Dr.P.Augusta Sophy,
SENSE,
VIT Chennai

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Module 1
 Lexical Conventions
 Ports and Modules
 Operators
 Gate Level Modeling
 Data Flow Modeling
 System Tasks & Compiler Directives
 Test Bench.

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Verilog ‘module’
 Modules can represent pieces of hardware ranging
from simple gates to complete systems, even a MP.
 Modules are the basic entity of a Verilog program
 There can be many modules in a Verilog program.
Modules run concurrently
 One top level module may specify a closed system
containing both test data and hardware models.
 The top level module invokes instances of other
modules.

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Structure of a Verilog Module
 module <module name> (<port list>);
<declarations>
<module items>
endmodule
 The module name is an identifier that uniquely
names the module.
 The port list is a list of input, inout and output
ports which are used to connect to other modules.
 The declares section specifies data objects as
registers, memories and wires as wells as
procedural constructs
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Verilog Module - contd
 The module items may be initial constructs,
always constructs, continuous
assignments or instances of modules.
 The semantics of the module construct in
Verilog is very different from subroutines,
procedures and functions in other
languages.
 A module is never called! A module is
instantiated at the start of the program and
stays around for the life of the program.
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Module Example
A A
S S

B B
C C

module half_adder(S, C, A, B);

output S, C;
input A, B;
wire S, C, A, B;
assign S = A ^ B;
assign C = A & B;
endmodule
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Types of Modeling
 Structural Modeling
◦ Gate level Modeling (Use Gate level primitives)
◦ Describes the structure of the hardware components
 Data Flow Modeling
◦ Use Boolean expressions to describe the
functionality.
 Behavioral Modeling
◦ Models describe what a module does.
◦ Use of assignment statements, loops, if, else kind of
statements

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Continuous Assignments

 Syntax:
assign #delay <id> = <expr>;

optional net

 Where to write them:

◦ inside a module
◦ outside procedures
 Properties:
◦ they all execute in parallel
◦ are order independent
◦ are continuously active

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Structural Model (Gate Level)
 Built-in gate primitives:
and, nand, nor, or, xor, xnor, buf, not, bufif0,
bufif1, notif0, notif1

 Usage:
nand (out, in1, in2); 2-input NAND without delay
and #2 (out, in1, in2, in3); 3-input AND with 2 t.u. delay
not #1 N1(out, in); NOT with 1 t.u. delay and instance name
xor X1(out, in1, in2); 2-input XOR with instance name

 Write them inside module, outside

procedures

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Example: Half Adder,
2nd Implementation – Gate level Structural
Modeling

A module half_adder(S, C, A, B);

S
output S, C;
B input A, B;
C
wire S, C, A, B;

xor #2 (S, A, B);

and #1 (C, A, B);
Assuming:
• XOR: 2 t.u. delay endmodule
• AND: 1 t.u. delay

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Half Adder – Data Flow Modeling
module half_adder(S,C,A,B);
output S, C;
input A, B;
wire S, C, A, B;
assign S = A ^ B;
assign C = A & B;
endmodule

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Half Adder- Behavioral Modeling
module half_adder(S,C,A,B);
output reg S, C;
input A, B;
//reg S,C;
always@(A,B)
begin
S = A ^ B;
C = A & B;
end
endmodule
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 Behavioral Model - Procedures (i)
 Procedures = sections of code that we know they
execute sequentially
 Procedural statements = statements inside a
procedure (they execute sequentially)
 e.g. another 2-to-1 mux implem:
begin
if (sel == 0)
Y = B;
Execution
Flow
else Procedural assignments:
Y must be reg !!
Y = A;
end

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 Behavioral Model - Procedures (ii)

 Modules can contain any number of procedures

 Procedures execute in parallel (in respect to each
other) and ..
 .. can be expressed in two types of blocks:
◦ initial they execute only once
◦ always  they execute for ever (until simulation
finishes)

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“Initial” Blocks
 Start execution at sim time zero and finish
when their last statement executes
module nothing;

initial
Will be displayed
$display(“I’m first”);
at sim time 0

initial begin
#50; Will be displayed
$display(“Really?”); at sim time 50
end

endmodule

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 “Always” Blocks
 Start execution at sim time zero and
continue until sim finishes

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Events (i)
 @
always @(signal1 or signal2 or ..) begin
..
end execution triggers every
time any signal changes

always @(posedge clk) begin

.. execution triggers every
end time clk changes
from 0 to 1

always @(negedge clk) begin

execution triggers every
..
time clk changes
end
from 1 to 0

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 Examples
 3rd half adder implementation  Behavioral edge-triggered DFF
module half_adder(S, C, A, B); implem
output S, C; module dff(Q,QB,D, Clk);
input A, B; output Q,QB;
input D, Clk;
reg S,C;
wire A, B; reg Q,QB;
wire D, Clk;
always @(A or B) begin
S = A ^ B; always @(posedge Clk)
C = A && B; Q = D;
end
endmodule
endmodule

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Events (ii)
execution loops every
 wait (expr) time ctrl = 1 (level
always begin
sensitive timing control)
wait (ctrl)
#10 cnt = cnt + 1;
#10 cnt2 = cnt2 + 2;

end

 e.g. Level triggered DFF ?

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Example

res
a
b Y

c W
clk

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always @(res or posedge clk) begin
if (res) begin
Y = 0;
W = 0;
end
else begin
Y = a & b;
W = ~c;
end
end

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 Mixed Model
Code that contains various both structure and behavioral styles
module simple(Y, c, clk, res);
output Y;
input c, clk, res;

reg Y;
wire c, clk, res;
res wire n;
c n Y Not g1(n, c); // gate-level
clk
always @(res or posedge clk)
if (res)
Y = 0;
else
Y = n;
endmodule

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4:1 Mux

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Procedural Statements: if
E.g. 4-to-1 mux:
module mux4_1(out, in, sel);
output out;
if (expr1) input [3:0] in;
true_stmt1; input [1:0] sel;

reg out;
else if (expr2) wire [3:0] in;
wire [1:0] sel;
true_stmt2;
.. always @(in or sel)
if (sel == 0)// (sel=2’b0
else out = in[0];
def_stmt; else if (sel == 1)
out = in[1];
else if (sel == 2)
out = in[2];
else
out = in[3];
endmodule

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Procedural Statements: case

E.g. 4-to-1 mux:

module mux4_1(out, in, sel);
output out;
input [3:0] in;
input [1:0] sel;

reg out;
wire [3:0] in;
wire [1:0] sel;

always @(in or sel)

case (sel)// case({s1,s0})
0: out = in[0];
1: out = in[1];
2: out = in[2];
3: out = in[3];
default:out =1’b0;
endcase
endmodule

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 Timing (i)

d
initial begin
#5 c = 1; c
#5 b = 0;
#5 d = c; b
end
0 5 10 15
Time
Each assignment is
blocked by its previous one

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 Timing (ii)

d
initial begin
fork c
#5 c = 1;
#5 b = 0; b
#5 d = c;
join 0 5 10 15
end Time

Assignments are
not blocked here

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Procedural Statements: for
for (init_assignment; cond; step_assignment)
stmt;
E.g.
module count(Y, start);
output [3:0] Y;
input start;

reg [3:0] Y;
wire start;
integer i;

initial
Y = 0;

always @(posedge start)

for (i = 0; i < 3; i = i + 1)
#10 Y = Y + 1;
endmodule

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Procedural Statements: while

E.g.
module count(Y, start);
output [3:0] Y;
input start;

reg [3:0] Y;
wire start;
integer i;
while (expr) stmt;
initial
Y = 0;

always @(posedge start) begin

i = 0;
while (i < 3) begin
#10 Y = Y + 1;
i = i + 1;
end
end
endmodule

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Procedural Statements: repeat

E.g.
module count(Y, start);
output [3:0] Y;
input start;

repeat (times) stmt; reg [3:0] Y;

wire start;

initial
Can be either an Y = 0;
integer or a variable
always @(posedge start)
repeat (4) #10 Y = Y + 1;
endmodule

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Procedural Statements: forever

Typical example:
clock generation in test modules
module test;

reg clk; Tclk = 20 time units

forever stmt;
initial begin
clk = 0;
forever #10 clk = ~clk;
Executes until sim end
finishes
other_module1 o1(clk, ..);
other_module2 o2(.., clk, ..);

endmodule

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Have a good day!

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