Verilog HDL Basics

Dr. Vasudeva
ECE Dpt.
MREC (A), Hyderabad
e-mail: vasudeva@mrec.ac.in

August 2023
 What is Verilog

• Hardware Description Language (HDL)

• Developed in 1984

• Standard: IEEE 1364, Dec 1995

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 Application Areas of Verilog
System Specification Suitable for all levels
Behavioral level
Not suitable
HW/SW
Partition
Hardware Softwre
Spec Spec

ASIC

FPGA Boards
& Software
PLD Systems
Std Parts
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 Basic Limitation of Verilog

Description of digital systems only

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 Abstraction Levels in Verilog

Behavioral

RTL Our focus

Gate

Layout (VLSI)

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 User Identifiers
• Formed from {[A-Z], [a-z], [0-9], _, $}, but ..
• .. can’t begin with $ or [0-9]
– myidentifier 
– m_y_identifier 
– 3my_identifier 
– $my_identifier 
– _myidentifier$ 
• Case sensitivity
– myid  Myid

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 Comments

• // The rest of the line is a comment

• /* Multiple line
comment */

• /* Nesting /* comments */ do NOT work

*/

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 Verilog Value Set

• 0 represents low logic level or false condition

• 1 represents high logic level or true condition

• x represents unknown logic level

• z represents high impedance logic level

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 Numbers in Verilog (i)

<size>’<radix> <value>

No of Binary  b or B Consecutive chars

bits Octal  o or O 0-f, x, z
Decimal  d or D
Hexadecimal  h or H

– 8’h ax = 1010xxxx
– 12’o 3zx7 = 011zzzxxx111

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 Numbers in Verilog (ii)

• You can insert “_” for readability

– 12’b 000_111_010_100
– 12’b 000111010100 Represent the same number
– 12’o 07_24
• Bit extension
– MS bit = 0, x or z  extend this
• 4’b x1 = 4’b xx_x1
– MS bit = 1  zero extension
• 4’b 1x = 4’b 00_1x

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 Nets (i)
• Can be thought as hardware wires driven by logic
• Equal z when unconnected
• Various types of nets
– wire
– wand (wired-AND)
– wor (wired-OR)
– tri (tri-state)
• In following examples: Y is evaluated,
automatically, every time A or B changes
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 Nets (ii)
A wire Y; // declaration
Y
B assign Y = A & B;

wand Y; // declaration
assign Y = A;
A assign Y = B;
Y
B
wor Y; // declaration
assign Y = A;
assign Y = B;

dr
tri Y; // declaration
A Y
assign Y = (dr) ? A : z;

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 Logical Operators

• &&  logical AND

• ||  logical OR
• !  logical NOT
• Operands evaluated to ONE bit value: 0, 1 or x
• Result is ONE bit value: 0, 1 or x
A = 6; A && B  1 && 0  0
B = 0; A || !B  1 || 1  1
C = x; C || B  x || 0  x but C&&B=0

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 Bitwise Operators (i)

• &  bitwise AND

• |  bitwise OR
• ~  bitwise NOT
• ^  bitwise XOR
• ~^ or ^~  bitwise XNOR

• Operation on bit by bit basis

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 Bitwise Operators (ii)
c = ~a; c = a & b;

• a = 4’b1010;
b = 4’b1100;

c = a ^ b;

• a = 4’b1010;
b = 2’b11;

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 Reduction Operators
• &  AND
• |  OR
• ^  XOR
• ~&  NAND
• ~|  NOR
• ~^ or ^~  XNOR

• One multi-bit operand  One single-bit result

a = 4’b1001;
..
c = |a; // c = 1|0|0|1 = 1

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 Shift Operators
• >>  shift right
• <<  shift left

• Result is same size as first operand, always zero filled

a = 4’b1010;
...
d = a >> 2; // d = 0010
c = a << 1; // c = 0100

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 Relational Operators
• >  greater than
• <  less than
• >=  greater or equal than
• <=  less or equal than

• Result is one bit value: 0, 1 or x

1 > 0 1
’b1x1 <= 0  x
10 < z x
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 Equality Operators
• ==  logical equality
Return 0, 1 or x
• !=  logical inequality
• ===  case equality
Return 0 or 1
• !==  case inequality

– 4’b 1z0x == 4’b 1z0x x

– 4’b 1z0x != 4’b 1z0x  x
– 4’b 1z0x === 4’b 1z0x  1
– 4’b 1z0x !== 4’b 1z0x  0

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 Conditional Operator

• cond_expr ? true_expr : false_expr

• Like a 2-to-1 mux ..

A
1
Y
B Y = (sel)? A : B;
0
sel

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 Hierarchical Design

Top Level
E.g.
Module

Full Adder
Sub-Module Sub-Module
1 2

Half Adder Half Adder

Basic Module Basic Module Basic Module
1 2 3

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 Module
module my_module(out1, .., inN);

in1 my_module out1 output out1, .., outM;

in2 out2 input in1, .., inN;

f .. // declarations
inN outM .. // description of f (maybe
.. // sequential)

endmodule

Everything you write in Verilog must be inside a module

exception: compiler directives

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 Example: Half Adder

A module half_adder(S, C, A, B);

S
output S, C;
B input A, B;
C
wire S, C, A, B;

A S assign S = A ^ B;
Half assign C = A & B;
B Adder C
endmodule

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 Example: Full Adder
in1 A Half S I1 A Half S sum
Adder 1 I2 Adder
in2 B C B C I3
ha1 ha2 cout

cin
module full_adder(sum, cout, in1, in2, cin);
output sum, cout;
input in1, in2, cin;

wire sum, cout, in1, in2, cin;

Module wire I1, I2, I3; Instance
name name
half_adder ha1(I1, I2, in1, in2);
half_adder ha2(sum, I3, I1, cin);

assign cout = I2 || I3;

endmodule
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 Hierarchical Names

ha2.A

in1 A Half S I1 A Half S sum

Adder 1 I2 Adder
in2 B C B C I3
ha1 ha2 cout

cin

Remember to use instance names,

not module names

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 Port Assignments

module
• Inputs reg or net net

module

• Outputs reg or net net

module

net net
• Inouts

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 Structural Model (Gate Level)

• Built-in gate primitives:

and, nand, nor, or, xor, xnor, buf, not, bufif0,
bufif1, notif0, notif1

• Usage:
nand (out, in1, in2); 2-input NAND without delay
and #2 (out, in1, in2, in3); 3-input AND with 2 t.u. delay
not #1 N1(out, in); NOT with 1 t.u. delay and instance name
xor X1(out, in1, in2); 2-input XOR with instance name

• Write them inside module, outside procedures

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 Example: Half Adder,
2nd Implementation
A module half_adder(S, C, A, B);
S
output S, C;
B input A, B;
C
wire S, C, A, B;

xor a1(S, A, B);

and a2(C, A, B);

endmodule

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 Behavioral Model - Procedures (i)
• Procedures = sections of code that we know they
execute sequentially
• Procedural statements = statements inside a
procedure (they execute sequentially)
• e.g. another 2-to-1 mux implem:
begin
if (sel == 0)
Execution Y = B;
Flow Procedural assignments:
else
Y must be reg !!
Y = A;
end
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 Behavioral Model - Procedures (ii)

• Modules can contain any number of procedures

• Procedures execute in parallel (in respect to each
other) and ..
• .. can be expressed in two types of blocks:
– initial  they execute only once
– always  they execute for ever (until simulation finishes)

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 “Initial” Blocks
• Start execution at sim time zero and finish when
their last statement executes
module nothing;

initial
$display(“I’m first”); Will be displayed
at sim time 0
initial begin
#50;
$display(“Really?”); Will be displayed
end at sim time 50

endmodule

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 “Always” Blocks
• Start execution at sim time zero and continue until
sim finishes

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 Events (i)
• @
always @(signal1 or signal2 or ..) begin
..
end execution triggers every
time any signal changes
always @(posedge clk) begin
.. execution triggers every
end time clk changes
from 0 to 1
always @(negedge clk) begin
.. execution triggers every
end time clk changes
from 1 to 0

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 Examples
• 3rd half adder implem • Behavioral edge-triggered
module half_adder(S, C, A, B); DFF implem
output S, C; module dff(Q, D, Clk);
input A, B; output Q;
input D, Clk;
reg S,C;
wire A, B; reg Q;
wire D, Clk;
always @(A or B) begin
S = A ^ B; always @(posedge Clk)
C = A && B; Q = D;
end
endmodule
endmodule

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 Example

always @(res or posedge clk) begin

res if (res) begin
a Y = 0;
b Y W = 0;
end
else begin
c W Y = a & b;
W = ~c;
clk end
end

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 Timing (i)

d
initial begin
#5 c = 1; c
#5 b = 0;
#5 d = c; b
end
0 5 10 15
Time
Each assignment is
blocked by its previous one

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 Timing (ii)

d
initial begin
fork c
#5 c = 1;
#5 b = 0; b
#5 d = c;
join 0 5 10 15
end Time

Assignments are
not blocked here

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 Example: Simple Circuit Diagram

All examples and code from Mano “Digital Design” 3rd Ed.
Example: Simple Circuit HDL
module smpl_circuit(A,B,C,x,y);
input A,B,C;
output x,y;
wire e;
and g1(e,A,B);
not g2(y, C);
or g3(x,e,y);
endmodule
 Simple Circuit Notes

• The module starts with module keyword and

finishes with endmodule.
• Internal signals are named with wire.
• Comments follow //
• input and output are ports. These are placed
at the start of the module definition.
• Each statement ends with a semicolon, except
endmodule.
Circuit to code

module smpl_circuit(A,B,C,x,y);
input A,B,C;
output x,y;
wire e;
and g1(e,A,B);
not g2(y, C);
or g3(x,e,y);
endmodule
 Input signals

• In order to simulate a circuit the input signals need

to be known so as to generate an output signal.
• The input signals are often called the circuit
stimulus.
• An HDL module is written to provide the circuit
stimulus. This is known as a testbench.
 Testbench

• The testbench module includes the module to be

tested.
• There are no input or output ports for the testbench.
• The inputs to the test circuit are defined with reg and
the outputs with wire.
• The input values are specified with the keyword
initial
• A sequence of values can be specified between
begin and end.
 Signal Notation

• In Verilog signals are generalised to support

multi-bit values (e.g. for buses)
– The notation
A = 1’b0;

– means signal A is one bit with value zero.

• The end of the simulation is specified with
$finish.
Stimulus module for simple circuit
module stimcrct;
reg A,B,C;
wire x,y;
circuit_with_delay cwd(A,B,C,x,y);
initial
begin
A = 1'b0; B = 1'b0; C = 1'b0;
#100
A = 1'b1; B = 1'b1; C = 1'b1;
#100 $finish;
end
endmodule
 Gate Level Modelling

• The simple circuit used so far is an example of

gate-level modelling.
• The module is a text description of the circuit
layout.
• Verilog has all the standard gates
• and, nand
• or, nor
• xor, xnor
• not, buf
 Dataflow modelling

• Another level of abstraction is to model dataflow.

• In dataflow models, signals are continuously
assigned values using the assign keyword.
• assign can be used with Boolean expressions.
– Verilog uses & (and), | (or), ^ (xor) and ~ (not)
• Logic expressions and binary arithmetic are also
possible.
 Dataflow description of 2-input Mux
• Conditional operator ?:takes three operands:
condition? true_expression : false_expression

module mux2x1_df (A,B,select,OUT);

input A,B,select;
output OUT;
assign OUT = select ? A : B;
endmodule
 Behavioural Modelling

• Represents circuits at functional and algorithmic

level.
• Use proceedural statements similar in concept to
proceedural programming languages (e.g. C,
Java),
• Behavioural modelling is mostly used to represent
sequential circuits.
 Behavioural Modelling

• Behavioural models place proceedural statements

in a block after the always keyword.
• The always keyword takes a list of variables.
The block of statements is executed whenever one
of the variables changes.
• The target variables are of type reg. This type
retains its value until a new value is assigned.
Behavioral description of 2-input mux

module mux2x1_bh(A,B,select,OUT);
input A,B,select;
output OUT;
reg OUT;
always @ (select or A or B)
if (select == 1) OUT = A;
else OUT = B;
endmodule
 HDL Summary

• Hardware Description Languages allow fast

design and verification of digital circuits.
• Accurate simulation and testing requires delays
and inputs to be specified.
• There are three different levels of abstraction for
modelling circuits.