1.

110/220V

ON/OFF

1
 IC
PLD Programmable Logic Device FPGA
Field Programmable Gate Array

1.2

VHDL

2
 PID PWM
FPGA A/D

1.3
FPGA
FPGA IC

FPGA [1]
ADAPTIVE FPGA FPGA VHDL
ADAPTIVE FPGA [2][3] FPGA
Neural Networks [4] Fuzzy
FPGA IC [5]
FPGA [6] FPGA
PWM IC [7] FPGA
Encoder
FPGA
FPGA [8][9] FPGA
[10] FPGA Java

FPGA FPGA
PWM PID FPGA
IC

3
1.4

FPGA

Matlab/Simulink

4
 FPGA

FPGA
,

FPGA

FPGA 2.1
2.2 FPGA
CPLD 2.3 FPGA Xilinx
XC4000XL FPGA 2.4
FPGA VHDL

5
 Design entry

Pre-Simulation

IC Layout

Post-Simulation

(1) (Design Entry)

(Schematics) (Hardware Description Language)

6
(2) (Pre-Simulation)

(3) (Layout)

(4) (Post-Simulation)
(Cell
Delay) (Path Delay)…
(Post-Layout Simulation)

(1) Full Custom ICs( IC)

(2) Cell Base ICs( IC)

7
 Cell Base ICs
Cell Cell Cell Library

Logic

ASIC Stand Logic

PLD Gate Array Cell_Based ICs Full Custom ICs

SPLD FPGA CPLD

(3) Gate Arrays( )

Gate Array CMOS
PMOS NMOS
IC
PLD
PLD IC
A. SPLD
PLD(Simple PLD) PROM PAL PLA

8
 AND OR
PROM OR AND PAL AND
OR PLA AND OR
B. CPLD
CPLD(Complex PLD) PLD
(Logic Blocks)
PLD 2.3 Xilinx XC9500XL CPLD

2.3 XC9500XL [32]

9
C. FPGA
FPGA File Programmable Gate Array
(Logic Cell) (Vertical Channel) (Horizontal
Channel) 2.4 CPLD FPGA
FPGA IO

CPLD

Logic Cell

FPGA

10
2.3 FPGA
2.2 FPGA FPGA
Xilinx XC4000XL FPGA
2.3.1 FPGA
FPGA
(Configurable Logic Block CLB) CLB
CLB CLB
(Routing) CLB
FPGA
(I/O Block) FPGA
FPGA
A. SRAM

B. Anti-fuse

2.3.2 XC4000XL
Xilinx XC4000XL
XC4005XL-PC84 FPGA ,

11
 1 RAM
/
2 PCI
3
4
5

8 80MHz

10 IC
(2.5) XC4000X CLB I/O
(Interconnect)

Programmable
interconnect I/O Block (IOBs)

Configurable
Logic Block (CLBs)
FPGA

12
(1) CLB
FPGA CLB FPGA
CLB (2.6) XC4000X CLB CLB

CLB
F G
CLB

XC4000X CLB

(2) IOB
IOB IOB
(2.7)

13
XC4000X IOB

XC4000X IOB

(3)
IOB CLB CLB CLB FPGA
(routing)

2.4 VHDL

(Functional Design) (Physical Design)

14
 VHDL Verilog AHDL
VHDL(Very High Speed Integrated Circuit Hardware Description
Language)
2.4.1 VHDL
(1)
VHDL (Description) (Synthesis)
(Simulation)

(2)
VHDL
VHDL

(3)

15
 VHDL

2.4.2 VHDL
(1) Entity
(Entity)

(2) Architecture
(Architecture)

(3) Configuration
(Configuration)

(4) Package
(Package)
(5) Driver
(Driver)
(6) Attribute
(Attribute) VHDL VHDL

(7) Process
(Process) VHDL VHDL

16
2.5 FPGA
VHDL
VHDL FPGA
Xilinx Foundation 1.5
VHDL FPGA
Xilinx Foundation 1.5
(2.8) Foundation 1.5 Foundation 1.5
(2.9)

17
 N

FPGA

FPGA

18
 1
HDL (Hardware
Description Language ) (Schematic Editor)
(State Editor)
HDL
HDL (Macro)

(Logic Simulator)

HDL
3

Foundation Implementation netlist

netlist
FPGA
4
FPGA (Timing
Simulation)
5
Hardware Debuger
FPGA
FPGA

19
FPGA FPGA
FPGA

20
 (refrigerant) (compressor) (condenser)
(expansion value) (refrigerant control)
(evaporator) (3.1)

Low Pressure High Pressure

Expansion

Evaporator Condenser

Compressor

3.1

(1)

21
(2)

(3)

(4)

22
 Constant air volume induction system
CAV System

2 Variable air volume constant temperature

system
VAV System

23
 1
2
3
4
5
QgD

QgD = A × SC × SHGF × CLF

A : (m2)
SC : shading cofficient
SHGF : kcal/hrm2
CLF : cooling load factor
SHGF
QgD
Qg Qg

Qg = U g × A × CTLD

Ug : kcal/hr.m2.
A : (m2)
CTLD :
Ug A 3.2

24
 Qg = K g × CTLD = K g × (TOA − TRA )

TOA TRA Kg
QW QW

1
Qw = U w × A × CTLD = × A × CTLD 3.4
Rw

UW : kcal/hr.m2.
A : (m2)
CTLD :
RW : (hr.m2. /kcal)
RW

1 l 1 1
RW = +∑ + + 3.5
αi λ C αO

o i kcal/hr.m2.
: (kcal/hr.m. )
l : m
C kcal/hr.m2.
Rw UW A

Qw = K w × CTLD = K w × (TOA − TRA ) 3.6

25
 Qi = C p × G × (TOA − TRA )

CP : 0.24 kcal/kg.
G : kg/hr

Qi = K i × (TOA − TRA ) 3.8

QR 3.3 3.6
3.8

QR = Qg + QW + Qi
= ( K g + K w + K i ) × (TOA − TRA ) 3.9
= K R × (TOA − TRA )

26
 QgD
QD
CP
QL

dTRA
QL = C P × M ×
dt
(3.10)
dT
= C r × RA
dt

Cr u

u + QL = QR + QD (3.11)

(3.9) (3.10) (3.11)

dTRA
Q u + Cr × = K R × (TOA − TRA ) + QD
dt
dTRA K R 1 1
∴ = × (TOA − TRA ) + QD − u (3.12)
dt Cr Cr Cr

KR 1
a= ,b =
Cr Cr

T&RA = a(TOA − TRA ) + bQD − bu (3.13)

27
 TOA QD TOA
QD u (3.2) (3.13)

QD

TRA
1
u 1/Cr
s
Integrator
Gain

TOA
KR

Gain1

3.2

(3.13) Laplace

a b b
TRA ( s ) = TOA + QD − u (3.14)
s+a s+a s+a

3.14 3.3

28
 TO A a
s+a
function1

T(s)
b
QD
s+a

function2

b
u s+a
function3

3.3

3.3 PID
3.2 PID
PID (Proportional
Integeral Derivate Controller)

PID
e(t)

e(t ) = r (t ) − y (t ) (3.15)
de(t )
u (t ) = K P e(t ) + K I ∫0e(t )dt + K D
t
(3.16)
dt

KP
KI
KD

29
 E (s) = R(s) − Y (s)

1
U ( s) = ( K P + + K D s) E (s) 3.18
KI s

U (s) 1
GPID ( s ) = = KP + + KDs 3.19
E (s) KI s

KP
R(s) E(s)
U(s) Y(s)
KDs Plant

1/KIs

3.4 PID

30
 FPGA
3.16 Z

kIT z + 1
GI ( z ) = ( ) (3.18)
2 z −1

kD z −1
GD ( z ) = (3.19)
T z

kIT z + 1 kD z −1
D( z ) PID = k P + ( )+ ( ) (3.20)
2 z −1 T z

T PID 3.5

kP

e(kT)
KD
z −1 u( kT)
Tz

kIT z + 1
2 z −1

3.5 PID

31
 3.4

1 RTD IC AD590

ON/OFF

RTD PT-100 PT-100

3.4.1 RTD

RTD ( Resistance temperature detectors)

RTD

32
 200 ~ 700

RTD Pt

:
L
R=ρ
A

Pt-100

R(T ) = R(0)[1 + αT ]

33
3.6 Pt-100

34
 MATLAB

MATLAB/Simulink
3.2

PID
PWM
MATLAB /Simulink

4.1

35
 10m×5m×3m
5m×1m
185m2 200mm
3.2
4.1
4.1

TOA 28
Kg 19.75 kcal/hr
Kw 300 kcal/hr
TRA 24
Ki 20 kcal/hr
KR 339.75 kcal/hr
Cr 43.37 kcal/
u 2500 kcal/hr
QD 600 kcal/hr

4.2
3.2 3.2 ON/OFF
4.1

ON

OFF

ON/OFF

36
 QD

u TRA
1
ON/OFF 1/Cr
s

controler Integrator
Gain

TOA
KR

G ain1

4.1

MATLAB (4.2)
4.2 25 23
( 1 )
0.5 24.5 23.5
(4.3) 4.2

37
 1
28

26

24
temperature

22
ON
OFF
20

18

16
0 10 20 30 40 50 60
time(mim)

4.2 1
0.5
28

26

24
temperature

22
ON
OFF
20

18

16
0 10 20 30 40 50 60
time(mim)

4.3 0.5

38
4.3

4.4
PID PID

PID
4.5 (kP=0.25 kI=0.015625 kD=0.03125)

QD

u TRA
1
PID 1/Cr
s

PID controler Integrator

Gain

TOA
KR

Gain1

4.4 PID

158
78.26
1.2 0.5
MATLAB (4.6)
(4.6) PID

39
 4.6 4.5

PID controler
30

28

26
Temperature
24

22
Temperature

20 153%

18
78.26%
16

14

12

10
0 10 20 30 40 50 60
time(min)

4.5 PID

40
 P ID controler
30

28

26 Temperature

24

22
Temperature

20
120%
18

78.26%
16

14

12

10
0 10 20 30 40 50 60
time(min)

4.6 PID

4.4

0.6 0.6
PID 4.7

41
 P ID controler
28

26

Temperature
24

22
Temperature

20

18 120%

78.26%
16

14

12
0 10 20 30 40 50 60
time(min)

4.7 PID

4.8
80 75% , 24
± 0.035

42
 P ID controler
30

28

26 Temperature

24
Temperature

22

20

120%
18
80%

16

14 75%
60%
12
0 10 20 30 40 50 60
time(min)

4.8 PID

t=30 28
29 t=46 4.9
90
95 4.10

600kcal/hr 900kcal/hr 100 105

43
 PID controler
28

26
Temperature

24

22
Temperature

20

90%
18 80%

16

95%
14 75%
50%
12
0 20 40 60 80 100
time(min)

4.9
P ID controler
28

26
Temperature

24

22
Temperature

20 105%

18

100%
16

14

12
0 50 100 150 200
time(min)

4.10

44
4.5 PWM

( 2500 kcal/hr)

(PWM)
PWM

>
<
(4.11)
(4.12) PWM
FPGA

4.13 4.14 PWM

4.11 4.12 PWM

45
 120

100
80
amplitude

60

40
20

0
0 20 40 60 80 100 120
time(sec)

1
output signal

0.8

0.6
0.4

0.2

0
0 20 40 60 80 100 120
time(sec)

4.11 PWM ( )

150

100
amplitude

50

0
0 20 40 60 80 100 120
time(sec)

1
output signal

0.8

0.6
0.4

0.2

0
0 20 40 60 80 100 120
time(sec)

4.12 PWM

46
 120

100
80
amplitude

60

40
20

0
0 20 40 60 80 100 120
time(sec)

1
output signal

0.8

0.6
0.4

0.2

0
0 20 40 60 80 100 120
time(sec)

4.13 PWM

150

100
amplitude

50

0
0 20 40 60 80 100 120
time(sec)

1
output signal

0.8

0.6
0.4

0.2

0
0 20 40 60 80 100 120
time(sec)

4.14 PWM

47
 (1) PC
(2)
(3) Pt-100
(4) A/D
(5)
(6)
(7) FPGA
(8)
(5.1) (5.2)

PC

FPGA

A/D

5.1

48
 5.2

5.1 PC
PC VHDL
PC
FPGA

5.2

2500 Kcal/hr
220V 60Hz 3.9A 750W (5.3)
(5.4)

49
5.3

5.4

50
5.3 Pt-100
3.4 Pt-100 Pt-100

R4558
mV

0V~5V 5.6

5.4 A/D
FPGA
5.3 Pt-100
FPGA
FPGA
/ A/D converter
IC ADC0804
ADC0804 20 8 A/D
5.5 ADC0804 8
DB0~DB7 256
5.3 Pt-100 10 ~35.5
0.1 0.1
5.1 5.6
ADC0804
100KHz ~ 1460KHz RC ADC0804

51
 FPGA CLK ADC0804
CLK CLK

5.5 ADC080X IC

5.1 /

10 00000000

10.1 00000001

10.2 00000010

: :
: :
35.4 11111110

35.5 11111111

52
5.5

FPGA

5.4 A/D
8 FPGA
8
5.6 74193 8
S1 S2
S3 24

5.6 A/D
5.7 PCB 5.6
Pt-100
A/D AC/DC
FPGA (DC ± 5V)

5.6

3 IC 7447 3 5.8

53
 1 2 3 4

J4
1
2
3
D 4 D
5
6
7
VCC 8
9
10
11
12
U6 U7 13
R23 R22 R21 14 12 14 12 14
330 330 330 CLR CO CLR CO 15
5 13 5 13
UP BO UP BO 16
4 4
DOWN DOWN 17
11 3 11 3
LOAD QA LOAD QA 18
15 2 15 2
A QB A QB 19
1 6 1 6
B QC B QC 20
10 7 10 7
C QD C QD 21
9 9
D D 22
1

C 23 C
SW-UP 74193 74193
S3 S2 S1 VCC 24
2 1

VCC 25
26
RESET SW-DOWN 27
28
2

29
30
31
32
33
34
VCC 35
36
VCC 37
38
R4 R10 VCC 39

20
10K 100K R11 U5 ADC0804 40
100K 41
B 42 B
8

J2 7 18

VccREF
R7 U4A R18 Vin(-) lsbDB0 43
VCC 17
1 U4B DB1 44
1K 3 VCC 6 16
2 Vin(+) DB2 45
+ 1 5 15
Pt-100 C9 DB3 46
2 7 14
DB4 47
R5
100K
R8
10UF
RC4558
6

RC4558 20k
8
A-GND DB5
DB6
13
12
11
48
49 A/D
4

R15 msbDB7 50
1K 9
100K Vref/2
5
R13 V- INTR 50PIN
500 330 R16
R17 19 1
R9 10k R19 CLK-R CS D4
2
1K 10k RD LED
R6 4 3
CLK-IN WR
1K
C10
R12
+

R14
100K 100K
10uf Title
A A

Size Number Revision

A4
Date: 10-Jan-2000 Sheet of
File: C:\pcb_work\MyDesign1.ddb Drawn By:
1 2 3 4

5.6 A/D

A/D

5.7 A/D

54
 5.8

5.7 FPGA
FPGA LH070 FPGA
5.9 Xilinx FPGA
XC4005XL-PC84 Xilinx Foundation-
1.5 VHDL FPGA
LH070
LH070 PID

55
 5.9 LH070 FPGA

1
2 VHDL
Macro

3
4 FPGA
5.10

A. CLK
B.
C. BCD
D. PID

56
 E. PWM
F.
6

BCD

CLK

PID PWM

5.10 FPGA

5.7.1
FPGA 8M/500K/16K/490/15 Hz
OSC4 CLK

5.7.2

57
 TWOBCD 5.12
TURN X2 XS
XT

5.11

5.7.3 BCD
5.3 5.5
FPGA 8
BCD 12 8 4
BCD 5.10 macro BCD
5.12 11.5
X2 00001111 BCD 0001 0001 0101
35.5 11111111 BCD 0011 0101
0101

58
 5.12 BCD

5.7.4 PWM
4.4 PWM
0 1
VHDL 8
PWM
PWM
T 16 PWM

5.13 PWM
T 5.13_A T=0001 5.13_B T=0110
5.13_C T=1111 Q1
Q2 Q1 Q2 PWM Q1
Q2 Q1 Q2 T

59
 5.13_A T= 0001 PWM

5.13_B T= 0110 PWM

5.13_C T= 1111 PWM

5.7.5 PID
3.3 PID 3.19 PID
PID 5.14
VHDL
5.7.6
PT-100

60
 KP

Gain1
y(K)
KiT /2

E(K) Gain
1
z

KD/T

Gain2
1
z

1
5.14 PID

FPGA
8

5.15

5.15

5.8
5.7.3 FPGA PWM

61
 rectifier
inverter 5.16

Diode PWM
C M
rectifier inverter
1 1

FPGA

5.16

ON/OFF GTO Gate Turn

Off Thyristor Bipolar Power Transistor IGBT
Insulated Gate Bipolar Transister MOSFET Power Metal Oxide
Semicon Field Effect Transistor MOSFET
IRFP 450 VDSS=500V ID(cont)=14A RDS(on)=0.4 4
MOSFET
IRFP450
feed back diode MOSFET
MOSFET 5.17
5.18

62
 L
INDUCTOR

Q1 Q3
1
J1 J3
D1
1 1
J5
Q1 IRFP450 Q2 IRFP450
1
4 2 J6
2 C
+
CAPACITOR POL 1
220V
2
BRIDGE MOTOR
3

Q2 Q4
J2 J4

FPGA PWM Q2
1 1
Q1
IRFP450 IRFP450

5.17

5.18

FPGA PWM MOSFET

63
PWM MOSFET
5.19

5.19

64
 FPGA PWM

FPGA PID

6.1

5.7 PWM

110V 75W 110V

FPGA 6.1
6.1
T
FPGA
PWM
1111 rpm 48W 64

65
 T

W A
110V60Hz
6.1

6.1
(W) (A) rpm
110V60Hz 75 0.78 1425
0000 88 0.82 1470
0001 87 0.82 1463
0010 85 0.81 1441
FPGA 0011 83.5 0.8 1432
0100 82 0.79 1429
0101 81 0.77 1426
0110 78 0.72 1412
0111 73.5 0.7 1388
1000 68 0.7 1360
T
1001 68 0.68 1353
4
1010 63 0.67 1330
1011 61 0.67 1300
1100 60 0.66 1288
1101 56 0.62 1250
1110 50 0.61 1130
1111 48 0.6 1111

66
6.2
6.2.1
24 ± 0.3
28 220V 60Hz
6.2
23.7 24.3

± 0.5

--
28

26

24.3
24
23.7

22

20

18

16

14
ON
OFF
12
0 10 20 30 40 50 60
time(min)

6.2

67
6.2.2 FPGA
FPGA
24 (5.1)
6.3
± 0.1 30
2 24.5
33

28

26

24

22

20

18

16
0 10 20 30 40 50 60
time(min)

6.3 FPGA

68
7.1
FPGA

PWM
PID PWM PID
VHDL FPGA

FPGA

FPGA
Xilinx
Fundation-1.5

A/D
8 IC IC

69
7.2
1

2 PWM

4
4

70
[1] K.A. Kwiat and W.H. Debany Jr., “Modeling a versatile FPGA for
prototyping adaptive system ,” in Proc. Sixth IEEE International
Workshop on Rapid System Prototpying , pp. 174-180, 1995.
[2] D.S. Reay, T.C. Green, and B.W. Williams, “Field programmable
gate array implementation of a neural network accelerator,”
Colloquium on Hardware Implementation of Neural Networks and
Fuzzy Logic, No.061, pp. 2/1-2/3, Mar 1994.
[3] M. Cirstea, A. Dinu, M. McCormick, and D. Nicula, “A VHDL
success story: electric drive system using neural controller,” VHDL
International Users Forum Fall Workshop, pp. 118-122. 2000
[4] Parris, P. Christopher, Haggard, and L. Roger, “Architecture for a
high speed fuzzy logic inference engine in FPGAs,” in Proc. Annual
Southeastern on System Theory, pp. 179-182, Jun 1996.
[5] J.J. Blake, L.P. Maguire, T.M. McGinnity, and L.J. McDaid, “Using
Xilinx FPGAs to implement neural network and fuzzy systems,” in
Proc. IEE Colloquium on Neural and Fuzzy System: Design,
Hardware and Applications, No. 133, pp. 246-249, May 1997.
[6] S.-L. Jung, M.-Y. Chang, and J.-Y. Jyang, “Design and
implementation of an FPGA-based control IC for the single-phase
PWM inverter used in an UPS,” in Proc. 2nd International
Conference on Power Electronics and Drive Systems, Part 1, Vol. 1,
pp. 344-349, May 1997.
[7] B. Pamela and H. Blake, “Single-Chip Velocity Measurement
System for Incremental Optical Encoders,” IEEE Trans. Control

71
 Systema Technology , Vol. 5, NO. 6, November, 1997.
[8] G. Lienhart, R. Lay, K.H. Noffz, and R. Manner, “An FPGA-based
video compressor for H.263 compatible bitstreams,” Digest of
Technical Papers, ICCE. Int. conf., pp. 320-321, 2000.
[9] Dick and Chris, “Image processing on an FPGA based custom
computing platform,” in Proc. of the International Symposium on
Signal Processing and its Application, pp. 361-364, Aug 1996.
[10] A. Kim and M. Chang, “Designing a Java microprocessor core using
FPGA technology,” Computing and Control Engineering Journal,
Vol. 11, No. 3, pp. 135-141, 2000.
[11] L. Charles, H. Phillips, and N. Troy, Digital Control System Analysis
and Design, 3nd ed. , Prentice-Hall, New Jersey , 1995.
[12] Xilinx The Programmable Logic Data Book , Xilinx Inc. ,2000
[13] ” ” 2001
pp.750-756 2001
[14] “ ” 1994 2
pp.60-71
[15] “ ” 1994
2 pp.84-88
[16] XILINX FPGA
88
[17] VHDL
88
[18] VHDL
89

72
[19] VHDL 86
[20] VHDL McGraw-Hill 2000 7

[21] VHDL 88 9

[22] IC
88
[23] A/D 84
[24]
90
[25] CPLD 88
[26] 80
[27] “FPGA ”
90 6
[28] “ FPGA ”
90 6
[29] “ FPGA ”
90 6
[30] “ FPGA
” 89 7

[31] “ ”
89 7

73
[32] 86 6

74
FPGA
A. singphase.vhd

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_UNSIGNED.all;

ENTITY singphase IS

PORT
( CLK,CLRN : IN STD_LOGIC;
T : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
O1,O2 : OUT STD_LOGIC
);

END singphase;

ARCHITECTURE a OF singphase IS
SIGNAL S: STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL Q : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL F : STD_LOGIC;
BEGIN
UPDOWNCOUNTER :BLOCK
SIGNAL H : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL P : STD_LOGIC;
BEGIN

PROCESS (CLK,CLRN)
VARIABLE N :INTEGER RANGE 0 TO 6;
BEGIN
IF CLRN='0' THEN
Q<="0000000";
p<='1';
N:=0;

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 ELSE
IF (CLK'EVENT AND CLK = '1') THEN
IF N=0 THEN
P<='1';
H<=T;
Q<=Q+"11"+H;
N:=N+1;
ELSIF N=6 THEN
P<='0';
Q<=Q-"11"-H;
N:=N-1;
ELSIF P='1' THEN
Q<=Q+"11"+H;
N:=N+1;
ELSIF P='0' THEN
N:=N-1;
IF N=0 THEN
H<=T;
Q<="0000000";
ELSE
Q<=Q-"11"-H;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END BLOCK UPDOWNCOUNTER;

SINNUM :BLOCK
SIGNAL K: STD_LOGIC;
BEGIN
PROCESS (CLK,CLRN)
VARIABLE M: integer range 0 to 60;
BEGIN
IF (CLRN='0') THEN
M:=0;
F<='0';

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 K<='1';
ELSIF (CLK'EVENT AND CLK = '1') THEN
IF K='1' THEN
M:=M+1;
ELSIF K='0' THEN
M:=M-1;
END IF;
IF M=0 THEN
K<='1';
F<= NOT F;
ELSIF M=60 THEN
K<='0';
END IF;
IF M<3 THEN
S<="0000000";
ELSIF M<5 THEN
S<="0001101";
ELSIF M<7 THEN
S<="0010001";
ELSIF M<9 THEN
S<="0010111";
ELSIF M<11 THEN
S<="0011100";
ELSIF M<13 THEN
S<="0100010";
ELSIF M<15 THEN
S<="0101000";
ELSIF M<17 THEN
S<="0101100";
ELSIF M<19 THEN
S<="0110010";
ELSIF M<21 THEN
S<="0110111";
ELSIF M<23 THEN
S<="0111100";
ELSIF M<25 THEN
S<="1000001";

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 ELSIF M<27 THEN
S<="1000101";
ELSIF M<29 THEN
S<="1001010";
ELSIF M<31 THEN
S<="1001110";
ELSIF M<33 THEN
S<="1010001";
ELSIF M<35 THEN
S<="1010101";
ELSIF M<37 THEN
S<="1011001";
ELSIF M<39 THEN
S<="1011100";
ELSIF M<41 THEN
S<="1011111";
ELSIF M<43 THEN
S<="1100010";
ELSIF M<45 THEN
S<="1100100";
ELSIF M<47 THEN
S<="1100110";
ELSIF M<49 THEN
S<="1101000";
ELSIF M<51 THEN
S<="1101010";
ELSIF M<53 THEN
S<="1101011";
ELSE
S<="1101110";
END IF;
END IF;
END PROCESS;
END BLOCK SINNUM;

COMPARATOR : BLOCK
BEGIN

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PROCESS (CLK,CLRN)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF CLRN='0' THEN
O1<='1';
O2<='1';
ELSIF F<='0' THEN
O1<='1';
IF Q<S THEN
O2<='0';
ELSE
O2<='1';
END IF;
ELSIF F<='1' THEN
O2<='1';
IF Q<S THEN
O1<='0';
ELSE
O1<='1';
END IF;
END IF;
END IF;
END PROCESS;
END BLOCK COMPARATOR;
END a;

B. twobcd.vhd

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_UNSIGNED.all;
USE ieee.std_logic_ARITH.ALL;

ENTITY TWOBCD IS

79
 PORT
(
TURN : IN STD_LOGIC;
XS : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
XT : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
X2 : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);

END TWOBCD;

ARCHITECTURE a OF TWOBCD IS
SIGNAL AA :STD_LOGIC;
BEGIN
AA<=TURN;
X2<=XS WHEN AA='1' ELSE
XT ;

END A;

C. pingun.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_UNSIGNED.all;
USE ieee.std_logic_ARITH.ALL;

ENTITY PINGUN IS

PORT
( CLK,CLRN : IN STD_LOGIC;
X2 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
XBCD : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);

END PINGUN;

ARCHITECTURE a OF PINGUN IS

80
 SIGNAL Q0 : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL Q1 : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL Q2 : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL Q3 : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL Q4 : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL Q5 : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL Q6 : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL Q7 : STD_LOGIC_VECTOR(8 DOWNTO 0);
BEGIN
READ :BLOCK
BEGIN
PROCESS (CLK,CLRN)
VARIABLE A :INTEGER RANGE 0 TO 7;
BEGIN
IF CLRN='0' THEN
A:=0;
ELSIF (CLK'EVENT AND CLK = '1') THEN
IF A=0 THEN
Q0<='0'&X2;
ELSIF A=1 THEN
Q1<='0'&X2;
ELSIF A=2 THEN
Q2<='0'&X2;
ELSIF A=3 THEN
Q3<='0'&X2;
ELSIF A=4 THEN
Q4<='0'&X2;
ELSIF A=5 THEN
Q5<='0'&X2;
ELSIF A=6 THEN
Q6<='0'&X2;
ELSIF A=7 THEN
Q7<='0'&X2;
END IF;
A:=A+1;
END IF;
END PROCESS;

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END BLOCK READ;

DIV :BLOCK
SIGNAL QS1,QS2,QS3,QS4,QA1,QA2,QA3,QA4,QA5 : STD_LOGIC_VECTOR(8 DOWNTO
0);
SIGNAL A1,A2,A3,A4 : STD_LOGIC_VECTOR(8 DOWNTO 0);
BEGIN
PROCESS (CLK,CLRN)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
A1<=Q0+Q1;
A2<=Q2+Q3;
A3<=Q4+Q5;
A4<=Q6+Q7;
QS1<='0'&A1(8 DOWNTO 1);
QS2<='0'&A2(8 DOWNTO 1);
QS3<='0'&A3(8 DOWNTO 1);
QS4<='0'&A4(8 DOWNTO 1);
QA1<=QS1+QS2;
QA2<=QS3+QS4;
QA3<='0'&QA1(8 DOWNTO 1);
QA4<='0'&QA2(8 DOWNTO 1);
QA5<=QA3+QA4;
XBCD<=QA5(8 DOWNTO 1);
END IF;
END PROCESS;
END BLOCK DIV;
END A;

D. bcd.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_UNSIGNED.all;
USE ieee.std_logic_ARITH.ALL;

ENTITY bcd IS

82
 PORT
( CLK : IN STD_LOGIC;
X2 : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
XA : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
XBCD : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);

END BCD;

ARCHITECTURE a OF BCD IS
SIGNAL QQ,D : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
HUNDAED :BLOCK
BEGIN
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
D<=X2;
IF D>="11001000" THEN
XA<="11";
QQ<=X2-"11001000";
ELSIF D>="01100100" THEN
XA<="10";
QQ<=X2-"01100100";
ELSE XA<="01";
QQ<=D;
END IF;
END IF;
END PROCESS;
END BLOCK HUNDAED;

TEN :BLOCK
SIGNAL PP : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
PROCESS (CLK)
BEGIN

83
IF (CLK'EVENT AND CLK = '1') THEN
IF QQ>="01011010" THEN
XBCD(7 DOWNTO 4)<="1001";
PP<=QQ-"01011010";
ELSIF QQ>="01010000" THEN
XBCD(7 DOWNTO 4)<="1000";
PP<=QQ-"01010000";
ELSIF QQ>="01000110" THEN
XBCD(7 DOWNTO 4)<="0111";
PP<=QQ-"01000110";
ELSIF QQ>="00111100" THEN
XBCD(7 DOWNTO 4)<="0110";
PP<=QQ-"00111100";
ELSIF QQ>="00110010" THEN
XBCD(7 DOWNTO 4)<="0101";
PP<=QQ-"00110010";
ELSIF QQ>="00101000" THEN
XBCD(7 DOWNTO 4)<="0100";
PP<=QQ-"00101000";
ELSIF QQ>="00011110" THEN
XBCD(7 DOWNTO 4)<="0011";
PP<=QQ-"00011110";
ELSIF QQ>="00010100" THEN
XBCD(7 DOWNTO 4)<="0010";
PP<=QQ-"00010100";
ELSIF QQ>="00001010" THEN
XBCD(7 DOWNTO 4)<="0001";
PP<=QQ-"00001010";
ELSE XBCD(7 DOWNTO 4)<="0000";
PP<=QQ;
END IF;
XBCD(3 DOWNTO 0)<=PP(3 DOWNTO 0);
END IF;
END PROCESS;
END BLOCK TEN;
END A;

84