ĐẠI HỌC QUỐC GIA TP.

HỒ CHÍ MINH
ĐẠI HỌC BÁCH KHOA
NGÀNH KỸ THUẬT ĐIỆN TỬ

Chapter 3
Digital Design Using Verilog
PGS.TS. HOÀNG TRANG
Bộ môn Kỹ Thuật Điện Tử
hoangtrang@hcmut.edu.vn

1
 Cell Base Design Flow Review
Support Tools
Design flow Output
(Languages)

Specifications <file>.docx/xls/ppt

System Level G++ (C++ with

Flatform / Model
Design Sysem C class) Front
NG VI, NotePath++ End
RTL Design (Verilog/VHDL) <file>.v

NG Report file,
VCS/ModelSim,
RTL Verification wave form
etc(Verilog/ VHDL)
<file>.v (netlist),
Synthesis DC compiler <file>.sdf,
Reports
NG
Netlist Verification Formality Report file

DFT FastScan/Tmax/… Report file, Netlist Back

End
STA Report file, Netlist
Prime Time

Place&Route <file>.gds
ICC compiler
2
 Cell Base Design Flow Review
Support Tools
Design flow Output
(Languages)

Specifications <file>.docx/xls/ppt

System Level G++ (C++ with

Flatform / Model
Design Sysem C class) Front
VI, NotePath++ End
RTL Design (Verilog/VHDL) <file>.v
NG
NG Report file,
VCS/ModelSim,
RTL Verification wave form
etc(Verilog/ VHDL)
<file>.v (netlist),
Synthesis DC compiler <file>.sdf,
Reports
NG
Netlist Verification Formality Report file

DFT FastScan/Tmax/… Report file, Netlist Back

End
STA Report file, Netlist
Prime Time

Place&Route <file>.gds
ICC compiler
3
 Cell Base Design Flow Review
Design flow

Specifications

System Level
Design

NG
RTL Design

NG
RTL Verification Can simulate, Tools are not
but cannot enough excellent
Synthesis
synthesize to to understand
Netlist Verification Gate Level your writing

4
 Agenda
Introduction

Verilog language with different levels?

How to write Verilog code well to be able to

Synthesize to gate level?

5
 Introduction
Verilog, standardized as IEEE 1364, is a hardware
description language (HDL) used to model electronic systems.
It is most commonly used in the design and verification of
digital circuits at the register-transfer level of abstraction. It is
also used in the verification of analog circuits and mixed-signal
circuit.

Verilog was the first modern hardware description language

to be invented. It was created by Phil Moorby and Prabhu
Goel during the winter of 1983/1984

Versions: Verilog-95, Verilog 2001, Verilog 2005,

SystemVerilog

6
 Agenda
Introduction

Verilog language with different level?

How to write Verilog code well ?

7
 Behavior level
Verilog Language

Behavior Model RTL Gate Level Netlist

module sram_controller ( clk, rst_n,

Initial begin assign A = B&C; ready, fs, addr_recog, sram_addr);
while (1) begin
Red = 1; Yellow = 0; Green = 0; always@(posedge CLK or negedge PRESET) begin input [13:0] addr_recog;
# 30; if(!PRESET) begin output [13:0] sram_addr;
Red = 0; Yellow = 0; Green = 1; Q <= 0; input clk, rst_n, ready, fs;
# 27; end
Red = 0; Yellow = 1; Green = 0; else begin DFFSXL chip_ena_reg ( .D(vsr_ena_n)
#3; Q <= A; .CK(clk), .SN(rst_n), .Q(chip_ena) );
end end
end end XAND2X1 U4 ( .A(fs), .B(ready),
.Y(sram_oe_n) );

.................

SUCCESS

FAIL
8
 Behavior level
Verilog Language

Behavior Model RTL Gate Level Netlist

9
 Behavior level
Verilog Language

Behavior Model RTL Verify

How to model a behavior of traffic light system?

• Red  Green : 30 s
• Green  Yellow : 27s
• Yellow  Red :3s

10
Behavior level

• Red  Green : 30 s
• Green  Yellow : 27s
• Yellow  Red :3s

Initial begin
while (1) begin
Red = 1; Yellow = 0; Green = 0;
# 30;
Red = 0; Yellow = 0; Green = 1;
# 27;
Red = 0; Yellow = 1; Green = 0;
#3;
end
end

11
Behavior level

• Red  Green : 30 s
• Green  Yellow : 27s
• Yellow  Red :3s

Verificataion

12
 Behavior level

• Red  Green : 30 s
• Green  Yellow : 27s
• Yellow  Red :3s

Initial begin
while (1) begin
Can simulate, Red = 1; Yellow = 0; Green = 0;
# 30;
but cannot be Red = 0; Yellow = 0; Green = 1;
# 27;
synthesized to Red = 0; Yellow = 1; Green = 0;
Gate Level #3;
end
end

13
 Cell Base Design Flow Review
Design flow

Specifications

System Level
Design

NG
RTL Design

NG
RTL Verification Can simulate, Tools are not
but cannot enough excellent
Synthesis
synthesize to to understand
Netlist Verification Gate Level your writing

14
Cell Base Design Flow Review

Synthesize Report

Netlist

Verilog 15
 Writing Verilog code for what ?
Writing Verilog
Code for What ?

Behavior Model Synthesis to Gate

Verify
Level

Coding style Constrains Version

16
 How to write Verilog code well ?

Synthesized Verilog Introduce

Verilog Basic

17
 How to write Verilog code well ?

Synthesized Verilog Introduce

Verilog Basic

18
Synthesized Verilog Introduce Components

Components

Combination Sequential
components components

19
Synthesized Verilog Introduce
Components

Combination Sequential
components components

Comb1
DFF DFF

Comb 3
DFF

Comb 2
DFF
DFF

20
 Synthesized Verilog Introduce Prototype

assign/always@ always@

Comb1
DFF DFF

Comb 3
DFF

Comb 2
DFF
DFF

21
 Synthesized Verilog Introduce Thinking Flow

Specification
we have idea

How to write source code Verilog ?

22
 Synthesized Verilog Introduce Thinking Flow

Specification
we have idea

How to write source code Verilog ?

23
 How to write Verilog code well ?

Synthesized Verilog Introduce

Verilog Basic

24
 Verilog Basic Fundamentals

B
A

C B
A
C

25
 Verilog Basic Fundamentals

B assign A = (S == 1)?B:C;
A

C always@(S or B or C) begin
B if(S == 1) begin
A A <= B;
assign A = B&C; C end
else begin
always@(B or C) begin
A <= C;
A <= B&C;
end
end
end

always@(posedge CLK or negedge PRESET) begin

if(!PRESET) begin
Q <= 0;
end
else begin
Q <= D;
end
end
26
 VHDL Fundamentals

architecture rtl of mux is

B begin
A process (S, B, C) begin
if (S= '0') then
C B A <= C;
elsif (S = ‘1’) then
architecture rtl of AND_logic is A A <= B;
begin C end if;
A <= B and C;
end process;
end architecture;
end architecture;
architecture rtl of AND_logic is
begin
process (B, C) begin architecture rtl of dff_async_reset is
A <= B and C; begin
end process process (CLK, PRESET) begin
end architecture; if (PRESET= '0') then
q <= '0';
elsif (rising_edge(CLK)) then
q <= D;
end if;
end process;
end architecture;

27
 Verilog Basic Fundamentals

X[2] X[1] X[0] Y[1:0]

0 0 0 01
0 0 1 10
0 1 0 11
0 1 1 00
-------- --------- -------- 00

28
 Verilog Basic Fundamentals

always@(X) begin
X[2] X[1] X[0] Y[1:0]
end
0 0 0 01
0 0 1 10
0 1 0 11
0 1 1 00
-------- --------- -------- 00

29
 Verilog Basic Fundamentals

always@(X) begin
X[2] X[1] X[0] Y[1:0]
case (X)
0 0 0 01 endcase
0 0 1 10 end
0 1 0 11
0 1 1 00
-------- --------- -------- 00

30
 Verilog Basic Fundamentals

always@(X) begin
X[2] X[1] X[0] Y[1:0]
case (X)
0 0 0 01 3’b000: begin
0 0 1 10 end
3’b001: begin
0 1 0 11 end
0 1 1 00 3’b010: begin
-------- --------- -------- 00 end
default : begin
end
endcase
end

31
 Verilog Basic Fundamentals

always@(X) begin
X[2] X[1] X[0] Y[1:0]
case (X)
0 0 0 01 3’b000: begin
0 0 1 10 Y <= 2’b01;
end
0 1 0 11 3’b000: begin
0 1 1 00 Y <= 2’b10;
-------- --------- -------- 00 end
3’b000: begin
Y <= 2’b11;
end
default : begin
Y <= 2’b00;
end
endcase
end

32
 Verilog Basic Fundamentals

always@(X) begin
X[2] X[1] X[0] Y[1:0]
case (X)
0 0 0 01 3’b000: begin
0 0 1 10 Y <= 2’b01;
end
0 1 0 11 3’b001: begin
0 1 1 00 Y <= 2’b10;
-------- --------- -------- 00 end
3’b010: begin
Y <= 2’b11;
end
default : begin
Y <= 2’b00;
end
endcase
end

33
 Verilog Basic Fundamentals

always@(X) begin
X[2] X[1] X[0] Y[1:0]
if (X == 3’b000) begin
0 0 0 01 Y <= 2’b01;
0 0 1 10 end
else if (X == 3’b001) begin
0 1 0 11 Y <= 2’b10;
0 1 1 00 end
-------- --------- -------- 00 else if (X == 3’b010) begin
Y <= 2’b11;
end
else begin
Y <= 2’b00;
end
end

34
 Verilog Basic Fundamentals

example1

35
 Verilog Basic Fundamentals

example1 R
S Input

Output

Q Internal Signal
A

CLK

36
 Verilog Basic Fundamentals

example1 R
S Input

Output

Q Internal Signal
A

CLK

Should be “reg/wire”
data type

37
 Verilog Basic Fundamentals

example1 module example1 (CLK, R, S, A, Q);

S R
input CLK;
input R;
input S;
input A;
Q output Q
A reg Q;

wire D;

assign D = (S==0)?A:Q;

CLK
always@(posedge CLK or negedge R) begin
if(R == 0) begin
Q <= 0;
end
else begin
Q <= D;
end
end
endmodule 38
 Verilog Basic Fundamentals

example1 module example1 (CLK, R, S, A, Q);

S R
input CLK;
input R;
Why not declare the data type ?
input S;
input A;
Q output Q
A Why declare “reg”data type ?
reg Q;

wire D; Why declare “type”data type ?

assign D = (S==0)?A:Q;

CLK
always@(posedge CLK or negedge R) begin
if(R == 0) begin
Q <= 0;
end
else begin
Q <= D;
end
end
endmodule 39
 Verilog Basic Fundamentals

example1

S R

Q[2:0]
A [2:0]

CLK

40
 Verilog Basic Fundamentals

example1 module example1 (CLK, R, S, A, Q);

S R parameter DATA_WIDTH = 3;

input CLK;
input R;
input S;
input [DATA_WIDTH-1:0] A;
Q[2:0]
A [2:0] output [DATA_WIDTH-1:0] Q
reg [DATA_WIDTH-1:0] Q;

wire [2:0] D;

assign D = (S==0)?A:Q;

always@(posedge CLK or negedge R) begin

CLK if(R == 0) begin
Q <= 0;
end
else begin
Q <= D;
end
end

endmodule
41
 Verilog Basic Fundamentals

example1 module example1 (CLK, R, S, A, Q);

S R parameter DATA_WIDTH = 3;

input CLK;
input R;
input S;
input [DATA_WIDTH-1:0] A;
Q[2:0]
A [2:0] output [DATA_WIDTH-1:0] Q
reg [DATA_WIDTH-1:0] Q;

wire [2:0] D;

assign D = (S==0)?A:Q;

always@(posedge CLK or negedge R) begin

CLK if(R == 0) begin
Q <= 0;
end
else begin
Q <= D;
end
end

endmodule
42
 Verilog Basic Fundamentals

module example1 (CLK, R, S, A, Q);

parameter DATA_WIDTH = 3;

Module Declaration input CLK;

input R;
Parameter input S;
Declaration input [DATA_WIDTH-1:0] A;

output [DATA_WIDTH-1:0] Q
Input Declaration
reg [DATA_WIDTH-1:0] Q;

Output Declaration wire [2:0] D;

assign D = (S==0)?A:Q;
Internal signal
always@(posedge CLK or negedge R) begin
if(R == 0) begin
Combination logic Q <= 0;
end
Sequential logic else begin
Q <= D;
end
end

endmodule
43
 Verilog Basic Fundamentals

module example1 (CLK, R, S, A, Q);

parameter DATA_WIDTH = 3;

Module Declaration input CLK;

input R;
Parameter input S;
Declaration input [DATA_WIDTH-1:0] A;

output [DATA_WIDTH-1:0] Q
Input Declaration
reg [DATA_WIDTH-1:0] Q;

Output Declaration wire [2:0] D;

assign D = (S==0)?A:Q;
Internal signal
always@(posedge CLK or negedge R) begin
if(R == 0) begin
Combination logic Q <= 0;
end
Sequential logic else begin
Q <= D;
end
end

endmodule
44
 Module
Verilog Basic Declaration

module <module_name>(<input1>, <input_2>, <input_3>… <output_1>,.. <output_n>);

<module_name> should be same to file name

should be lower case characters

45
 Module
Verilog Basic Declaration

module <module_name>(<input1>, <input_2>, <input_3>… <output_1>,.. <output_n>);

 Example:
module traffic_light ( clk, rst_n, enable
, read_counter[2:0], yellow_counter[2:0], green_counter[2:0]
, red_light, yellow_light, green_light
);

Should not declare the size of signal

in the module declaration

46
 Module
Verilog Basic Declaration

module <module_name>(<input1>, <input_2>, <input_3>… <output_1>,.. <output_n>);

 Example:
module traffic_light ( clk, rst_n, enable
, read_counter, yellow_counter, green_counter
, red_light, yellow_light, green_light
);

Only name of signal should be declared

in the module declaration

47
 Module
Verilog Basic Declaration

module <module_name>(<input1>, <input_2>, <input_3>… <output_1>,.. <output_n>);

 Example:
module traffic_light ( clk, rst_n, enable
, read_counter, yellow_counter, green_counter
, red_light, yellow_light, green_light
);
• <module name> and <port_name> are separated by lower &
upper characters

• The <module name> and <port_name> should be used by

reminiscent words

• The first input should be <clock> port

• The second input should be <reset> port

• The output port should be declared after input ports

48
 Module
Verilog Basic Declaration

module <module_name>(<input1>, <input_2>, <input_3>… <output_1>,.. <output_n>);

module traffic_light ( clk, rst_n, enable Q3?

, read_counter, yellow_counter, green_counter New line & The
comma is first
, red_light, yellow_light, green_light
);
• <module name> and <port_name> are separated by lower &
upper characters Q1?

• The <module name> and <port_name> should be used by

reminiscent words Q2?

• The fist input should be <clock> port

• The second input should be <reset> port

• The output port should be declared after input ports

49
 Verilog Basic Character

• White space: Space, tab(\t), newline( \n) characters are ignored.

 The space characters are members of string

• Comment:
+ Line comment (//)
+ Block comment (/* */)
 Should not use the block comment

• Number: The constant number can be integer constant or real constant

 Should be clear the type of number

• String : Is enclosed by double quotes (“”)

 Example : “Hello World”

• Identifier: Use “$” character for identifiers.

These can be system functions or system variables
 Example: $time, $display

• Backslash (\): Use the define the escaped identifier

 Example: “\$ ” is understand as “$ ” string
The identifier should be end with white space 50
 Verilog Basic Name Rule

• Use enough character for name (5  16)

• Use the underscore “_” to separate the name by meaning (not use at the end)

• Not use the same character with different lower & upper cases (“aaa” and “AAA”)

• Do not mix the upper case and lower case (Dmac_Enable, Uart_Clock)

• Use reminiscent word for the name (dmac_enable, uart_tx)

• Use “_n” for the active low signal (dmac_rst_n, uart_rst_n)

• The clock should be start by “clk” character (clk_dmac, clk_uart)

• Do not use the name which is same with the keywords (vcc, vdd, clock, reset …)

• Use the upper cases for the parameter (parameter DATA_WIDTH = 32)

• Good example: clk_system, clk_sbi

rst_n_timer, rst_n_system
temp_01, temp_02
rd_ena, wr_ena
51
 Verilog Basic Key Words

 <NETTYPE>
wire, reg, wand, wor, supply0, supply1, tri, tri0, tri1, triand , trior, trireg

 <CAPACITOR_SIZE>
small, medium, large

 <STRENGTH0>
supply0, strong0, pull0, weak0, highz0

 <STRENGTH1>
supply1, strong1, pull1, weak1, highz1

 <CAPACITOR_SIZE>
small, medium, large

 <GATETYPE>
and, nor, pullup, tran, buf, not, rcmos, tranif0, bufif0, notif0, rnmos, tranif1, bufif1,
notif1 rpmos, xnor, cmos, or, rtran, xor, nand, pmos rtranif0, nmos, pulldown, rtranif1

52
 System
Verilog Basic Function/Variable

$display - Print to screen a line followed by an automatic newline.

$write - Write to screen a line without the newline.
$swrite - Print to variable a line without the newline.
$sscanf - Read from variable a format-specified string. (*Verilog-2001)
$fopen - Open a handle to a file (read or write)
$fdisplay - Write to file a line followed by an automatic newline.
$fwrite - Write to file a line without the newline.
$fscanf - Read from file a format-specified string. (*Verilog-2001)
$fclose - Close and release an open file handle.
$readmemh - Read hex file content into a memory array.
$readmemb - Read binary file content into a memory array.
$monitor - Print out all the listed variables when any change value.
$time - Value of current simulation time.
$dumpfile - Declare the VCD format output file name.
$dumpvars - Turn on and dump the variables.
$dumpports - Turn on and dump the variables in Extended-VCD format.
$random - Return a random value.

The system functions/variables are used to simulate

 These are not synthesized
53
 Verilog Basic Fundamentals

module example1 (CLK, R, S, A, Q);

parameter DATA_WIDTH = 3;

Module Declaration input CLK;

input R;
Parameter input S;
Declaration input [DATA_WIDTH-1:0] A;

output [DATA_WIDTH-1:0] Q
Input Declaration
reg [DATA_WIDTH-1:0] Q;

Output Declaration wire [2:0] D;

assign D = (S==0)?A:Q;
Internal signal
always@(posedge CLK or negedge R) begin
if(R == 0) begin
Combination logic Q <= 0;
end
Sequential logic else begin
Q <= D;
end
end

endmodule
54
 Verilog Basic Parameter

parameter <PARAMETER_NAME> = <value>;

parameter DATA_WIDTH = 3;

• Valid only in the module in which is declared

• Use for the bit/bus size, cycle, address, state name …

• How to define a parameter ? Q4?

• How to define a parameter outside of the module? Q5?
• How to separate between “define ” and “parameter”? Q6?

55
 Verilog Basic Parameter

parameter <PARAMETER_NAME> = <value>;

parameter DATA_WIDTH = 3;
• How to define a parameter ? Q4?
parameter DATA_WIDTH = 32;
Example code parameter INITIAL = 2’b00;
parameter START = 2’b01;
parameter BUS_ADDRESS = 8;
…….….
reg [DATA_WIDTH-1:0] pci_data;
………..
assign pci_address = data[BUS_ADDRESS-1:0];
………..
INITIAL: begin
if(pci_ena == 1) begin
state <= START;
end
else begin
state <= INITIAL;
end
end 56
 Verilog Basic Parameter

parameter <PARAMETER_NAME> = <value>;

parameter DATA_WIDTH = 3;
• How to define a parameter outside of the module? Q5?

module LEVER_A(….); module LEVER_B(….);

parameter WIDTH = 8; parameter WIDTH = 9;
….. …..
reg [WIDTH-1:0] level_a_temp; reg [WIDTH-1:0] level_b_temp;

8 9
The values of “WIDTH” are different in
two independent modules 57
 Verilog Basic Parameter

parameter <PARAMETER_NAME> = <value>;

parameter DATA_WIDTH = 3;
• How to define a parameter outside of the module? Q5?

module LEVER_A(….);
parameter WIDTH = 8;
…..
reg [WIDTH-1:0] level_a_temp;
……
LEVEL_B inst_01 (…);
module LEVER_B(….);
parameter WIDTH = 9;
…..
reg [WIDTH-1:0] level_b_temp;

The values of “WIDTH” are different in the instance module

58
 Verilog Basic Parameter

parameter <PARAMETER_NAME> = <value>;

parameter DATA_WIDTH = 3;
• How to define a parameter outside of the module? Q5?

module LEVER_A(….); The value of “WIDTH” in the

defparam inst_01.WIDTH = 8;
parameter WIDTH = 8; LEVEL_B instance is redefined
to 8
…..
reg [WIDTH-1:0] level_a_temp;
……
LEVEL_B inst_01 (…); module LEVER_B(….);
parameter WIDTH = 9;
…..
reg [WIDTH-1:0] level_b_temp;

59
 Verilog Basic Parameter

parameter <PARAMETER_NAME> = <value>;

parameter DATA_WIDTH = 3;
• How to define a parameter outside of the module? Q5?

module LEVER_A(….); The value of “WIDTH” in the

defparam inst_01.WIDTH = 8;
parameter WIDTH = 8;
Inst_01 of LEVEL_B module is
redefined to 8 but it is still 9 in
….. The inst_02 of LEVEL_B module
reg [WIDTH-1:0] level_a_temp;
……
LEVEL_B inst_01 (…); module LEVER_B(….);
LEVEL_B inst_02 (…); parameter WIDTH = 9;
…..
reg [WIDTH-1:0] level_b_temp;

60
 Verilog Basic Parameter

parameter <PARAMETER_NAME> = <value>;

parameter DATA_WIDTH = 3;
• How to define a parameter outside of the module? Q5?

module LEVER_A(….); module LEVER_B(….);

parameter WIDTH = 8; parameter WIDTH = 8;
….. …..
reg [WIDTH-1:0] level_a_temp; reg [WIDTH-1:0] level_b_temp;

8 8
If using same parameter, the same parameters can list
in the parameter file 61
 Verilog Basic Parameter

parameter <PARAMETER_NAME> = <value>;

parameter DATA_WIDTH = 3;
• How to define a parameter outside of the module? Q5?
Parameter_dev.v
module LEVER_A(….); parameter WIDTH = 8;
`include “parameter_def.v” parameter ADRESS = 32;
….. …
reg [WIDTH-1:0] level_a_temp;

If using same parameters, these can be declared in the

parameter file
 The “parameter” is LOCAL

62
 Verilog Basic Parameter

parameter <PARAMETER_NAME> = <value>;

parameter DATA_WIDTH = 3;
• How to differentiate “define ” and “parameter”? Q6?
module A(…); module A(….);
`define ALW_PRT always@*begin …
… ….
ALW_PRT always@*begin
….. …..

Use “define” to replace a string/character …

63
 Verilog Basic Parameter

parameter <PARAMETER_NAME> = <value>;

parameter DATA_WIDTH = 3;
• How to differentiate “define ” and “parameter”? Q6?
module A (…);
`define TEMP_ONE 3’b111
…..
endmodule

module B (…); The “TEMP_ONE” is updated

`define TEMP_ONE 3’b110
….
after this code line
endmodule  Same as “macro” concept
in C++

 The “define” is GLOBAL

64
 Verilog Basic Fundamentals

module example1 (CLK, R, S, A, Q);

parameter DATA_WIDTH = 3;

Module Declaration input CLK;

input R;
Parameter input S;
Declaration input [DATA_WIDTH-1:0] A;

output [DATA_WIDTH-1:0] Q
Input Declaration
reg [DATA_WIDTH-1:0] Q;

Output Declaration wire [2:0] D;

assign D = (S==0)?A:Q;
Internal signal
always@(posedge CLK or negedge R) begin
if(R == 0) begin
Combination logic Q <= 0;
end
Sequential logic else begin
Q <= D;
end
end

endmodule
65
 Verilog Basic Input Declaration

input <[side of signal]> <input name> ;

Input [7:0] data_01, data_02;
input clk, rst_n;
wire clk, rst_n;
wire [7:0] data_01, data_02;

• Should declare the clk signal and reset signal firstly

• Should not declare many input signals in the same lines
• The default type of input is “wire”
 Should not declared “wire” data type

66
 Verilog Basic Input Declaration

input <[side of signal]> <input name> ;

input [7:0] data_01, data_02;

input clk, rst_n;
wire clk, rst_n;
wire [7:0] data_01, data_02;
correct  Should not declared “wire” data type for input
input clk;
input rst_n
input [7:0] data_01;
input [7:0] data_02;

67
 Verilog Basic Fundamentals

module example1 (CLK, R, S, A, Q);

parameter DATA_WIDTH = 3;

Module Declaration input CLK;

input R;
Parameter input S;
Declaration input [DATA_WIDTH-1:0] A;

output [DATA_WIDTH-1:0] Q
Input Declaration
reg [DATA_WIDTH-1:0] Q;

Output Declaration wire [2:0] D;

assign D = (S==0)?A:Q;
Internal signal
always@(posedge CLK or negedge R) begin
if(R == 0) begin
Combination logic Q <= 0;
end
Sequential logic else begin
Q <= D;
end
end

endmodule
68
 Verilog Basic Input Declaration

output<[side of signal]> <input name> ;

output [4:0] data_out;

wire[4:0] data_out
correct  Should not declared “wire” data type

output [4:0] data_out;

• Question: When decalaring “reg” type to output ports ?

 “reg” type is used whenever the signal is assigned in
“always” prototype

69
 Verilog Basic Fundamentals

module example1 (CLK, R, S, A, Q);

parameter DATA_WIDTH = 3;

Module Declaration input CLK;

input R;
Parameter input S;
Declaration input [DATA_WIDTH-1:0] A;

output [DATA_WIDTH-1:0] Q
Input Declaration
reg [DATA_WIDTH-1:0] Q;

Output Declaration wire [2:0] D;

assign D = (S==0)?A:Q;
Internal signal
always@(posedge CLK or negedge R) begin
if(R == 0) begin
Combination logic Q <= 0;
end
Sequential logic else begin
Q <= D;
end
end

endmodule
70
 Verilog Basic Internal Signal

wire<[side of signal]> <input name> ;

reg <[side of signal]> <input name> ;

reg [4:0] out_multiplier;

wire[4:0] out_adder;

• Question: When declaring “reg/type” type to internal

nets ?
 “reg” type is used whenever the output port is
assigned in “always” prototype.
 “wire” type is used whenever the output port is
assigned in “assign” prototype.

71
 Verilog Basic Main Structures

module example1 (CLK, R, S, A, Q);

parameter DATA_WIDTH = 3;

Module Declaration input CLK;

input R;
Parameter input S;
Declaration input [DATA_WIDTH-1:0] A;

output [DATA_WIDTH-1:0] Q
Input Declaration
reg [DATA_WIDTH-1:0] Q;

Output Declaration wire [2:0] D;

assign D = (S==0)?A:Q;
Internal signal
always@(posedge CLK or negedge R) begin
if(R == 0) begin
Combination logic Q <= 0;
end
Sequential logic else begin
Q <= D;
end
end

endmodule
72
Verilog Basic Rules

Is Same?

73
Verilog Basic Number

Decimal number 35
8’d35 //10*3+5
Octal number 8’o043 //64*0+8*4+3
Hex number 8’h23 //16*2+3
Binary number 8’b0010_0011 //Should use

Real number 35.

.35e2

Bit width Base number Value

4’sb1001 : Sized bit is 1  negative number

Size format Signed bit

74
 Verilog & Techniques Main Structures

Logic vs. Arithmetic

Synchronous Reset vs. Asynchronous Reset

None-Blocking vs. Blocking

Use enough cases towards Case/If

Limitation of Hierarchies

How many levels when using Case/If

How to connect many modules

75
 Logic vs. Arithmetic

wire [2:0] a;
wire [2:0] b;
wire [2:0] c1; //Test logic
wire [2:0] c2; //test arithmetic

assign c1 = a && b; // AND LOGIC

assign c2 = a & b; // AND BIT
 Is c1 and c2 similarly when a = 3’b101 and b = 3’b110

76
 Logic vs. Arithmetic

wire [2:0] a;
wire [2:0] b;
wire [2:0] c1; //Test logic
wire [2:0] c2; //test arithmetic

assign c1 = a && b; // AND LOGIC

assign c2 = a & b; // AND BIT
a = 3’b101 and b = 3’b110
Result : c1 = 3’b001; // Ignore the c1[2] and c1[1]; c1[0] is 1
because a != 0 and b != 0
c2 = 3’b100; // c2[2] = a[2] && b[2]; …; a[0] && b[0];

77
 Logic vs. Arithmetic

wire [2:0] a;
wire [1:0] b; // b is only two bits
wire [2:0] c1; //Test logic
wire [2:0] c2; //test arithmetic

assign c1 = a && b; // AND LOGIC

assign c2 = a & b; // AND BIT
a = 3’b101 and b = 2’b10
Result : c1 = 3’b001; // Ignore the c1[2] and c1[1]; c1[0] is 1
because a != 0 and b != 0
c2 = 3’bX00; // c2[2] is ignored; c2[1] = a[1] && b[1];
c2[0] = a[0] && b[0];
78
Logic vs. Arithmetic

79
 Synchronous Reset vs. Asynchronous Reset

Asynchronous Synchronous
• Synchronous reset signal is similar to other signal as S,
D or Q
• Asynchronous reset signal is special signal as CLK Q7?

80
 Synchronous Reset vs. Asynchronous Reset

Synchronous
Asynchronous
always@(posedge CLK or negedge PRESET) begin assign D = S & PRESET;
if(PRESET == 0) begin
Q <= 0; always@(posedge CLK) begin
end Q <= D;
else begin end
Q <= D;
end
end

81
Asynchronous Synchronous
always@(posedge CLK or negedge PRESET) begin
if(PRESET == 0) begin assign D = S & PRESET;
Q <= 0;
end always@(posedge CLK) begin
else begin Q <= D;
Q <= D; end
end
end
D <= S and PRESET;
process (CLK, PRESET) begin process (CLK) begin
if (PRESET = '0') then if (PRESET = '0') then
Q <= '0'; Q <= '0';
elsif (rising_edge(CLK)) then elsif (rising_edge(CLK)) then
Q <= D; Q <= D;
end if; end if;
end process; end process;
 Blocking vs. Non-Bloking
Non-Blocking : Only apply to ‘always’ prototype (<=)
Blocking : Apply for both “assign” and “always” prototype(=)

assign D = S & PRESET; // Blocking assignment

always@(posedge CLK) begin

Q <= D; // Non- Blocking assignment
end
No error,
Same function,
Same Hardware
always@(posedge CLK) begin  ??? Difference
Q = D; // Blocking assignment
end

83
 Blocking vs. Non-Bloking
Non-Blocking : Only apply to ‘always’ prototype (<=)
Blocking : Apply for both “assign” and “always” prototype(<=)
always@(posedge CLK) begin
B <= A; // Non-Blocking assignment
C <= B;
D <= C;
end

always@(posedge CLK) begin

B = A; // Blocking assignment
C = B;
D = C;
end

84
 Blocking vs. Non-Bloking

always@(posedge CLK) begin // Non-Blocking assignment

B <= A;
C <= B;
D <= C;
end

always@(posedge CLK) begin // Blocking assignment

B = A;
C = B;
D = C;
end

85
 Use K-Map to optimize function Fundamentals

X[2] X[1] X[0] Y[1] Y[0]

0 0 0 0 1
0 0 1 1 0
0 1 0 1 1
0 1 1 0 0
-------- --------- -------- 0 0 K-Map
 Do not care how
many cases

Y[1] = (!X[2] && X[0]) | (!X[2] && X[1])

Y[0] = !X[2] && (!X[0])

86
 Use enough cases Fundamentals

always@(X) begin
X[2] X[1] X[0] Y[1:0]
if (X == 3’b000) begin
0 0 0 01 Y <= 2’b01;
0 0 1 10 end
else if (X == 3’b001) begin
0 1 0 11 Y <= 2’b10;
0 1 1 00 end
-------- --------- -------- 00 else if (X == 3’b010) begin
Y <= 2’b11;
end
else begin
Y <= 2’b00;
end
end

‘else’ is for other cases to cover all cases of X[2:0]

87
 Use enough cases Fundamentals

always@(X) begin
X[2] X[1] X[0] Y[1:0]
case (X)
0 0 0 01 3’b000: begin
0 0 1 10 Y <= 2’b01;
end
0 1 0 11 3’b001: begin
0 1 1 00 Y <= 2’b10;
-------- --------- -------- 00 end
3’b010: begin
Y <= 2’b11;
end
default : begin
Y <= 2’b00;
end
endcase
end
‘default’ is for other cases to cover all cases of X[2:0]

88
 Use enough cases Fundamentals

always@(X) begin
case (X)
3’b000: begin
Y <= 2’b01;
end
3’b001: begin
Y <= 2’b10;
assign Y[1] = (!X[2] && X[0]) | (!X[2] && X[1])
assign Y[0] = !X[2] && (!X[0])
VS. end
3’b010: begin
Y <= 2’b11;
end
default : begin
Y <= 2’b00;
end
endcase
end

89
 Limitation of hierarchies Fundamentals

always@(X) begin
case (X) // Level 1 of case
3’b000: begin
case (Z) // Level 2 of case
3’b000: begin
Y <= 2’b01; // How many levels ?
4 space bar end
after ‘begin’ …………..
endcase
end Maximum three levels are accepted
………….. + If
default : begin + Case
Y <= 2’b00; + If & Case together
end
endcase
end

90
 Use “always” Fundamentals

always( S or A or D) begin
if(S == 1’b0) begin
D = A;
end
else
D = B;
end
end

always@(posedge CLK or negedge R) begin

if(R == 0) begin
Q <= 0;
end
else begin
Q <= D;
end
end

always@(posedge CLK or negedge R) begin

if(R == 0) begin Should not use ‘if’/’case’ in
Q <= 0;
end ‘always’ if it is too complicated
else if (S == 1’b0) begin
Q <= A;
end
else
Q <= B;
end
end
91
 Connect modules Fundamentals

Top level
module second level
third level
module
module

Top level second level

module top
module com
module seq

92
Connect modules Fundamentals

Top level second level module seq (CLK, R, D, Q);

input CLK;
module top input R;
input D;
module com output Q;
reg Q;
module seq always@(posedge CLK or negedge R) begin
if(R == 1’b0) begin
Q <= 0;
end
else begin
Q <= D;
end
end

endmodule
module com (A, B, S, O);
input A;
input B;
input S;
output O;
wire O;
assign O = (S==1’b0)?A:B;
endmodule

93
Connect modules Fundamentals

Top level second level module seq (CLK, R, D, Q);

………….
module top endmodule

module com
module seq module top (CLK, R, A, B, S, Q);

input CLK;
X input R;
input A;
input B;
input S;

output Q;
wire Q;

module com (A, B, S, O); wire X;

………….. // Call module com named ‘com_01’
endmodule com com_01 ( .A(A), B(B), .S(S), .O(X) );

// Call module seq named : ‘seq_01’

seq seq_01 ( .CLK(CLK), .R(R), .D(X), .Q(Q) );

endmodule

94
Connect modules Fundamentals

module seq (CLK, R, D, Q);

………….
endmodule

module top (CLK, R, A, B, S, Q);

input CLK;
X input R;
input A;
input B;
input S;

output Q;
wire Q;

module com (A, B, S, O); wire X;

………….. // Call module com named ‘com_01’
endmodule com com_01 ( .A(A), B(B), .S(S), .O(X) );

// Call module seq named : ‘seq_01’

seq seq_01 ( .CLK(CLK), .R(R), .D(X), .Q(Q) );

endmodule

95
Connect modules Fundamentals

module seq (CLK, R, D, Q);

………….
endmodule

module top (CLK, R, A, B, S, Q);

input CLK;
X input R;
input A; Second level
input B; Top level
input S;

output Q;
wire Q;

module com (A, B, S, O); wire X;

………….. // Call module com named ‘com_01’
endmodule com com_01 ( .A(A), .B(B), .S(S), .O(X) );

// Call module seq named : ‘seq_01’

seq seq_01 ( .CLK(CLK), .R(R), .D(X), .Q(Q) );

endmodule

96
Connect modules Fundamentals

module seq (CLK, R, D, Q);

………….
endmodule

module top (CLK, R, A, B, S, Q);

input CLK;
X input R;
input A;
input B;
input S;

output Q; Declare wire due to

wire Q;
connection instead of
wire X; from “always”
module com (A, B, S, O);
………….. // Call module com named ‘com_01’
endmodule com com_01 ( .A(A), .B(B), .S(S), .O(X) );

// Call module seq named : ‘seq_01’

seq seq_01 ( .CLK(CLK), .R(R), .D(X), .Q(Q) );

endmodule

97
 Connect modules Fundamentals

module top (CLK, R, A, B, S, Q); module top (CLK, R, A, B, S, Q);

input CLK; input CLK;

input R; input R;
input A; input A;
input B; input B;
input S; input S;

output Q; output Q;
wire Q; wire Q;

wire X; wire X;
// Call module com named ‘com_01’ // Call module com named ‘com_01’
com com_01 ( .A(A), .B(B), .S(S), .O(X) ); com com_01 ( A, B, S, X);

// Call module seq named : ‘seq_01’ // Call module seq named : ‘seq_01’
seq seq_01 ( .CLK(CLK), .R(R), .D(X), .Q(Q) ); seq seq_01 (CLK, R, X, Q);

endmodule endmodule

Name Assignment Order Assignment

98
 Gate Level Netlist
Verilog Language

Behavior Model RTL Gate Level Netlist

+ Use any things, but + Strict Rules + Declare gate level

not commit syntax + Only use simple netlist in detail
error structures + Have other kind of
+ Do not use ‘for, writing Verilog called
while,…’ of complex Verilog Primitives
structures

99
 Gate Level Netlist
Verilog: Primitives Format

primitive multiplexer(mux, control, dataA, dataB )

; Verilog : Gate Level
output mux ;
input control, dataA, dataB ;
table
010:1;
011:1;
01x:1;
000:0;
001:0;
00x:0;
101:1;
111:1;
1x1:1;
100:0;
110:0;
1x0:0;
x00:0;
x11:1;
endtable
endprimitive

100
Q&A

101