Digital Design

With an Introduction to the Verilog HDL, VHDL, and

SystemVerilog
6th Edition

Chapter 05
Synchronous Sequential Logic

Copyright © 2018, 2013, 2007 by Pearson Education, Inc.,

 2

Synchronous Sequential Logic

Part I

Copyright © 2018, 2013, 2007 by Pearson Education, Inc.,

 Sequential Circuits Model

inputs outputs
Combinational
Circuit

current next
state state
Memory
Elements

current state is a function of past inputs and initial state

3
 Classification
Two types of sequential circuits
1. Synchronous
• The state of the memory elements are updated with the
arrival of each pulse
• Synchronization is usually achieved through the use of a
common clock

2. Asynchronous
• No clock
• behavior of an asynchronous sequential circuits depends
upon the input signals at any instant of time and the order
in which the inputs change.

4
 Clocked Sequential Circuits
• Memory elements are flip-flops which are logic
devices, each of which is capable of storing one
bit of information.

inputs outputs
Combinational
Circuit

current next
state state
Flip-Flops
clock
5
 Clocked Sequential Circuits
• The outputs of a clocked sequential circuit can
come from the combinational circuit, from the
outputs of the flip-flops or both.
• The state of the flip-flops can change only
during a clock pulse transition
– i.e. low-to-high and high-to-low
– clock edge
• When the clock maintains its value, the flip-flop
output does not change
• The transition from one state to the next occurs
at the clock edge.
6
 Latches
• The most basic types of memory elements
are latches.
• A latch is a memory device that can
maintain a binary state.
• Latches are, in fact, asynchronous devices
and they usually do not require a clock to
operate.

7
 SR-Latch
• made of cross-coupled NOR (or NAND) gates
R
Q

Q’
S

S R Q Q’
1 0 1 0
0 0 1 0
0 1 0 1
0 0 0 1
1 1 0 0 Undefined 8
 SR-Latches with NAND Gates
S
Q

Q’
R
Also known as S’R’-latch
S R Q Q’
1 0 0 1
1 1 0 1 After S = 1, R = 0
0 1 1 0
1 1 1 0 After S = 0, R = 1
0 0 1 1 Undefined
9
 SR-Latch with Control Input
• Control inputs allow the changes at S and R to change the
state of the latch.
S
Q

Q’
R

C S R Q Q’
0 X X No change
1 0 0 No change
1 0 1 Q = 0 Reset state
1 1 0 Q = 1 Set state
1 1 1 Indeterminate 10
 D-Latch
• SR latches are seldom used in practice because
the indeterminate state may cause instability
• Remedy: D-latches

D S
Q

R Q’

This circuit guarantees that the inputs to the S’R’-latch

is always complement of each other when C = 1. 11
 D-Latch as a Storage Unit
• D–latches can be used as temporary storage
• The input of D-latch is transferred to the Q
output when C = 1
• When C = 0 the binary information is retained.

12
Graphic symbols for latches.

Copyright © 2018, 2013, 2007 by Pearson Education, Inc.,

 Need for Flip-Flops
• Outputs may keep changing so long as C = 1

inputs outputs
Combinational
Circuit

current next
state state
Latches
C
14
 Need for Flip-Flops
– The states of the memory elements must change
synchronously
– memory elements should respond to the changes in
input at certain points in time.
– This is the very characteristics of synchronous
circuits.
– To this end, we use flip-flops that change states
during a signal transition of control input (clock)

15
Clock response in flip-flop.

Copyright © 2018, 2013, 2007 by Pearson Education, Inc.,

 Edge-Triggered D Flip-Flop
• An edge-triggered D flip-flop can be constructed
using two D latches
Y
D D Q D Q Q
D latch D latch
(master) (slave)
C C

clk’
clk Y=D
clk Y does not change
clk
Q=Y=D
D
clk’
Y
Negative edge-triggered
Q
D flip-flop 17
Positive Edge-Triggered D Flip-Flop
Y
D D Q D Q Q
D latch D latch
(master) (slave)
clk’ C C

clk
clk
Y= D
clk’ Y does not change

Q=Y=D
clk

18
 Symbols for D Flip-Flops

D Q
Positive edge-triggered
D FF
D Flip-Flop
clk C

D Q
Negative edge-triggered
D FF
D Flip-Flop
clk C

19
 D Flip-Flop
D Q
Positive edge-triggered
D FF
D Flip-Flop
clk C

• Characteristic equation
– Q(t+1) = D
D Q(t+1)
0 0
1 1

Characteristic Table 20
 Other Flip-Flops
• D flip-flop is the most common
– since it requires the fewest number of gates to
construct.
• Two other widely used flip-flops
– JK flip-flops
– T flip-flops
• JK flip-flops
– Three FF operations
1. Set
2. Reset
3. Complement
21
JK flip-flop.

Copyright © 2018, 2013, 2007 by Pearson Education, Inc.,

 JK Flip-Flops
J K Q(t+1) next state
J Q
0 0 Q(t) no change
C
0 1 0 Reset
K
1 0 1 Set
1 1 Q’(t) Complement

Characteristic Table

• Characteristic equation
– Q(t+1) = JQ’(t) + K’Q(t)

23
 T (Toggle) Flip-Flop
• Complementing flip-flop

T Q(t+1) next state

T Q
0 Q(t) no change
C 1 Q’(t) Complement
Characteristic Table
• Characteristic equation
– Q(t+1) =

T J Q
T
D Q

C C
K
24
 Table 5.1
Flip-Flop Characteristic Tables.

Copyright © 2018, 2013, 2007 by Pearson Education, Inc.,

 Characteristic Equations
• The logical properties of a flip-flop can be
expressed algebraically using characteristic
equations
• D flip-flop
– Q(t+1) =
• JK flip-flop
– Q(t+1) =
• T flip-flop
– Q(t+1) =

26
 Asynchronous Inputs of Flip-Flops
• They are used to force the flip-flop to a
particular state independent of clock
– “Preset” (direct set) set FF state to 1
– “Clear” (direct reset) set FF state to 0
• They are especially useful at startup.
– In digital circuits when the power is turned on, the
state of flip-flops are unknown.
– Asynchronous inputs are used to bring all flip-flops to
a known “starting” state prior to clock operation.

27
 Asynchronous Inputs
data D Q clk
C
D
R

reset Q

reset

reset C D Q Q’

1 X X 0 1 Starting State

0  0 0 1

0  1 1 0
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