Unit 3

Serial Peripheral
Interface
• What is it?

• Basic SPI

• Capabilitie
s
Serial Peripheral
• Protoco Interface
http://upload.wikimedia.org/wikipedia/commons/thu

l mb/e/ed/
SPI_single_slave.svg/350px-SPI_single_slave.svg.png

• Pros and
Cons

• Uses

2
What is
SPI?
• Serial bus protocol
• Fast, easy to use, and
simple
• Very widely used
• Not “standardized”

3
SPI
Basics
• A 4-wire communications bus
• Typically communicate across short
distances
• Supports
– Single master
– Multiple slaves
• Synchronized
– Communications are “clocked”

4
SPI
Capabilities
• Always full-duplex
– Communicates in both directions simultaneously
– Transmitted (or received) data may not be
meaningful
• Multiple Mbps transmission
speeds
– 0-50 MHz clock speeds not
uncommon
• Transfer data in 4 to 16 bit
characters
• Supports multiple slaves

5
SPI bus
wiring

• Bus wires
– Master-Out, Slave-In (MOSI)
– Master-In, Slave-Out (MISO)
– System Clock (SCLK)
– Slave Select/Chip Select (SS1#, …, SS#n or CS1,
…, CSn)
• Master asserts slave/chip select line
• Master generates clock signal
• Shift registers shift data in and out

6
SPI signal
functions

• MOSI – carries data out of master to slave

• MISO – carries data out of slave to master
– Both MOSI and MISO are active during every
transmission
• SS# (or CS) – unique line to select each slave
chip
• SCLK – produced by master to synchronize
transfers

7
SPI uses a “shift register” model of
communications

Master shifts out data to Slave, and shifts in data

from Slave
http://upload.wikimedia.org/wikipedia/commons/thumb/b/bb/SPI_8-bit_circular_transfer.svg/400px-SPI_8-bit_circular_tra
nsfer.svg.png

8
Two bus configuration
models

Some wires have been

renamed
Master and multiple
daisy- chained slaves
Master and multiple http://www.maxim-ic.com/appnotes.cfm/an_pk/3947

independent
slaves
http://upload.wikimedia.org/wikipedia/commons/thumb/f/fc/SPI_t
hree_sla
ves.svg/350px-SPI_three_slaves.svg.png

9
SPI clocking: there is no
“standard way”
• Four clocking “modes”
– Two phases
– Two polarities
• Master and selected slave must be in the same
mode
• During transfers with slaves A and B, Master
must
– Configure clock to Slave A’s clock mode
– Select Slave A
– Do transfer
– Deselect Slave A
– Configure clock to Slave B’s clock mode
– Select Slave B
– Do transfer
– Deselect Slave B
1
SPI timing
diagram

Timing Diagram – Showing Clock polarities and

phases
http://www.maxim-ic.com.cn/images/appnotes/3078/3078Fig02.gif

1
SPI tradeoffs: the pros
and cons
• Pros
– Fast for point-to-point connections
– Easily allows streaming/constant data inflow
– No addressing in protocol, so it’s simple to implement
– Broadly supported

• Cons
– Slave select/chip select makes multiple slaves more
complex
– No acknowledgement (can’t tell if clocking in garbage)
– No inherent arbitration
– No flow control (must know slave speed)

1
SPI is used
everywhere!
• Peripherals
– LCDs
– Sensors
– Radios
– Lots of other chips

• Microcontrollers
– Almost all MCUs have SPI
masters
– Some have SPI slaves

1
SPI
summary
• SPI – a 4-wire serial bus (but not official
“standard”)
– MOSI, MISO, SS/CS, and SCLK signals
• Full-duplex operation
• One master
• Multiple slaves
• Best for point-to-point data transfers
• Easily supported
• Broadly used

1
SPI bus
architecture
• Shared
bus
• SCK
• MOSI
• MISO
• Chip
selects

1
SPI bus
architecture
• Compact shared
bus
• SCK
• MOSI
• MISO
• Chip selects

1
I2C
bus

• Inter-Integrated Circuit
• Pronounced “eye-squared-see”
• Sometimes called “eye-two-see”
• Two wire serial bus specification
• Invented by Philips in the early 1980s
• The division is now NXP
• Was a patented protocol, but patent has now
expired

1
I2C
uses

• Originally used by Philips inside television

sets
• Now a very common peripheral bus
standard
• Intended for use in embedded systems
• Philips, National, Xicor, Siemens, … all
use
• Also used in PCs
• RTC
• Temperature sensors
• Variant is the SMBus (system
management bus)
1
I2C bus
architecture
• I2C
• Standardizes peripheral
classes
• SCK, SDA
• Philips/NXP

1
I2C
details
• Two-wire serial protocol with addressing
capability

• Speeds up to 3.4 Mbps

• Discussion: what limits I2C to such small
speeds?
• Multi-master architecture
• Open collector bus driver
• Pull-up resistors

• Multi-master, Multi-slave
• Uses bus arbitration

2
I2C
wiring
• Two lines
• SDA (serial data)
• SCL (serial clock)
• Open collector design
• Simple interfacing in for multi-
voltage
• Supports bus arbitration

2
I2C
clock
• Not a “traditional” clock
• Normally is kept “high” using a pull-up
• Pulsed by the master during data
transmission
• Master could be either the
transmitter or receiver
• Slave device can hold clock low if
needs more time
• Allows for flow control

2
I2C
transaction
• Transmitter/receiver differs from
master/slave
• Master initiates transactions
• Slave responds
• Transmitter sets data on SDA line, slave
acks
• For a read, slave is transmitter
• For a write, master is transmitter

2
I2C start
condition
• Master pulls SDA low while SCL is high
• Normal SDA changes only happen when
SCL is low

2
I2C address
transmission
• Data is always sampled on the rising clock
edge
• Address is 7 bits
• An 8-th bit indicated read or write
• High for read
• Low for write
• Addresses assigned by Philips/NXP
• For a fee
• Was covered by patent

2
I2C data
transmission
• Transmitted just like address (8 bits)
• For a write, master transmits, slave
acknowledges
• For a read, slave transmits, master
acknowledges
• Transmission continues
• Subsequent bytes sent
• Continue until master creates stop
condition

2
I2C stop
condition

• Master pulls SDA high while SCL is

high
• Also used to abort transactions

2
I2C bus transactions: start and stop
conditions

2
I2C bus transactions: data
transfer

2
I2C bus transactions: data
transfer

3
 UART: U n i v e r s a l A s y n c h r o n o u s
R e c e i v e r Tr a n s m i t t e r

•UART is a simple half-duplex, asynchronous,

serial protocol.

•Simple communication between two

equivalent nodes.

• Any node can initiate communication.

• Since connection is half-duplex, the two

lanes of communication are completely
independent.
 UART: U n i v e r s a l A s y n c h r o n o u s
Receiver
Tr ans m it t er
• What makes it ‘universal’ ?
Its parameters (format , speed ..) are
configurable.

•W h y
‘asynchronous’ ? It
doesn’t have a
clock .
 UA RT B a s i c s

• Baud Rate:
No. of bits transmitted/received per
second =
bits/sec.

• Format of Communication
 Connections for
U A R T B a s i UART
cs
 UA RT C ha r a c t e r i s t i c s

• The speed of communication (measured in

bauds) is predetermined on both ends.

• A general rule of thumb is to use 9600

bauds for wired communication.

• UART implements error detection in the

form of parity bit.
 Parity Bit

• Parity bit is HIGH when number of 1’s in the

Data is odd.

• Respectively, it is LOW when number of 1’s

in the Data is even
Connecting A R D U I N O with
Computer

• Latest Direct
Way
Serial
Communication:
Serial Monitor
Serial
Communication:
Serial Monitor
 C o d i n g for
Arduino

• Serial.begin(speed)
Sets the data rate in bits per second (baud) for serial data
transmission.
• Serial.end()
Disables serial communication, allowing the R X and TX pins to
be used for general input and output.
To re-enable serial communication, call Serial.begin().
• Serial.read()
Reads incoming serial data
• Serial.println(val)
• Serial.println(val, format)
Prints data to the serial port a s human-readable ASCII text
followed by a carriage return character (ASCII 13, or '\r') and a
newline character (ASCII 10, or '\n')
 C o d i n g Fo r A r d u i n o

•
• Serial.print(val)
• Serial.print(val, format)
Prints data to the serial port as human-readable ASCII
text.
• Serial.flush()
Waits for the transmission of outgoing serial data to
complete. (Prior to Arduino 1.0, this instead
removed any buffered incoming serial data.)
• Serial.available()
Get the number of bytes (characters) available for
reading from the serial port. This is data that's
already arrived and stored in the serial receive buffer
(which holds 6 4 bytes).
 S a m p l e C o d e for A r d u i n o

• Int incomingByte = 0;
• // for incoming serial data
• void setup() {
• Serial.begin(9600);
• // opens serial port, sets data rate to 9 6 0 0
bps
• }
• void loop() {
• // send data only when you receive data:
• if (Serial.available() > 0) {
• // read the incoming byte:
• incomingByte= Serial.read();
• // s a y what you got:
• Serial.print("I received: ");
• Serial.println(incomingByte, DEC);
• }
• }
S P I – Serial Peripheral
Interface
SPI

• Serial ? ?
• Because it works on serial mode of transfer.
It is also synchronous and full duplex.
• Peripheral Interface.
• Because it has the capability of
communicating with many nodes.
• H o w ? ? Let us see.
SPI

• In SPI, the sender and receiver follows a

master- slave relationship.
• There m a y be multiple nodes in the
network.
• One node is master, the rest are slaves.
• The communication is always initiated
by the master.
• The slaves can communicate only
with the master.
• How do master selects the slave??
SPI Schematics: Single Slave
SP I Pins

• CLK is generated by Master and is used

as the mode is synchronous.
• M O S I is Master Out Slave In: Data sent by
Master to Slave.
• M I S O is Master In Slave Out: Data sent by
Slave to Master.
• SSSS is slave select: Slave
communicates with Master only if this
pin’s value is set as LOW.
SPI Schematics: Single Slave
S P I Schematics: Multiple Slaves
D a t a Tr a n s f e r i n S P I

MOS MIS
M0 S0
I O
M1 S1

M S
MASTE SLAV
R 2 2 E
M S

3 3

M S

4 4

M S
D a t a Tr a n s f e r i n S P I

MOS MIS
M1 S1
I O
M2 S2

M S
MASTE SLAV
R 3 3 E
M S4

4 S5

M S6

5 S7

M M
D a t a Tr a n s f e r i n S P I

MOS MIS
M2 S2
I O
M3 S3

M S
MASTE SLAV
R 4 4 E
M S5

5 S6

M S7

6 M

M 0
D a t a Tr a n s f e r i n S P I

MOS MIS
S0 M0
I O
S1 M1

S M
MASTE SLAV
R 2 2 E
S M

3 3

S M

4 4

S M
Clock Polarity (CPOL)

• The value of CPOL bit decides the value of Clock (SCK)

in its idle state.
• When CPOL = 1 , S C K is 5V in idle state.
• When CPOl = 0 , S C K is 0V in idle state.

CPOL Leading Trailing ( L ast )

(First) Edge
Edge
0 (low) Rising Falling
1 (high) Falling Rising
Clock P h a s e ( CPHA)

• The settings of the Clock Phase bit (CPHA)

determine if data is sampled on the leading
(first) or trailing (last) edge of SCK

CPHA Sample
0 (half) Leading Edge
1 (start) Trailing Edge
M o d e s of S P I

• Two - Two possible values of CPOL and

CPHA bits gives rise to 4 modes of SPI

Mode Clock Clock P h a s e ( C P H A )

Polarity
(CPOL)
0 0 0
1 0 1
2 1 0
3 1 1
S P I Trans fe r Fo r m a t w i t h
CPHA
= 0
S P I Trans fe r Fo r m a t w i t h
CPHA
= 1
S P I C o d e for Arduino

• SPI.begin();
Initializes the SPI bus by setting SCK, MOSI, and
S S to outputs, pulling SC K and MOSI low, and
S S high.
• SPI.end();
Disables the SPI bus (leaving pin modes
unchanged).
• setClockDivider(divider)
Sets the SPI clock divider relative to the system
clock. The default setting is SPI_CLOCK_DIV4,
which sets the SPI clock to quarter of system
clock.
• SPI.setDataMode(mode)
Sets the SPI data mode: that is, clock polarity
S P I C o d e for Arduino

• SPI.setBitOrder(order)
Sets the order of the bits shifted out of and
into the SPI bus, either LSBFIRST (least-
significant bit first) or MSBFIRST (most-
significant bit first).
 Introduction to I2C
 I2C is a control bus providing
communications link between integrated
circuits in a system.
 Developed by Philips in the early 1980s.
 Examples of I2C-compatible devices
found in embedded systems include
EEPROMs, thermal sensors and real-time
clock.
 Why I2C has endured?

 Bus has kept pace with performance

and today offers 3 levels of data
transfer rate
 100kbps in standard mode
 400kbps in Fast mode
 3.4 Mbps in high-speed mode
 Why I2C has endured?

 Reliable performance using software-

controlled collision detection and
arbitration.
 Ease of use. 2 lines connect all ICs in
a system.
 Software controlled addressing
scheme eliminating need for address-
decoding hardware.
 What does I2C consist of?

I2C is a 2 wire serial bus as shown above. The 2 signals are

SDA Serial Data
SCL  Serial Clock
Together these signals make it possible to support serial transmission.
 I2C BUS

 The device that initiates the transaction on the I2C

bus is termed the master. The master normally
controls the clock signal.
 A device being addressed by the master is called
the slave.
 There needs to be at least one master( a
microcontroller or a DSP) on the bus, but there can
be more than one master. All the masters on a bus
have equal priority.
 Every device on the I2C bus has a
unique 7 bit (or 10 bit) I2C address.
 Typically the 4 most significant bits are
fixed and assigned to specific
categories of devices. Ex: 1010 is
assigned to serial EEPROM.
 The lower 3 bits are programmable
allowing 8 devices of one kind to be
present on a single I2C bus.
 Terminology for bus transfer

SCL and SDA are bi-directional !

 F(free) – Bus is idle or free. Both SDA and SCL are in a high
state
 S(Start) or R(Restart) – SDA changes from high to low with
the SCL line remaining high. All data transfers begin with
S(Start) condition.
 C(Change) – SCL line is low. Data bit to be transferred is
applied to the SDA line.
 D(Data) – high or low bit of information on SDA line is valid
during the high level of the SCL line.
 P(Stop) – SDA line changes from low to high with SCL line
remaining high. All data transfers end with P(Stop) condition.
 Data transfer
• Data is transferred in sequences of 8 bits.
•Bits are placed on SDA line with MSB first.
•SCL line is then pulsed high and then low.
•For every 8 bits transferred, the device receiving the
data sends back an acknowledge bit.
 Data transfer(contd)

 If the receiving device sends back an low ACK bit,

then it has received the data and is ready to accept
another byte.
 If it sends back a high ACK, then the device is
indicating that it cannot accept any further data and
the master should terminate the transfer by sending
a stop sequence.
 Writing to a slave device

 Master sends a start sequence. This alerts all the

slave devices to an impending transaction and they
should listen , in case its for them.
 Next the master sends out the device address with
read/write bit low. The slave that matches this
address will continue the transaction , while others
ignore.
 Master can now send data byte(s).
 Master sends the stop sequence.
 Reading from a slave

 Master sends a start sequence.

 Master sends the device address with read/write bit high.
 Master reads data from the device.
 Master sends the stop sequence
 ANALOG
COMMUNICATION
 What is a communication system?.

 Communication systems are designed to transmit

information.
 Communication systems Design concerns:
• Selection of the information–bearing waveform;
• Bandwidth and power of the waveform;
• Effect of system noise on the received information;
• Cost of the system.

These factors will be discussed later in this course

Eeng360 75
Digital and Analog Sources and
Systems
Basic Definitions:
• Analog Information Source:
An analog information source produces messages which are defined on a
continuum. (E.g. :Microphone)

• Digital Information Source:

A digital information source produces a finite set of possible messages.
(E.g. :Typewriter)

x(t) x(t)

t t
Analog Digital

Eeng360 76
 Digital and Analog Sources and
Systems
A digital communication system transfers information from a digital
source to the intended receiver (also called the sink).
An analog communication system transfers information from an
analog source to the sink.
A digital waveform is defined as a function of time that can have a
discrete set of amplitude values.
An Analog waveform is a function that has a continuous range of
values.

Eeng360 77
Digital Communication
Advantages
• Relatively inexpensive digital circuits may be used;
• Privacy is preserved by using data encryption;
• Data from voice, video, and data sources may be merged and
transmitted over a common digital transmission system;
• In long-distance systems, noise dose not accumulate from
repeater to repeater. Data regeneration is possible
• Errors in detected data may be small, even when there is a large
amount of noise on the received signal;
• Errors may often be corrected by the use of coding.

Disadvantages
• Generally, more bandwidth is required than that for analog
systems;
• Synchronization is required.

Eeng360 78
Block Diagram of A Communication
System
 All communication systems contain three main sub systems:

1. Transmitter
2. Channel
3. Receiver

Transmitter Receiver

Eeng360 79
 Block Diagram of A Communication
System
TRANSMITTER:
 The signal-processing block is used for more efficient transmission.
Examples:
• In an analog system, the signal processor may be an analog low-pass filter
to restrict the bandwidth of m(t).
• In a hybrid system, the signal processor may be an analog-to-digital
converter (ADC) to produce digital signals that represent samples of the
analog input signal.

 The transmitter carrier circuit converts the processed base band signal into a
frequency band that is appropriate for the transmission medium of the channel.

Example:
• An amplitude –modulated (AM) broadcasting station with an assigned
frequency of 850 kHz has a carrier frequency fc=850kHz. The mapping of the
base band input information waveform m(t) into the band pass signal s(t) is
called modulation. It will be shown that any band pass signal has the form

s (t ) R (t ) cos( ct   (t ))  c 2 f

If R(t)=1 and θ(t) = 0, s(t) would be a pure sinusoid of frequency f=fc with zero
bandwidth.

Eeng360 80
 Block Diagram of A Communication
System
Channel:
 Channels represents the path in which signals travel from transmitter to
receiver. Very general classification of channels are:

• Wire: Twisted-pair telephone line, coaxial cable, waveguide, and fiber-

optic cables.
• Wireless: Air vacuum, and seawater.

In general, the channel medium attenuates the signal so that the delivered
information deteriorated from that of the source. The channel noise may arise
from natural electrical disturbances or from artificial sources.

Transmitter Receiver

Eeng360 81
 Block Diagram of A Communication
System
Receiver:
 The receiver takes the corrupted signal at the channel output and converts
it to be a base band signal that can be handled by the receiver’s base band
processor.

 The base band processor cleans up this signal and delivers an estimate
of the source information m(t) to the communication system output.

 In digital systems, the measure of signal deterioration is usually taken to be

the probability of bit error P(e) – also called Bit Error Rate (BER) of the
delivered data m(t).

 In analog systems, the performance measure is usually taken to be the

Signal-to-noise Ratio (SNR) at the receiver output.

Transmitter Receiver

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What makes a Communication System
GOOD
 We can measure the “GOODNESS” of a
communication system in many ways:

 How close is the estimate to the original signal m(t)

• Better estimate = higher quality transmission

• Signal to Noise Ratio (SNR) for analog m(t)
• Bit Error Rate (BER) for digital m(t)

 How much power is required to transmit s(t)?

• Lower power = longer battery life, less interference

 How much bandwidth B is required to transmit s(t)?

• Less B means more users can share the channel
• Exception: Spread Spectrum -- users use same B.

 How much information is transmitted?

• In analog systems information is related to B of m(t).
• In digital systems information is expressed in bits/sec.

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