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Advanced trends in microcontrollers by suhel
The document discusses advancements in microprocessor technology, focusing on multi-core processing and inbuilt USB connectivity. It highlights Moore's law, the need for multi-core processors to address limitations in single-core designs, and the benefits of reduced power consumption and increased performance. Additionally, it covers challenges such as power and temperature dependence, cache coherence, and multithreading in multicore systems.
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Advanced trends in microcontrollers by suhel
- 1. PRESENTED BY: 1. SuhelMulla (MIS no: 121333009) 2. Anjani Gheware (MIS no: 121333003) 12/21/2013 1:17 AM College of Engineering, Pune 1
- 2. Discussed Technology Microprocessorsadvanced through many stages in the course of time, different features are added to it,two of them which are discussed in the presentation are as follows : Multicore processing Inbuilt USB Connectivity 12/21/2013 1:17 AM College of Engineering, Pune 2
- 3. Moore’s law Itstates that, “For every 18 to 24 months later in IC fabrication, any one of below case possible – 1. No of transistors on a die gets doubled. 2. Size of the chip gets halved. 3. Operating frequency gets doubled. 4. Supply voltage decreases by √2 times. If any two conditions are satisfied, that is best design. Any three or all four can never be satisfied.” 12/21/2013 1:17 AM College of Engineering, Pune 3
- 4. Why Multi-core……?? !!! Shrinking die size and increasing component density has came to a limit. Escalating clock speed are boosting heat dissipation problems. Sophisticated pipelining techniques have reached an optimum balance between improving best case and doing minimum harm in worst case. Thus, Multi-core processor is a way to extend Moore’s law so that the user gets more performance out of a single piece of silicon. 12/21/2013 1:17 AM College of Engineering, Pune 4
- 5. Contd… Computer architectsneeded a new approach to improve performance. Adding an additional processing core to the same chip would result in twice the performance and dissipate less heat. The actual speed of each core is slower than the fastest single core processor. IEEE Review noted that “the power consumption increases by 60% with every 400MHz rise in clock speed”. But the dual-core approach means you can get a significant boost in performance without the need to run at ruinous clock rates.” 12/21/2013 1:17 AM College of Engineering, Pune 5
- 6. Microprocessors using multicore architecture Intel’s Pentium D, core 2 duo & xenon series AMD’s Athlon, Turion and Opteron series Sony-Toshiba-IBM’s Cell Processor series Tilera’s TILE64 Processor 12/21/2013 1:17 AM College of Engineering, Pune 6
- 7. Conventional Processor Architecture 12/21/20131:17 AM College of Engineering, Pune 7
- 8. Performance and designparameters of multicore processor systems Power Consumption Temperature Dissipation Frequency Requirement No. of Cores in a die Type of cores ( Homogeneous or Heterogeneus ) Communication Protocol (e.g. Round Robin, Daisy Chain etc.) Memory Configuration ( Universal vs. Distributed cache ) 12/21/2013 1:17 AM College of Engineering, Pune 8
- 9. Memory Models inMulti-core Processors a) Shared memory model 12/21/2013 1:17 AM b) Distributed memory model College of Engineering, Pune 9
- 10. Comparison of singlecore and Multi-core Processors Multicore processors seem to answer the deficiencies of single core processors, by increasing bandwidth while decreasing power consumption. 12/21/2013 1:17 AM College of Engineering, Pune 10
- 11. Intel and AMDDual-Core Processors 12/21/2013 1:17 AM College of Engineering, Pune 11
- 12. Multicore Challenges Powerand Temperature Dependence Cache Coherence Problem Multithreading 12/21/2013 1:17 AM College of Engineering, Pune 12
- 13. Power and Temperature Dependence To combat unnecessary power consumption many designs incorporate a power control unit that has the authority to shut down unused cores or limit the amount of power. By powering off unused cores, the amount of leakage in the chip is reduced. To lessen the heat generated by multiple cores on a single chip, the chip is architected so that the number of hot spots doesn’t grow too large and the heat is spread out across the chip. 12/21/2013 1:17 AM College of Engineering, Pune 13
- 14. Contd… Cell Processor ThermalDigram 12/21/2013 1:17 AM College of Engineering, Pune 14
- 15. Cache Coherence Ingeneral there are two schemes for cache coherence, a snooping protocol and a directory-based protocol. The snooping protocol only works with a bus-based system, and uses a number of states to determine whether or not it needs to update cache entries and if it has control over writing to the block. The directory-based protocol can be used on an arbitrary network and is, therefore, scalable to many processors or cores, in contrast to snooping which isn’t scalable Intel’s Core 2 Duo tries to speed up cache coherence by being able to query the second core’s L1 cache and the shared L2 cache simultaneously. Having a shared L2 cache also has an added benefit since a coherence protocol doesn‟t need to be set for this level. AMD‟s Athlon 64 X2, 12/21/2013 1:17 AM College of Engineering, Pune 15
- 16. Multi-threading Programmers haveto write applications with subroutines able to be run in different cores, meaning that data dependencies will have to be resolved or accounted for. If one core is being used much more than another, the programmer is not taking full advantage of the multicore system. Applications should be balanced. Languages with multithreaded extensions are more useful for this purpose. 12/21/2013 1:17 AM College of Engineering, Pune 16
- 17. Contd… In orderto use a multi-core processor at full capacity the applications run on the system must be multithreaded. Programmers have to write applications with subroutines able to be run in different cores. In recent time, companies like Apple, Microsoft designed new products with multi-core facility. 12/21/2013 1:17 AM College of Engineering, Pune 17
- 18. Universal serial bus Features: Easy to use Fast Reliable Flexible Inexpensive Power conserving 12/21/2013 1:17 AM College of Engineering, Pune 18
- 19. TERMS USED INUSB USB Host USB Device Enumeration Hub Endpoint 12/21/2013 1:17 AM College of Engineering, Pune 19
- 20. Speed of usb 12/21/20131:17 AM College of Engineering, Pune 20
- 21. Bus Topology 12/21/2013 1:17AM College of Engineering, Pune 21
- 22. Data flow ControlTransfer Bulk Transfer Isochronous Transfer Interrupt Transfer 12/21/2013 1:17 AM College of Engineering, Pune 22
- 23. Electrical design Fig :USB Cable 12/21/2013 1:17 AM College of Engineering, Pune 23
- 24. Powered device Athost should pull down register in range 14.25 to 24.8 kohm. Required pull up register of 500 to 900 ohmat device. Bus powerd device. Self power device. 12/21/2013 1:17 AM College of Engineering, Pune 24
- 25. References Bryan Schaumer,”Multi-core Processor : A Necessity”, Realised in Proquest September 2008 D. Geer, “Chip Makers Turn to Multi-core Processors”, Computer, IEEE Computer Society, May 2009 W. Knight, “Two Heads Are Better Than One”, IEEE Review, September 2009 P. Frost Gorder, “Multi-core Processors for Science and Engineering”, IEEE CS, March/April 2007 “Universal Serial Bus Specification”, Revision 2.0,April 27, 2000 Jan Axelson, “USB Complete”, 2nd Edition, Penram International Publishing. 12/21/2013 1:17 AM College of Engineering, Pune 25
- 26. Any Questions… ??? 12/21/20131:17 AM College of Engineering, Pune 26
- 27. Thank You…!!! 12/21/2013 1:17AM College of Engineering, Pune 27