Digital VLSI Design : Combinational Circuit

Combinational Logic Design
Prof. (Dr.) Usha Mehta
usha.mehta@nirmauni.ac.in

Before we start……
• Logic with Switching Circuits….
• Logic can be done with switches
as well as gates.
• A parallel connection implements OR. A series connection
implements AND. Series and parallel combinations can do
complex logic.
• Loop Analysis
• Construct all paths between a logic “1” and the output.
Each path is a string of ANDs. which are ORed together. The
expression comes out as a Sum-of-Products (Σ of Π)
• Cut-Set Analysis
• Make all the cuts that completely separate the output and
Vcc. The cuts must only pass through switches. The
switches in the cut are ORed together. The expression
comes out as a Product-of-Sums (Π of Σ)
2
CombinationalLogicDr.UshaMehta12-04-2019

In case you forgot…..
12-04-2019CombinationalLogicDr.UshaMehta
3

4

Switch Model
5

MOS as Switch
6

Pull Up / Pull Down
7

nMOS-Pull Down
pMOS-Pull Up
8

Pull Up / Pull Down…..
• For nMOS
• Vgs >= Vt
• 5-Vs>=1
• Vs = [0,4) i.e. ( 0 to Vg-Vt only, never Vg full is
coming to Vs)
• For pMOS
• Vgs =< Vt
• Vg-Vs =< Vt
• 0-Vs =< -1
• Vs = (1,5] i.e. ( 0 to Vg-Vt only, never Vg full is
coming to Vs)
9

CMOS Inverter
10

Determine the logic….
11

Logic to Voltages
12

Source and Drain
Terminals
13

nMOS-pMOS/Series-Parallel
14

NAND2
15

NAND2…
16

NAND2 & NOR2
17

Which is better?
NAND or NOR? Why?
• Considering propagation delay….
• Do remember
• For pMOS and nMOS :
• Hence nMOS is speedier than pMOS.
• So overall delay of CMOS is delay of pMOS
• So to reduce the delay of pMOS, reduce the Ron
of pMOS and hence widen the pMOS i.e. double
size.
• R 1/IDD , IDD W/L => R 1/(W/L)
• Now using inverter model,
• Delay
• For nMOS,
18

Which is better?
NAND or NOR? Why?
• Now using inverter model,
• Delay
• For NAND
• Worst case rise time delay is
• Worst case ( and only) fall time delay is
• For NOR
• Worst case (and only) rise time delay is :
• Worst case fall time delay is:
• Consider Rn = 1 Unit, analyse delay for NOR
and NAND
• in case of pMOS and nMOS of equal size
• Consider widening of pMOS
19

Gates with large Fan-ins
• The earlier slide’s analysis draws the attentions
towards the deficiency of CMOS for large Fan-
in gates
• Larger Fan-ins means
• Either the series connected pMOSes or nMOSes
• Large difference in rise time and fall time
• Need to find out solutions..
20

Solution 1
Transistor Sizing
21

Solution 2
Progressive Transistor Sizing
22

Solution 3
Transistor Ordering
23

Primitive Gates
• INVERTER, NAND, NOR
• AND, OR
• What about XOR, XNOR?
• Draw transistor level Schematic
24

Six Transistors XOR-XNOR
25

Tristate
26

Tristate Inverter
27

COMPLEX BOOLEAN FUNCTIONS
AND ITS TRANSISTOR LEVEL
SCHEMATIC
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CombinationalLogic
Dr.UshaMehta
28

Complimentary Static CMOS
Gates
• At any time, the output is connected to either
power supply or ground with low resistance
path.
• Conduction of Pull-up network (PUN)and Pull-
down network (PDN) should be mutually
exclusive. (Why?)
• PDN and PUN are dual.
• Complimentary static CMOS are inverting.
29

Implementation of Combinational
Logic
30

Implementation of
Combinational Logic
31

Logic
32

Implementation of
Combinational Logic
33

Implementation of
Combinational Logic
34

Logic
35

CMOS Topology AOI/OAI
36

DO REMEBER
• Find and simplify F’
• Make sure that complements are down to the
literal level.
• Implement F’ as nMOS net and connect it
between ground and output
• OR operations by parallel connected nMOS
• AND operations are series connected nMOS
• Find dual of F’, implement it as pMOS net and
connect it between output and power supply.
• AND operations by parallel connected pMOS
• OR operations are series connected pMOS
37

Optimize the transistor level
schematic for # of transistor
• F’
• F
• Literals are available in normal form only
• Literals are available in normal form and
complement form.
38

STICK DIAGRAM FOR TRANSISTOR
LEVEL SCHEMATIC OF COMPLEX
BOOLEAN FUNCTION ( SIZE IS NO
BAR HERE!)
12-04-2019
CombinationalLogic
Dr.UshaMehta
39

CMOS Structure
40

gate
drain
source
nMOS Layout
polysilicon
metal
Contact holes
diffusion (active
region)
41

Stick Diagram
• Stick diagrams help plan layout quickly
• Need not be to scale
• Draw with color pencils or dry-erase markers
• Estimate area by counting wiring tracks and
other areas
Vin
Vout
VDD
GND
42

Stick Diagram Colour Notation
Silicon layers are typically colour coded as follows :
This colour representation is used during mask layer definition
Translation from circuit format to a mask layout (and vice-versa) is relatively straightforward
diffusion (device well, local interconnect)
polysilicon (gate electrode, interconnect)
metal (contact, interconnect)
contact windows
depletion implant
P well (CMOS devices)
43

Layer contact mask layout representation
A transistor is formed when device well is crossed by polysilicon.
Device well oxide : thin gate oxide
Metal contacting diffusion
Metal contacting polysilicon
Metal contacting diffusion (no contact, electricall
isolated
with thick oxide)
Metal crossing polysilicon (no contact, electrically
isolated
with thick oxide and so can carry separate voltages)
diffusion
polysilicon
metal
contact windows
depletion implant
P well
44

Transistor Mask Layout Preparation
A transistor is formed when device well is crossed by polysilicon.
Device well oxide : thin gate oxide
Depletion mode transistor (extra well implant to
provide Vth  -0.6Vdd )
Enhancement mode transistor (Vth  0.2Vdd )
diffusion
polysilicon
metal
contact windows
depletion implant
P well
45

nMOS transistor coloured
stick diagram
46

nMOS Inverter Stick
Diagram
47

CMOS Inverter
48

Static CMOS NAND2 Gate
Stick Diagram
49

Static NOR2 Gate
Stick Diagram
50

Static CMOS Design Example Layout
51

Layout 2 (Different layout style to previous but same function being
implemented)
52

Two Stick Diagrams of F =
(C*(A+B))’
A B C
X
VDD
GND
X
CA B
VDD
GND
uninterrupted diffusion strip
crossover requiring vias
53

To construct a minimum area
layout…
• For a complex logic function, if we choose
arbitrary ordering of polysilicon gates column:
• The separation between the polysilicon columns
must allow
• Diffusion to diffusion separation
• Diffusion to metal separation
• Hence, to reduce the number of diffusion area
break, the ordering of gate column should be
properly planned.
54

Let’s try…..
• F=(A(D+E)+BC)’
55

Stick Diagram
56

Euler Path
• Find a common Euler path for both p and n
graphs
• Euler Path:
• Uninterrupted path which traverse each edge of
the graph exactly once.
57

p-NET and n-NET
58

Euler’s Path
59

Stick Diagram as per Euler’s path
60

Euler’s Theorem
61

Euler’s Theorem
BA D
VDD
GND
C
X
62

Let’s have one magic!!!!!
• Pl. find the Euler path for x = !(a + bc + de)
• Ok…..
• Now try x = !(bc + a + de)
63

Duality of Function
• Pl. find Euler’s path for
• F=!(AB+BC+CA)
• Now try with duality concept….
• F = dual of F
• Now pl. check the n and p graph and find the
Euler’s path
• So easy to draw the stick diagram…
64

Transistor level Schematic of Full
Adder
65

LAYOUT
(W/L IS A BIG CONCERN HERE!)
12-04-2019
CombinationalLogic
Dr.UshaMehta
66

CMOS Inverter Mask Layout (using Microwind)
diffusion
polysilicon
metal
contact windows
depletion implant
P well
67

Static CMOS NOR2 gate
68

Static CMOS NOR2 gate
69

CMOS NAND2 Mask Layout
diffusion
polysilicon
metal
contact windows
depletion implant
P well
70

Layout Design rules & Lambda ()
• Lambda () : distance by which a geometrical feature or
any one layer may stay from any other geometrical feature
on the same layer or any other layer.
• All processing factors are included plus a safety margin.
•  used to prevent IC manufacturing problems due to mask
misalignment
• or exposure & development variations on every feature,
which otherwise could lead to :
• over-diffusion
• over-etching
• inadvertent transistor creation etc
•  is the minimum dimension which can be accurately re-
produced on the silicon wafer for a particular technology.
71

Layout Design rules & Lambda ()
• Minimum photolithographic dimension (width, not
separation) is 2.
• Hence, the minimum channel length dimension is 2.
• Where a 0.25m gate length is quoted,  is 0.125 microns
(m).
• Minimum distance rules between device layers are used,
e.g.,
• polysilicon  metal
• metal  metal
• diffusion  diffusion and
• minimum layer overlaps
• Layout design rule checker (DRC) automatically verifies
that no design rules have been broken
• Note however, the use of Lambda is not optimal but supports
design reuse
72

Layout Design rules &
Lambda ()
Lambda based design: half of technology since 1985. As technology
changes with smaller dimensions, a simple change in the value of  can
be used to produce a new mask set.
6
2
6

4
Hcmos6 technology : =0.2µm
Hcmos8 technology : =0.1µm
All device mask dimensions are based on multiples of , e.g., polysilicon
minimum width = 2. Minimum metal to metal spacing = 3
73

Basic Design Rules
• Minimize spared diffusion
• Use minimum poly width (2) •1 contact = 1mA
•Multiply contacts
2mA
74

Basic Design Rules
• Same N and P alters symmetry • L min
• Wpmos=2 Wnmos
Width of pMOS
should be twice the
width of nMOS
75

CALCULATION OF SIZE
BASICALLY CALCULATION OF
W/L……..
ALL OTHER SIZE IS WITH
REFERENCE TO W/L
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CombinationalLogic
Dr.UshaMehta
76

Design Strategy
• Fan-out, Rise time, Fall time…
• Load Current, VOL, VOH..…
• Depends on W/L and other parameters…
• Designable parameter is (W/L).
• Find the worst case of above parameters and
design for that (W/L)
77

• Performing a manual analysis of the dynamic
behavior of complex gates is only tractable via
a switch model.
• Here, the transistor is modelled as a switch
with an infinite off-resistance and a finite on
resistance, Ron.
• Ron is chosen so that the equivalent RC-circuit
has a propagation delay identical to the
original transistor-capacitor model.
• Ron is inversely proportional to the W/L ratio
but varies during the switching transient.
• Deriving propagation delay can be done by
analysing the RC network.
78

79

W/L Equivalent
(Resistive Load Model)
𝑊
𝐿 𝑒𝑞𝑖
=
𝑘(𝑜𝑛)
𝑊
𝐿 𝑘
𝑊
𝐿 𝑒𝑞𝑢𝑖
=
1
𝐾(𝑜𝑛)
1
(𝑊/𝐿) 𝑘
80

Calculate (W/L)equivalent for
resistive load implementation of
F=!(A(D+E)+BC)
81

Let’s try…..
• Calculate (W/L)equivalent for CMOS
implementation of F=!(A+D+E)(B+C) assuming
(W/L)n = 10 and (W/L)p=15
82

Various VOL Values
83

To calculate W/L….
• Specify maximum allowable VOL value
• Calculate equivalent (W/L)driver using for that
VOL
• Determine worst case path (class-1)
• Determine worst case path transistor size to
give the equivalent worst path VOL same as
equivalent (W/L)driver
84

Layout Optimization
Device Folding / Fingering & Sharing
• When we have to make the devices for large
current (like drivers), the width of the devices
should be very high compared to the other
devices
• Large transistors can be split into smaller ones
and then shorting the corresponding terminals
making up the required W/L
• In such an arrangement we can share the
diffusion drain and source of adjacent
transistors and then we can short the
terminals
85

Folding & Sharing (Cont...)
Why to have folding / fingering?
Poly resistance is reduced as single poly is
divided in multiple parts of poly
To maintain the uniformity in diffusion area
Process variations are less
Why to have sharing?
To save the diffusion area
To reduce the parasitic associated with the
devices
86

Folding and Sharing
D SG
D S
D S
G
Equivalence of devices connected in parallel
87

Folding and Sharing…..
88
D SG D SD SG G
Equivalence of devices connected in series
88

Folding and Sharing
S & D sharing in devices
G
89

Static CMOS
Do remember…
• Every point in time, gate output is connected
to either supply or ground via low resistance
path
• Rail to rail output voltage
• Ratioless design
• Low output and Extremely High input
impedance
• No static power dissipation
• Good Noise Margin
• BUT what about Rise and Fall Time????
90

91

Rise Time and Fall Time in
CMOS Gates….
92

93

Static CMOS
Do remember………
94

Gates with a fan-in greater than 4 become excessively slow and must be avoided.
Solutions????
95

96

Pseudo nMOS Gates
• Only single pMOS in load, permanently gate of
pMOS connected to ground
• Disadvantages:
• Always on load i.e. steady state current, static
power
• o/p voltage < Vdd
• Ratioed logic
97

Ratioed Logic
98

99

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Digital VLSI Design : Combinational Circuit

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Digital VLSI Design : Combinational Circuit