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Embedded System IoT_4.pptx ppt presentation
- 1. Embedded System &IoT Shubham Sharma CISC and RISC
- 10. Advantages of CISCProcessors 1.The compiler requires little effort to translate high-level programs or statement languages into assembly or machine language in CISC processors. 2.The code length is quite short, which minimizes the memory requirement. 3.To store the instruction on each CISC, it requires very less RAM. 4.Execution of a single instruction requires several low-level tasks. 5.CISC creates a process to manage power usage that adjusts clock speed and voltage. 6.It uses fewer instructions set to perform the same instruction as the RISC. Disadvantages of CISC Processors 1.CISC chips are slower than RSIC chips to execute per instruction cycle on each program. 2.The performance of the machine decreases due to the slowness of the clock speed. 3.Executing the pipeline in the CISC processor makes it complicated to use. 4.The CISC chips require more transistors as compared to RISC design. 5.In CISC it uses only 20% of existing instructions in a programming event.
- 16. Advantages of RISCProcessor 1.The RISC processor's performance is better due to the simple and limited number of the instruction set. 2.It requires several transistors that make it cheaper to design. 3.RISC allows the instruction to use free space on a microprocessor because of its simplicity. 4.RISC processor is simpler than a CISC processor because of its simple and quick design, and it can complete its work in one clock cycle. Disadvantages of RISC Processor 1.The RISC processor's performance may vary according to the code executed because subsequent instructions may depend on the previous instruction for their execution in a cycle. 2.Programmers and compilers often use complex instructions. 3.RISC processors require very fast memory to save various instructions that require a large collection of cache memory to respond to the instruction in a short time.
- 17. CISC RISC Emphasis onhardware Emphasis on software Includes multi-clock complex instructions Single-clock, reduced instruction only Memory-to-memory: "LOAD" and "STORE" incorporated in instructions Register to register: "LOAD" and "STORE" are independent instructions Small code sizes, high cycles per second Low cycles per second, large code sizes Transistors used for storing complex instructions Spends more transistors on memory registers
- 18. RISC CISC It isa Reduced Instruction Set Computer. It is a Complex Instruction Set Computer. It emphasizes on software to optimize the instruction set. It emphasizes on hardware to optimize the instruction set. It is a hard wired unit of programming in the RISC Processor. Microprogramming unit in CISC Processor. It requires multiple register sets to store the instruction. It requires a single register set to store the instruction. RISC has simple decoding of instruction. CISC has complex decoding of instruction. Uses of the pipeline are simple in RISC. Uses of the pipeline are difficult in CISC. It uses a limited number of instruction that requires less time to execute the instructions. It uses a large number of instruction that requires more time to execute the instructions. It uses LOAD and STORE that are independent instructions in the register-to-register a program's interaction. It uses LOAD and STORE instruction in the memory-to-memory interaction of a program. RISC has more transistors on memory registers. CISC has transistors to store complex instructions. The execution time of RISC is very short. The execution time of CISC is longer. RISC architecture can be used with high-end applications like telecommunication, image processing, video processing, etc. CISC architecture can be used with low-end applications like home automation, security system, etc. It has fixed format instruction. It has variable format instruction. The program written for RISC architecture needs to take more space in memory. Program written for CISC architecture tends to take less space in memory. Example of RISC: ARM, PA-RISC, Power Architecture, Alpha, AVR, ARC and the SPARC. Examples of CISC: VAX, Motorola 68000 family, System/360, AMD and the Intel x86 CPUs.
- 19. However, the RISCstrategy also brings some very important advantages. Because each instruction requires only one clock cycle to execute, the entire program will execute in approximately the same amount of time as the multi-cycle "MULT" command. These RISC "reduced instructions" require less transistors of hardware space than the complex instructions, leaving more room for general purpose registers. Because all of the instructions execute in a uniform amount of time (i.e. one clock), pipelining is possible.
- 48. The Performance Equation Thefollowing equation is commonly used for expressing a computer's performance ability: The CISC approach attempts to minimize the number of instructions per program, sacrificing the number of cycles per instruction. RISC does the opposite, reducing the cycles per instruction at the cost of the number of instructions per program.