Verilog

Verilog

• 1.
  Verilog Parallel Computing
• 2.
  Verilog • Verilog isa HARDWARE DESCRIPTION LANGUAGE (HDL). • A hardware description language is a language used to describe a digital system: • for example, a network switch, a microprocessor or a memory or a simple flip- flop. This just means that, by using a HDL, one can describe any (digital) hardware at any level.
• 3.
  Design Styles • Verilog,like any other hardware description language, permits a design in either Bottom- up or Top-down methodology.
• 4.
  Bottom-Up Design • Thetraditional method of electronic design is bottom-up. Each design is performed at the gate- level using the standard gates (refer to the Digital Section for more details). With the increasing complexity of new designs this approach is nearly impossible to maintain. New systems consist of ASIC or microprocessors with a complexity of thousands of transistors. These traditional bottom-up designs have to give way to new structural, hierarchical design methods. Without these new practices it would be impossible to handle the new complexity.
• 5.
  Top-Down Design • Thedesired design-style of all designers is the top-down one. A real top-down design allows early testing, easy change of different technologies, a structured system design and offers many other advantages. But it is very difficult to follow a pure top-down design. Due to this fact most designs are a mix of both methods, implementing some key elements of both design styles.
• 6.
  Verilog Abstraction Levels •Verilog supports designing at many different levels of abstraction. Three of them are very important: • Behavioral level • Register-Transfer Level • Gate Level