VlSI course project report : Keypad Scanner

VlSI course project report : Keypad Scanner

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  Project report on Keypadscanner Submitted by, Chaitanya Deshpande B197001 Omkar Rane B197026 Nitesh Mandal B197063 Guided by, Dr. Dipti Sakhare A report submitted, in partial fulfilment of the requirements for Seventh semester of BACHELOR OF TECHNOLOGY in ELECTRONICS & TELECOMMUNICATION ENGG. School of Electrical Engineering Alandi (D), Pune – 412105 2019-2020
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  Contents Abstract 1 Acknowledgement 2 1.Introduction 3 2. Implementation Details 6 3. Results 7 4. Conclusion 10 References 11
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  1 Abstract This project isabout keypad scanner. In this project, we are designing, simulating and implementing keypad scanner on FPGA. Logic for this project is written in Verilog code and is used for simulation in software. We are using Xilinx Vivado software for simulation and FPGA for hardware.
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  2 Acknowledgement I take thisopportunity to record my profound gratitude and indebtedness to Dr. Dipti Sakhare, Assistant Professor, Department of Electronics Engineering for her inspiring guidance, valuable advices, constant encouragement and untiring supervision throughout my project work. I express my deep sense of gratitude to Mrs. Anjali Dhumal, Lab Assistant, Department of Electronics and Telecommunication Engineering for valuable help. Also I express my deep sense to guide Dr. Dipti Sakhare, who pushed us within a lot by believing us and encourage us to complete this project. Finally, I would like to acknowledge and express my special thanks to my friends, especially my group mates for majorly contributing than any other in completing the project and my classmates for their patience, encouragement, support they have made during the period of this project. Omkar Rane Nitesh Mandal Chaitanya Deshpande
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  3 1. Introduction We designeda scanner for a keypad with three columns and four rows. The keypad is wired in matrix form with a switch at the intersection of each row and column. Pressing a key establishes a connection between a row and column. The purpose of the scanner is to determine which key has been pressed and to output a binary number N5 N3 N2 N1 N0, which corresponds to the key number. For example, pressing key 5 must output 0101, pressing the * key must output 1010, and pressing the # key must output 1011. When a valid key has been detected, the scanner should output a signal V for one clock time. When a switch is pressed, a path is established from the corresponding column line to the ground. If a voltage can be applied on the column lines C0, C1, and C2, then the voltage can be obtained on the row line corresponding to the key that is pressed. One among the rows R0, R1, R2 or R3 will have an active signal. Figure 1.1 Keypad used in Mobile phones.
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  4 Fig 1.2 Blockdiagram for keypad scanner We will use the following procedure to scan the keyboard: First apply logic 1s to columns C0, C1, and C2 and wait. If any key is pressed, a 1 will appear on R0, R1, R2 or R3. Then apply a 1 to column C0 only. If any of the R is 1, a valid key is detected. If R0 is received, one knows that switch 1 was pressed. If R1, R2, or R3 is received, it indicates switch 4, 7, or * was pressed. If so, set V 5 1 and output the corresponding N. If no key is detected in the first column, apply a 1 to C1 and repeat. If no key is detected in the second column, repeat for C2. When a valid key is detected, apply 1s to C0, C1, and C2 and wait until no key is pressed. This last step is necessary so that only one valid signal is generated each time a key is pressed. FPGA Board
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  5 Truth Table &Equations: Fig 1.2 Truth table and logical equations. C0 C1 C2
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  6 Hardware and softwarerequirements: a) Software requirements Xilinx Vivado 2014.4 b) Hardware requirements Digilent Nexys ddr (Artix 7 based) FPGA board. 2. Implementation details a) Verilog code in dataflow modelling style. module key( input r0, input r1, input r2, input r3, input c0, input c1, input c2, output n3, output n2, output n1, output n0 ); assign n3= (r2 & ~c0) | (r3 & ~c1); assign n2= r1 | (r2 & c0); assign n1=(r0 & ~c0)|(~r2 & c2)|(~r1 & ~r0 & c0); assign n0=(r1 & c1)|(~r1 & c2)|(~r3 & ~r1 & ~c1); endmodule
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  7 3.Results b)Simulation result Figure 3.1Waveform diagram
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  8 Figure 3.2 XDCfile Figure 3.3 Assigning switches.
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  9 Figure 3.4 Assigningswitches and Hardware implementation. c) Hardware result Figure 3.5 Assigning switches and Hardware implementation.
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  10 4.Conclusion We had successfullyimplemented and tested keypad scanner as a course project in VLSI design course. We learnt implement logic equations by programming them through various hardware language like Verilog and VHDL on field programmable logic array-based boards. We also logically verified truth table configuration of each and every key pressed on keypad.
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  11 1. References [1] VerilogHDL synthesis, A practical primer, Author: J. Bhasker. [2] Fundamentals of digital logic with Verilog design, Author: Stephen brown, Zvonko Vranesic. [3] Verilog digital system design,second edition, Author:Zainalabeddin Navabi. [4] Neil Weste and David Harris, “Principles of CMOS Design”, 4th Edition, Pearson Education, 2010, ISBN: 9780321547743 [5] John F Wakerly, “Digital Design-Principles and Practices”, 4th Edition Pearson education, ISBN : 9780131863897. [6] Charles H. Roth,“Digital systems design using VHDL”, PWS. ISBN : 978-8131500279. [7] Samir Palnitkar,” Verilog HDL: A Guide to Digital Design and Synthesis”,2nd Edition Publisher: Prentice Hall PTR Publication, February 21, 2003, ISBN: 978-0132599702. [8] Digilent Nexys ddr (Artix 7 based) FPGA board datasheet.