Announcements
• No office hours today or Thursday (catching a
plane right after class).
• Emily Allstot (TA) will give Friday lecture.
• Exam 2 in class on Monday 5/19
– MOSFETs
– MOSFETs in circuits and NMOS Logic
– HWs 4‐6
EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham
MOSFET Capacitances: Linear
Gate to Channel capacitance in
inversion (or accumulation) :
”
This is split between S and D:
"/2 0
"/2 0
There is also capacitance to body (diode area and sidewall)
" ′
" ′
EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham
MOSFET Capacitances: Saturation
In saturation, This is split
between S and D:
2/3 " 0
0
Still capacitance to body (diode area and sidewall)
" ′
" ′
EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham
MOSFET Capacitances: Cutoff
In cutoff, just overlap
capacitance remains between
G and S/D:
0
0
Small capacitance between gate and body
0
EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham
MOSFET Spice Model
EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham
EE 331 Devices and Circuits I
Chapter 6
Digital Electronics
EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham
Boolean Algebra
• Each statement is either “False” or “True”
• Assign a value to false (0) and another value to
true (1)
• 3 most basic operations: NOT, AND, OR
EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham
Boolean Algebra: Truth Tables
NOT OR AND NOR NAND
̅
A Z A B Z A B Z A B Z A B Z
0 1 0 0 0 0 0 0 0 0 1 0 0 1
1 0 0 1 1 0 1 0 0 1 0 0 1 1
1 0 1 1 0 0 1 0 0 1 0 1
1 1 1 1 1 1 1 1 0 1 1 0
• True = “1”, False = “0”
• NOR = NOT(OR), NAND = NOT(AND)
EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham
Boolean Identities
A + B = A B
Missing in text
EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham
Diode Logic
• D: {Von = 0.7 V, Ron = 0 Ω}
• If VA and VB both Low, DA
and DB both off, VO = 0 V (L)
“pull down” • If either VA or VB (or both)
go High (e.g. 5V), then DA
A B OUT or DB (or both) turn on,
0 0 0 and VO=5V‐Von=4.3V (H)
0 1 1
• OR gate
1 0 1
1 1 1
EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham
Diode Logic
• AND gate
A B OUT
0 0 0
0 1 0
1 0 0
1 1 1
“pull‐up”
EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham
Inverter
• Basic building block of digital logics
• NOT operation:
– Input TRUE (1) => output FALSE (0)
– Input FALSE (0) => output TRUE (1)
• Inverter
– input high voltage => output low voltage
– input low voltage => output high voltage
EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham
Ideal Inverter
• Requires an extra external power source
EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham
“Real” Inverter
• VIL : Maximum vI recognized
as a low input logic level.
• VIH : Minimum vI recognized
as a high input logic level.
• VOH : The vO corresponding to
an input voltage of VIL.
• VOL : The vO corresponding to
an input voltage of VIH.
• VL : Nominal output voltage
corresponding to a low‐logic
state for vI = VH.
• VH : Nominal output voltage
corresponding to a high‐logic
state for vI = VL.
EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham
“Real” Inverter
• :
the ‐1 slope points
• For (input
low) =>
(output high)
• For
(input high) =>
(output low)
• For :
undefined logic state
EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham
Noise Margin
• Noise margins represent “safety margins” that
prevent the circuit from producing erroneous
outputs in the presence of noisy inputs
• Noise margins are defined for low and high
input levels by:
EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham
Sample Inverter Circuits
EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham
NMOS Logic Design
• Designer’s job: choose the circuit topology
and the W/L ratios of the MOS transistors to
achieve the desired logic function
• Power supply voltage VDD
– 1.8–3.3 V power supply levels have gained
widespread use. Even lower now.
– Many portable low‐power systems (cell phones)
have voltages around 1.0 ‐ 1.5 V
EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham
NMOS Logic Design
• Inverters with different NMOS load
configurations:
– the resistor load
– saturated load
– depletion‐mode load
– linear load
– pseudo NMOS
EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham
NMOS resistive load inverter
Kn’=100μA/V2 • A resistor load to “pull”
VTN=0.6V the output up toward
the power supply VDD.
• Switch between two
states:
– Triode region:
,
Design: Chose R and – Cutoff region:
W/L of MS
EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham
NMOS resistive load inverter
Kn’=100μA/V2 MS cutoff
VTN=0.6V •
• is set by power supply
voltage VDD.
• should be less than ,
typically
EE 331 Spr 2014 Microelectronic Circuit Design © UW EE Chen/Dunham
