Verilog Test Paper
Time: 1 Hours
Maximum Marks: 100
Instructions:
1. This paper consists of Three sections: Section A (MCQs), Section B, Section C.
2. Each MCQ has only one correct answer.
3. There is no negative marking.
Section A: Multiple Choice Questions (MCQs)
[2 Marks Each]
1. What is the default value of a reg type in Verilog?
a) 0
b) 1
c) x
d) z
2. Output of below program:
module test;
integer a= 0;
always@(a)
begin
a= a+1;
$display(a);
End
endmodule
a)x
b) will not print anything
c) infinite loop
d) error
3. Choose the Correct declaration of 16X8 Memory.
a) reg[7:0][15:0]mem;
b) reg[7:0] mem[15:0];
c) reg[15:0] mem[7:0];
d) reg mem[15:0][7:0];
4. Which of the following is true about blocking and non-blocking assignments?
a) Blocking assignments execute sequentially.
b) Non-blocking assignments execute sequentially.
c) Blocking assignments execute in parallel.
d) Non-blocking assignments execute sequentially.
5. Which of the following is not a Verilog compiler directive?
a) `timescale
b) `define
c) `ifdef
d) `function
6. What is correct output of below program?
module test;
wire a;
assign c= 1’b0;
assign c= 1’b1;
initial begin
$display(c);
end
endmodule
a) z
b) 1
c) x
d) Compilation Error
7. Which of the following is not a loop construct in Verilog?
a) for
b) while
c) repeat
d) do-while
8. To suspend a simulation, you can use this system task command.
a) $finish
b) $stop
c) $end
d) $close
9. Which of the following types cannot be synthesized in Verilog?
a) integer
b) wire
c) reg
d) real
10. What is the result of 4'b0101 && 4'b1xx0?
a) 0
b) 1
c) x
d) z
Section B: Short Answer Questions
[5 Marks each ]
1. What are the different types of Data-types in Verilog. Explain properly.
2. How many different types of Modeling we have in Verilog. Write the code for full Adder by using
all different types of modeling.
3. What is the difference between inter and intra assignment delay? Explain with example.
4. Write a Verilog module for a 2:1 multiplexer in 4 different ways?
5. What is the difference between function and task?
6. Write the function for:
a) Factorial of user define number?
b) To check the number is even or not?
Section C: Problem Solving/Design Questions
[10 Marks Each]
1. Write a code for a 4-bit Ripple Carry Adder in Verilog by using generate block.
2. What is the purpose of if-else and case statement in Verilog? Provide an example of a 4-to-2
encoder using the case statement and if-else statement, and explain the difference.
3. Write the code for priority encoder by using casex and casez, and explain the difference also in
terms of outputs and with one is better in this scenario.
4. Write a Verilog code to implement a D Flip-Flop with asynchronous reset and synchronous D flip
flop and explain the difference also.
5. Design a 4-bit synchronous counter in Verilog. The counter should count from 0 to 15 and then
wrap around to 0. Provide the Verilog code and explain your design choices.
