CST 307: MICROPROCESSORS

AND MICROCONTROLLERS
MODULE 1
 Module 1 - Outline
1. Evolution of microprocessors
2. Overview of 8085 microprocessor
3. 8085 microprocessor - Architecture
4. 8086 Microprocessor - Architecture
5. Signals in 8086
6. Physical memory organization of 8086
7. Minimum and maximum mode 8086 system and timings
8. Comparison of 8086 and 8088
9. Machine language Instruction format
 Microprocessors
● A microprocessor is a computer processor where the data processing
logic and control is included on a single integrated circuit, or a small
number of integrated circuits.

● The microprocessor contains the arithmetic, logic, and control

circuitry required to perform the functions of a computer’s central
processing unit.
Microprocessor is a controlling unit of a micro-computer,
fabricated on a small chip capable of performing ALU (Arithmetic
Logical Unit) operations and communicating with the other
devices connected to it.
 Microcontrollers
● It is a compact integrated circuit designed to perform a
specific task in an embedded system.

● A typical microcontroller includes a processor, memory and

input/output (I/O) peripherals on a single chip.
Differences between Microprocessors
and Microcontrollers - Application

● Microprocessor: not used for any specific task.

Differences between Microprocessors
and Microcontrollers - Application
● Microcontroller: designed to perform specific task.
Differences between Microprocessors and
Microcontrollers - Internal structure

● Microprocessor
Differences between Microprocessors and
Microcontrollers - Internal structure
● Microcontroller
 Differences between Microprocessors and
Microcontrollers

Microprocessor Microcontroller
1) Not dedicated for specific task 1) Dedicated for specific task
Eg: personal computer Eg: washing machine

2) Memory and I/O are external to 2) All in a single small chip

CPU
3) System size is large 3) Small system size

4) High cost 4) Low cost

 Evolution of microprocessors
4-bit Microprocessors
● The first microprocessor was introduced in 1971 by Intel Corp.
● It was named Intel 4004 as it was a 4 bit processor.
● It could perform simple arithmetic and logic operations such as addition,
subtraction, boolean AND and boolean OR.
● The enhanced version of 4004 was Intel 4040. Some other 4 bit
processors are International’s PPS4 and Toshiba's T3472.

8-bit Microprocessors
● The first 8 bit microprocessor which could perform arithmetic and logic
operations on 8 bit words was introduced in 1973 again by Intel.
● This was Intel 8008 and was later followed by an improved version, Intel
8088.
● Some other 8 bit processors are Zilog-80 and Motorola M6800.
 Evolution of microprocessors
16-bit Microprocessors
● The 8-bit processors were followed by 16 bit processors. They are
Intel 8086 and 80286.

32-bit Microprocessors
● The 32 bit microprocessors were introduced by several companies but
the most popular one is Intel 80386.
● The 32-bit 80486 is the next evolutionary step up from the 80386.

64 bit Microprocessor
● AMD Opteron, Athlon 64
● Intel Celeron and Pentium 4
● Intel Pentium dual-core, Core i3, Core i5, and Core i7 processors.
 How does a Microprocessor Work?
The microprocessor follows a sequence:
Fetch, Decode, and then Execute.
➔ Initially instructions are stored in the memory in a sequential order.
➔The microprocessor fetches instructions from the memory, then
decodes it and executes those instructions till STOP instruction is
reached.
➔ Later, it sends the result in binary to the output port. Between these
processes, the register stores the temporarily data and ALU performs the
computing functions.
 List of Terms Used in a Microprocessor
Here is a list of some of the frequently used terms in a microprocessor −

Instruction Set
− It is the set of instructions that the microprocessor can understand.

Bandwidth
− It is the number of bits processed/transmitted in a single instruction.
Cont……
Clock Speed - It determines the number of operations per second the
processor can perform. It is expressed in megahertz (MHz) or gigahertz
(GHz). It is also known as Clock Rate.
Word Length - It depends upon the width of internal data bus, registers,
ALU, etc. An 8- bit microprocessor can process 8-bit data at a time. The word
length ranges from 4 bits to 64 bits depending upon the type of the
microcomputer.
Data Types − The microprocessor has multiple data type formats like binary,
BCD, ASCII, signed and unsigned numbers.
 8085 microprocessor
The salient features of 8085 μp are:

● It is a 8 bit microprocessor.
● It has 16-bit address bus and hence can address up to 216 =65536 bytes
(64KB) memory locations through A0 − A15.
● Data bus is a group of 8 lines D0 – D7.
● It supports external interrupt request.
● A 16 bit program counter (PC).
● A 16 bit stack pointer (SP).
● Six 8-bit general purpose register arranged in pairs: BC, DE, HL.
● It requires a signal +5V power supply and operates
at 3.2 MHZ single phase clock.
● It is enclosed with 40 pins DIP(Dual in line package).
Internal Architecture of 8085
8085 is pronounced as "eighty-eighty-five" microprocessor.
It is an 8-bit microprocessor designed by Intel in 1976 using NMOS
technology.
It has the following configuration −
❖ 8-bit data bus.
❖ 16-bit address bus, which can address upto 64KB.
❖ A 16-bit program counter.
❖ A 16-bit stack pointer.
❖ Six 8-bit registers arranged in pairs: BC, DE, HL.
❖ Requires +5V supply to operate at 3.2 MHZ single phase clock.
8085 consists of the following functional units:
Arithmetic and logic unit
● As the name suggests, it performs arithmetic and logical operations like
Addition, Subtraction, AND, OR, etc. on 8-bit data.
● It uses data from memory, registers and from Accumulator to perform
operations.
● The results of the arithmetic and logical operations are stored in the
accumulator.
 Registers
Registers are classified into Two
1. The 8085 has six General Purpose registers
2. Specific Purpose Registers

Program Counter (PC) Memory Address Register (MAR)

Stack Pointer (SP) Temporary Register

Flags/Status Registers (SR) Memory Buffer Register (MBR)

Instruction Register (IR)

General-purpose registers:
★ The 8085 has six general-purpose registers to store 8-bit data; these are identified
as B, C, D, E, H and L.
★ They can be combined as register pairs - BC, DE and HL to perform some 16-bit
operations.
★ The programmer can use these registers to store or copy data into the register by
using data copy instructions.

Accumulator
★ 8-bit register that is a part of ALU.
★ This register is used to store 8-bit data and to perform arithmetic and logical
operations.
★ The result of an operation is stored in the accumulator.
★ The accumulator is also identified as register A.
Program counter
● It is a 16-bit register
● The function of the program counter is to point to the memory address
from which the next byte is to be fetched.
● When a byte is being fetched, the program counter is automatically
incremented by one to point to the next memory location.
Stack pointer - It is also a 16-bit register works like stack, which is always
incremented/decremented by 2 during PUSH & POP operations.
Temporary register- It is an 8-bit register, which holds the temporary
data of arithmetic and logical operations.
Eg: W & Z registers
Flag/Status register
● It is an 8-bit register having five 1-bit flip-flops, which holds either 0
or 1 depending upon the result stored in the accumulator.
● These are the set of 5 flip-flops −
Sign (S) Auxiliary Carry (AC)
Zero (Z) Carry (C)
Parity (P)

bit position are shown in the following table −

Instruction register - It is an 8-bit register. When an instruction is fetched from
memory then it is stored in the Instruction register.

Instruction decoder - decodes the information present in the Instruction register.

Timing and control unit- It provides timing and control signal to the
microprocessor to perform operations.

Following are the timing and control signals, which control external and
internal circuits −

Control Signals: READY, RD’, WR’, ALE

Status Signals: S0, S1, IO/M’

DMA Signals: HOLD, HLDA

RESET Signals: RESET IN, RESET OUT

Interrupt control
It controls the interrupts during a process.When a microprocessor is executing a
main program and whenever an interrupt occurs, the microprocessor shifts the
control from the main program to process the incoming request. After the request
is completed, the control goes back to the main program.
There are 5 interrupt signals in 8085 microprocessor: INTR, RST 7.5, RST
6.5, RST 5.5, TRAP.
Serial Input/Output control - It controls the serial data communication by using
these two instructions:
SID (Serial input data) and SOD (Serial output data).
Address buffer and address-data buffer - The content stored in the stack
pointer and program counter is loaded into the address buffer and
address-data buffer to communicate with the CPU.
Address bus and data bus
Data bus carries the data to be stored. It is bidirectional.
Whereas address bus carries the location to where it should be stored and
it is unidirectional.
It is used to transfer the data & Address I/O devices.
Limitations of 8085 Microprocessor
● Low speed
● Low memory addressing capability
● Limited number general purpose registers
● Less powerful instruction set
 8086 Microprocessor
● 16-bit microprocessors.
● Designed by Intel.
● 20-bit address bus can access 220 = 1, 048, 576 = 1MB of memory location.
● 16-bit data bus.
● Registers are 16 bit, but it can also access as 8 bit.
● 40 Pin DIP, Operates in two modes: Minimum & Maximum
● It requires +5V power supply.
● More powerful instruction set.
● The peripheral chips designed earlier for 8085 were compatible with
microprocessor 8086 with slight or no modifications.
Difference between 8085 and 8086 Microprocessor
8086 Internal Architecture
8086 Microprocessor is divided into two functional units:

1. BIU (Bus Interface Unit)

2. EU (Execution Unit)

• Dividing the work between these two units speed up processing.

• The BIU handles all transfers of data and addresses on the buses for
the execution unit.

• The execution unit of the 8086 tells the BIU where to fetch
instructions or data from.
BUS INTERFACE UNIT (BIU)
This unit fetches instructions, reads data from memory and ports, and writes data to
memory and i/o ports. The BIU interfaces the 8086 to the outside world. It contains:
Instruction Queue:
● The BIU Instruction Queue is a FIFO group of registers in which up to
6 bytes of instruction code are pre fetched from memory ahead of
time. This is done in order to speed up program execution by
overlapping instruction fetch with execution.
● When EU executes instructions and is ready for its next instruction, then it
simply reads the instruction from this instruction queue resulting in
increased execution speed.
● Fetching the next instruction while the current instruction executes is
called pipelining.
● Pre fetched Instruction byte Queue.
Bus Control Circuitry
● The Bus Control Circuitry logic of a BIU generates all the bus control signals
such as READ, WRITE for memory or I/O.
MRDC, MWTC, IORC and IOWC - active low signals

Instruction pointer
● 16 bit register
● Store the address of next instruction to be executed.
Segment registers:

● A segment register contains the addresses of instructions and data in

memory which are used by the processor to access memory locations.
● The BIU has four 16 bit segment registers.
Note :Memory is logically divided into different segments. CODE ,DATA ,STACK,
EXTRA segments
● Each segment is 64K bytes in size and is addressable by one of the segment
registers .
● It points to the starting address of a memory segment currently being used.
Code Segment Register (CS) Stack Segment Register (SS)
Data Segment Register (DS) Extra Segment Register (ES)
CODE SEGMENT – is a section of memory that holds the programs used by the
processor.

DATA SEGMENT – is a section of memory that contains most data used by a program.

STACK SEGMENT – is a section of memory used as stack .

EXTRA SEGMENT – is an additional data segment that is used by some of the string

instructions to hold destination data.

Code segment register ,data segment register ,stack segment register and extra
segment register defines the starting address of code segment ,data segment,
stack segment and extra segment respectively .
The pointers IP, BP and SP usually contain offsets within the code, data and stack
segments .
OFFSET addresses are used to locate different instruction or data inside a segment .
CS IP - Instruction address
SS SP or BP - stack address
DS BX or DI ,or SI or 16 bit number - Data address
ES DI - String destination address

Address Generator

Generate 20 bit physical address from 16 bit segment register & 16 bit offset register.
Real Mode Addressing

● The complete available physical memory (1 MB) may be divided into 16 logical
segments , each segment is 64 KB in size and is addressed by one of the segment
registers.
● 16 bit contents of the segment register point to the starting location of a particular
segment .
● The actual memory location within a segment can be identified with the help of
16-bit long offset address .
Note : each segment is 64 KB in size ,
64KB=64 X 1024=65536 Bytes in each segment and the address range
from 0 to 65535 ie 0000H to FFFFH .
Physical address calculation from Segment and Offset address
➢Content of the segment register is shifted left bit-wise four times , then content of the offset
register is added to it ,hence produce a 20 –bit physical address .
eg : Segment address ---1005 H ( in binary :0001 0000 0000 0101 )
Offset address --- 5555 H ( in binary : 0101 0101 0101 0101)
After shifting 4 bit positions to the left : 0001 0000 0000 0101 0000
0001 0000 0000 0101 0000 +
0101 0101 0101 0101
0001 0101 0101 1010 0101 0R
Physical address : 155A5
Advantages of using Segmented memory Scheme :

1) Allow the memory capacity to be 1 MB , although the actual address to be

handled are of 16-bit size.
2) Placing of Code ,Data and Stack portions of the same program in different
parts of memory for data and code protection.
3) Permits a program and its data to be put into different areas of memory
each time the program is executed , i.e . Provision for relocation may be done.
EXECUTION UNIT(EU)

Function
● Fetches Instruction & data from BIU
● Decode Instruction
● Execute Instruction
● EU Contain control circuitry to perform various internal operations
Functional part
● General purpose register
● Pointers & index register
● ALU
● Flag register
● Timing & Control unit
● Decoding Unit
EXECUTION UNIT(EU)

● A decoder translates instructions fetched from memory into a series of actions

which the EU carries out.

● The control circuitry which directs internal operations by deriving the

necessary control signals to execute the instruction.
● 16 bit arithmetic logic unit which can add, subtract, AND, OR, XOR, increment,
decrement, complement or shift binary numbers.
● Contains register set of 8086 except segment registers and IP.
● 16 –bit flag register reflects the results of execution by the ALU.
● EU may pass the results to the BIU for storing them in memory.
General purpose registers
● General purpose registers are used to store temporary data within the
microprocessor.
● There are 8 general purpose registers in 8086 microprocessor.
● The registers AX,BX,CX, and DX are the general purpose 16-bit register.
● Each of these 16-bit registers are further subdivided into 8-bit registers,
i.e., AH, AL, BH, BL, CH, CL, DH, and DL.
● These registers can be used individually to store 8-bit data and can be used in
pairs to store 16 bit data.
● The valid register pairs are AH and AL, BH and BL, CH and CL, and DH and
DL.
Pointers & index register
Two Pointers & Two index register
● Stack Pointer(SP) & Base Pointer (BP)
● Source Index (SI) & Destination Index (DI)

ALU
● 16 bit ALU
● It handles all arithmetic and logical operations
● 8 bit & 16 bit ALU Operation can perform
Flag Register
● It is a 16-bit register that behaves like a flip-flop
● It has 9 flags and they are divided into 2 groups
● Six Conditional Flags and Three Control Flags.
Timing and control unit
● CU & EU direct all internal operations also responsible for generation of
control signal.
Decoding unit
● Decodes the opcode bytes fetched from the instruction byte & send to
control circuit for execution.
 Register Organization of 8086
● 8086 has a powerful set of registers containing general purpose and special
purpose registers.
● All the registers of 8086 are 16-bit registers.
● The general purpose registers, can be used either 8-bit registers or 16-bit
registers.
● The general purpose registers are either used for holding the data,
variables and intermediate results temporarily or for other purpose like
counter or for storing offset address for some particular addressing modes
etc.
● The special purpose registers are used as segment registers, pointers, index
registers or as offset storage registers for particular addressing modes. The
index and pointer registers are collectively called as special purpose
registers.
We will categorize the register set into four groups.

❖ General purpose registers

❖ Segment registers
❖ Flag register
❖ Pointers and index registers
General Purpose Registers
The registers AX, BX, CX, and DX are the general 16-bit registers.
AX (Accumulator)
● AX is 16-bit accumulator and it is divided in to two eight bit registers AH and AL.
● The lower 8-bits of AX are designated to use as AL and higher 8-bits as AH.
● AL can be used as an 8-bit accumulator for 8-bit operation.
● It is generally used for arithmetical and logical instructions.
ADD AX,AX (AX = AX + AX)

BX (Base Register)
● BX is a 16 bit register, BL indicates the lower 8-bits of BX and BH indicates the higher 8-bits
of BX.
● The register BX is used as address register to form physical address in case of certain
addressing modes. It is used to store the value of the offset.
CX (Count Register)
● The register CX(CL & CH) is used default counter in case of string and loop
instructions.
● Count register can also be used as a counter in string manipulation and shift/rotate
instruction.
MOV CX, 0005
LOOP
DX (Data Register)
● DX(DL & DH) register is a general purpose register which may be used as an implicit
operand or destination in case of a few instructions.
● DX holds a part of the result from multiplication or part of the dividend before
division.
● Data register can also be used as a port number in I/O operations.
MUL BX (DX AX = AX * BX)
Pointer Registers
8086 microprocessor contains three pointer registers.
SP (Stack Pointer): Stack Pointer register points the program stack that means SP
stores the base address of the Stack Segment.

BP (Base Pointer): Base Pointer register also points the same stack segment. Unlike
SP, we can use BP to access data in the other segments also.

IP (Instruction Pointer): The Instruction Pointer is a register that holds the address
of the next instruction to be fetched from memory. It contains the offset of the next word
of instruction code instead of its actual address
Index Registers
The index registers are particularly useful for string manipulation.
SI (Source Index)
● SI is a 16-bit register. Source Index Register is used to point the memory locations in
the data segment.
● It is used in the pointer addressing of data and as a source in some string-related
operations.
DI (Destination Index)
● DI is a 16-bit register. This is destination index register performs the same function
as SI.
● It is used in the pointer addressing of data and as a destination in some string-related
operations.
● Its offset is relative to the extra segment.
Segment Registers
1 megabyte of memory is divided into 16 logical segments.
Each segment contains 64 Kbytes of memory. There are four segment
registers to access this 1 megabyte of memory.
● Code segment register (CS): is used for addressing memory location in
the code segment of the memory, where the executable program is
stored.
● Data segment register (DS): points to the data segment of the memory
where the data is stored.
● Extra Segment Register (ES): also refers to a segment in the memory
which is another data segment in the memory.
● Stack Segment Register (SS): is used for addressing stack segment of
the memory. The stack segment is that segment of memory which is
used to store stack data.
Flag Registers
A flag is a flip-flop which indicates some conditions produced by the execution of an
instruction or controls certain operations of the EU .
8086 has a 16 –bit flag register which is divided into two parts .
1) Condition code or Status flags
● Lower byte of the 16-bit flag register along with the overflow flag .
● This part of the flag register reflects the results of the operations performed by ALU .
2) Control flag register
● Higher byte of the flag register.
● It contains three flags – Interrupt flag , Trap flag and Direction flag .
A 16 –bit flag register in the EU contains nine active flags.
Flag register is 16-bit register with only nine bits that are implemented.

● Six Conditional Flags

● Three Control Flags
Six Conditional Flags
1. SF (Sign Flag): This flag represents sign of the result.
0-Result is Positive
1-Result is Negative
2. ZF (Zero Flag): ZF is set if the result produced by an instruction is
zero. Otherwise, ZF is reset.
3. PF (Parity Flag): This flag is set to 1, if the lower byte of the result
contains even number of 1’s.
0- Odd parity
1- Even parity
4. CF (Carry Flag) : This flag is set, when there is a carry out of MSB in
case of addition or borrow in case of subtraction.
0- No Carry/ Borrow
1- Carry/ Borrow
5. AC (Auxiliary Carry Flag): This is set when there is a carry from the
lowest nibble or borrow for the lowest nibble.
6. OF(Overflow Flag): This flag is set, if an overflow occurs, i.e, if the
result of a signed operation is large enough to accommodate in a
destination register.
Three Control Flags
1. TF (Trap Flag): This trap flag is used for on-chip debugging. When
T=1, it will work in a single step mode. After each instruction, one
internal interrupt is generated.
2. IF (Interrupt Flag): If this flag is set, the maskable interrupts are
recognized by the CPU, otherwise they are ignored.
3. DF (Direction Flag): This is used by string manipulation instructions.
0- The string is processed beginning from the lowest address to the
highest address, i.e., auto incrementing mode.
1- The string is processed from the highest address towards the
lowest address, i.e., auto decrement mode mode.
 8086 Signals (Pin Diagram)
● Some of the pins serve a particular function in minimum mode
(single processor mode) and others function in maximum mode
(multiprocessor mode) configuration.
The 8086 signals can be categorized in three groups.
★ Signals having common functions in minimum as well as
maximum mode
★ Signals which having special functions in minimum mode
★ Signals having special functions in maximum mode.
Intel 8086 is a 16-bit microprocessor.

● It is available in 40 pin DIP chip.

● It uses 5V DC supply at VCC pin 40, and uses ground at VSS pin 1 and 20 for
its operation.
● The 8086 uses 20-line address bus.
● It has a 16-line data bus.
● The 20 lines of the address bus operate in multiplexed mode
● The 16-low order address bus lines have been multiplexed with data and 4
high-order address bus lines have been multiplexed with status signals.
● A16/S3,A17/S4,A18/S5,A19/S6. These are the 4 address/status lines.
● Clock signal is provided through Pin-19. It provides timing to the processor
for operations.
Signals common for minimum & maximum mode
VCC: +5V DC power supply for the operation of the internal circuit.
GND:ground for the internal circuit
CLK-Clock Input
● The clock input provides the basic timing for processor operation and bus
control activity.
● The range of frequency for different 8086 versions is from 5 MHz to 10MHz.
● Its an asymmetric square wave with 33% duty cycle.
RESET
● This input causes the processor to terminate the current activity and start
execution from FFFF0H.
● This signal is active high for the first 4 clock cycles to RESET the
microprocessor.
● It restarts execution when the RESET returns low.
Address/Data Line
● AD15–AD0 [ Pin 2- 16 &39]
● These are 16 address/data bus.
● The pins have dual function. They act as address bus during the first part of
machine cycle and as data bus in the later part.
● Time multiplexed address & data bus
● AD0 − AD7 carries low order byte data and AD8 − AD15 carries higher order
byte data.
● During the first clock cycle, it carries 16-bit address and after that it carries
16-bit data.
Address/status bus(A19/S6,A18/S5,A17/S4,A16/S3)
● These are the time multiplexed address and status lines.
● During T1 clock state higher order 4 bit address will be available on
these lines.
● During T2,T3,T4, & Tw clock state status signal will be available on
these lines
● The S3 and S4 together indicate which segment register is presently
being used for memory accesses
● S5: The status of the interrupt flag
● S6: is always low
Bus High Enable/Status(BHE/S7)
● Used to indicate the transfer of data using higher order data bus D8-D15.
● This signal is low during the first clock cycle, thereafter it is active.
● The status information is available during T2, T3 and T4
● It is Multiplexed with status signal S7
MN/MX
● The logic level at this pin decides whether the processor is to operate in
either minimum (single processor) or maximum (multiprocessor) Mode.
When it is high it works in the minimum mode.
When it is low it works in the maximum mode
RD-Read
● Indicates the peripherals that the processor is performing a memory
or I/O read operation
● It is active low and shows the state for T2, T3, TW of any read cycle.
● The signal remains tristated during the ’hold acknowledge’.
TEST

● This input is examined by a ’WAIT’ instruction.

● If the TEST input goes low, execution will continue, else, the processor
remains in an idle state.

READY
● This is the acknowledgement from the slow devices or memory that they
have completed the data transfer.
● The signal is active high.
INTR-Interrupt Request
● INTR is a maskable interrupt input. When this INTR become high ,check the
value of status pin s5 (which hold the value of flag bit IF), if S5=1 then
process the interrupt service request ,otherwise mask the interrupt request .
● If any interrupt request is pending, the processor enters the interrupt
acknowledge cycle.
● This can be internally masked by resetting the interrupt enable flag.
NMI

● NMI is the non maskable interrupt input , processor directly go for an

interrupt service routine when this NMI pin become high.
● NMI is not maskable internally by software.
 Signals having special functions in
minimum mode
INTA(Interrupt Acknowledge): When it goes low, it means that the processor
has accepted the interrupt.
ALE(Address latch Enable): This output signal indicates the availability of the
valid address on the address/data lines, and is connected to latch enable input
of latches.
DEN(Data Enable)
● This signal indicates the availability of valid data over the address/data
lines.
● It is used to enable the transreceivers (bidirectional buffers) to separate the
data from the multiplexed address/data signal.
● It is active from the middle of T2 until the middle of T4.
DT/ R Data Transmit/Receive
● This output is used to decide the direction of data flow through the
transreceivers (bidirectional buffers).
When the processor sends out data, this signal is high
when the processor is receiving data, this signal is low.
M/ IO Memory/IO
● Used to distinguish between m/y & i/o operations
When it is low, it indicates the CPU is having an I/O operation
when it is high, it indicates that the CPU is having a memory
operation.
Write(WR): Used to denote a m/y or i/o write operations
HOLD, HLDA-Hold/Hold Acknowledge:
HOLD indicates to the processor that external device are requesting to
access the Address/data bus.
HOLDA acknowledges the HOLD signal.
 Signals having special functions in
maximum mode
QS1, QS0-Queue Status:
These lines give information about the status of the instruction queue
S0 , S1 , S2 -These are the status signals that provide the status of operation
LOCK:
● Its an active low pin.
● It indicates that other system bus masters have not been allowed to gain
control of the system bus while LOCK’ is active low(0).
Request/Grant signals RQ/GT0,RQ/GT1:
● These pins are used by other local bus masters, in maximum mode, to
request the processor to release the local bus at the end of the
processor’s current bus cycle.
● Each of the pin is bi-directional.
● RQ’/GT0′ have higher priority than RQ’/GT1′.
Non-Overlapping and overlapping memory segments
Non - Overlapping
● A segment starts at a particular address and its maximum size can be 64 KB.
● Next segment will start after the 64KB of the first segment.
Overlapping
● A segment starts at a particular address and its maximum size can be 64 KB.
● If another segment starts before this 64KB locations of the first segment ,the 2
segments are said to be overlapping Segments.
● The area of memory from the start of the second segment to the possible end of
the first segment is called an overlapped segment area.
 Physical memory organization of 8086
● The Total memory (1MB) of 8086 is arranged in two banks.
● An odd bank and an even bank
● Both the banks have equal no. of locations.
● The odd bank contains odd numbered memory Locations. It is known as
upper bank (512 Kbytes)
● The even bank contains only even numbered memory Locations. It is
known as lower bank (512 Kbytes)
● Byte data with even address is transferred on D7 to D0 and byte data (Lower
byte of data (D0-D7) present in Even bank )
● with odd address is transferred on D15 to D8 (Higher byte of data (D8-D15)
present in Odd bank) .
● The processor provides two enable signals, BHE and A0 for selecting of either
even or odd or both the banks.
D8-D15
★ If all the address locations are present sequentially in memory then minimum 2
memory cycles needed for the completion of one memory access (16 bits of data)
operation.
★ In a 16 bit read or write operation both of these bytes will be read or written in a
single machine cycle.
★ Speed up the memory access operation.
★ The processor provide two enable signals, BHE & A0 for selection of either even
or odd or both.

.
 Minimum Mode 8086 System

● The microprocessor 8086 is operated in minimum mode by

strapping its MN/MX pin to logic 1.
● In this mode, all the control signals are given out by the
microprocessor chip itself.
● There is a single microprocessor in the minimum mode system.
● The remaining components in the system are latches,
transreceivers, clock generator, memory and I/O devices.
● Chip selection logic may be required for selecting memory or I/O
devices.
8086 works in Minimum Mode, when MN/ MX = 1.
➢ Minimum Mode, 8086 is the only processor in the system.
➢ Clock is provided by the 8284 clock generator, it provides CLK, RESET and READY
input to 8086.
➢ The ALE of 8086 is connected to STB of the latch. The ALE for this latch is given by
8086 itself.
➢ When theALE input is high ,address from the multiplexed address/data bus is
latched into 8282 8-bit latch.
➢ Three such latches are needed, as address bus is 20-bit.
➢ The data bus is driven through 8286 8-bit trans-receiver.
➢ Two such trans-receivers are needed, as the data bus is 16-bit.
➢ The trans-receivers are enabled through the DEN signal, while the direction of data
is controlled by the DT/ R’ signal.
.
Latches are used for separating the valid address from the multiplexed
address/data signals and are controlled by the ALE signal generated by
8086.
Transreceivers are required to separate the valid data from the time
multiplexed address/data signals and are controlled by two signals
namely, DEN and DT/R.
The DT/R signal indicates the direction of data & DEN signal
indicates the valid data is available on the data bus.
A system may contain I/O devices for communication with processor as
well as some special purpose I/O devices.
The trans-receivers are enabled through the DEN signal, while the
direction of data is controlled by the DT/ R’ signal.
➢ DEN’ is connected to OE’ and DT/ R’ is connected to T . Both DEN’
and DT/ R’ are given by 8086 itself .
➢ Control signals for all operations are generated by decoding M/IO ,
RD and WR signals.
➢ Bus Request is done using the HOLD and HLDA signals
➢ INTA’ is given by 8086, in response to an interrupt on INTR line.
● The working of the minimum mode configuration system can be
better described in terms of the timing diagrams rather than
qualitatively describing the operations.
● The opcode fetch and read cycles are similar. Hence the timing
diagram can be categorized in two parts,
1. Timing diagram for read cycle
2. Timing diagram for write cycle
MINIMUM MODE TIMING DIAGRAM – READ CYCLE
● The read cycle begins in T1 with the assertion of address latch enable (ALE) signal
and also M / IO signal.
● During the negative going edge of this signal, the valid address is latched on the local
bus.
● The BHE and A0 signals address low, high or both bytes.
● From T1 to T4, the M/IO signal indicates a memory or I/O operation.
● At T2, the address is removed from the local bus and is sent to the output. The bus is
then tristated. The read (RD) control signal is also activated in T2.
● The read (RD) signal causes the address device to enable its data bus drivers. After RD
goes low, the valid data is available on the data bus.
● The addressed device will drive the READY line high. When the processor returns the
read signal to high level, the addressed device will again tri state its bus drivers.
MINIMUM MODE TIMING DIAGRAM – WRITE CYCLE
● A write cycle also begins with the assertion of ALE and the emission of the
address.
● The M/IO signal is again asserted to indicate a memory or I/O operation.
● In T2, after sending the address in T1, the processor sends the data to be written
to the addressed location.
● The data remains on the bus until middle of T4 state. The WR becomes active at
the beginning of T2 (unlike RD is somewhat delayed in T2 to provide time for
floating).
● The BHE and A0 signals are used to select the proper byte or bytes of memory or
I/O word to be read or write.
● The M/IO, RD and WR signals indicate the type of data transfer as specified in
table below.
 Minimum Mode 8086 System
Hold Response sequence
● The HOLD signal indicates to the processor that external devices are requesting
to access the address/data buses.
● The HOLD pin is checked at leading edge of each clock pulse.
● If it is received active by the processor before T4 of the previous cycle or during
T1 state of the current cycle, the CPU activates HLDA in the next clock cycle
and for succeeding bus cycles, the bus will be given to another requesting
master.
● The control of the bus is not regained by the processor until the requesting
master does not drop the HOLD pin low. When the request is dropped by the
requesting master, the HLDA is dropped by the processor at the trailing edge of
the next clock.
 MAXIMUM MODE OPERATION
● In the maximum mode, there may be more than one microprocessor in the
system configuration.
● The maximum mode operation is selected by connecting the MN/MX pin to
ground.
● In this mode, the processor derives the status signal S2, S1, S0.
● The bus controller derives the control signal using this status information.
● In the maximum mode, the control signals are generated by external Bus
controller 8288.
 MAXIMUM MODE OPERATION
● In the maximum mode additional circuitry (Bus controller) is required to translate
the control signals.
● The additional circuitry converts the status signals (S2-S0) into the I/O and
memory transfer signals.
● It also generates the control signals required to direct the data flow and for
controlling 8282 latches and 8286 transceivers.
● 8288 is able to originate the address latch enable signal to the 8282 latch and
direction signals to the 8286 transceivers.
● It also decodes the S2-S0 signals to generate MRDC, MWTC, IORC, IOWC,
MCE/PDEN, AEN, IOB, CEN, AIOWC, and AMWC signals.
● The basic function of the bus controller chip IC 8288, is to derive control signals
like RD and WR, DEN, DT/R, ALE etc. using the information by the processor on
the status lines.
● The bus controller chip has input lines S2, S1, S0 and CLK. These inputs to 8288
are driven by CPU.
● It derives the outputs ALE, DEN, DT/R, MRDC, MWTC, AMWC, IORC, IOWC and
AIOWC.
● INTA pin used to issue two interrupt acknowledge pulses to the interrupt
controller or to an interrupting device.
● IORC, IOWC are I/O read command and I/O write command signals respectively.
These signals enable an IO interface to read or write the data from or to the
address port.
● The MRDC, MWTC are memory read command and memory write command
signals respectively and may be used as memory read or write signals.
● For both of these write command signals, the advanced signals namely AIOWC and
AMWTC are available.
● They are serve the same purpose, but are activated one clock cycle earlier than the
IOWC and MWTC signal respectively.
● The maximum mode system timing diagrams are also divided in two portions as
read (input) and write (output) timing diagrams.

● The address/data and address/status timings are similar to the minimum

mode.

● ALE is asserted in T1, just like minimum mode. The only difference lies in the
status signals used and the available control and advanced command signals.
S0,S1,S2 are set at the beginning of bus cycle.8288 bus controller will
output a pulse as on the ALE and apply a required signal to its DT /R pin
during T1.
Comparison of 8086 and 8088
1.Calculate the physical address of an instruction and the
contents of segment registers are given as
CS:1150H,
DS: 2010H,
SS: 3025H, and
IP: 5670H
ANSWER : 16B70H
2.The value of Code Segment (CS) Register is 3054H
and the value of different registers is as follows:
BX: 4025H ,
IP: 1580H ,
DI: 5467H.
Calculate the physical address of the next instruction
to be fetched.
ANSWER : 31AC0H
1. Find the physical address of the memory locations
referred by the following instructions,
when DS = 2AD3H, CS=0058H, BX=0312H, SI=0058H.
i) MOV AL, [BX]
ii) MOV [BX][SI]15H, DL
 ANSWER
i) when DS=2AD3H, SI=0058H, BX=0312H MOV AL, [BX] ---
physical address 2B042 H
ii) MOV [BX][SI]15h, DL --- physical address 2B0AFH